| blob | 7f2f24a29e6c178d4f5a08c6748e1b093fa21112 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada 375 family SoC
4 *
5 * Copyright (C) 2014 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
9 */
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/phy/phy.h>
15 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
21 model = "Marvell Armada 375 family SoC";
22 compatible = "marvell,armada375";
24 aliases {
25 gpio0 = &gpio0;
26 gpio1 = &gpio1;
27 gpio2 = &gpio2;
28 serial0 = &uart0;
29 serial1 = &uart1;
30 };
32 clocks {
33 /* 1 GHz fixed main PLL */
34 mainpll: mainpll {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <1000000000>;
38 };
39 /* 25 MHz reference crystal */
40 refclk: oscillator {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
44 };
45 };
47 cpus {
48 #address-cells = <1>;
49 #size-cells = <0>;
50 enable-method = "marvell,armada-375-smp";
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a9";
55 reg = <0>;
56 };
57 cpu1: cpu@1 {
58 device_type = "cpu";
59 compatible = "arm,cortex-a9";
60 reg = <1>;
61 };
62 };
64 pmu {
65 compatible = "arm,cortex-a9-pmu";
66 interrupts-extended = <&mpic 3>;
67 };
69 soc {
70 compatible = "marvell,armada375-mbus", "simple-bus";
71 #address-cells = <2>;
72 #size-cells = <1>;
73 controller = <&mbusc>;
74 interrupt-parent = <&gic>;
75 pcie-mem-aperture = <0xe0000000 0x8000000>;
76 pcie-io-aperture = <0xe8000000 0x100000>;
78 bootrom {
79 compatible = "marvell,bootrom";
80 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
81 };
83 devbus_bootcs: devbus-bootcs {
84 compatible = "marvell,mvebu-devbus";
85 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
86 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
87 #address-cells = <1>;
88 #size-cells = <1>;
89 clocks = <&coreclk 0>;
90 status = "disabled";
91 };
93 devbus_cs0: devbus-cs0 {
94 compatible = "marvell,mvebu-devbus";
95 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
96 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 clocks = <&coreclk 0>;
100 status = "disabled";
101 };
103 devbus_cs1: devbus-cs1 {
104 compatible = "marvell,mvebu-devbus";
105 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
106 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
107 #address-cells = <1>;
108 #size-cells = <1>;
109 clocks = <&coreclk 0>;
110 status = "disabled";
111 };
113 devbus_cs2: devbus-cs2 {
114 compatible = "marvell,mvebu-devbus";
115 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
116 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
117 #address-cells = <1>;
118 #size-cells = <1>;
119 clocks = <&coreclk 0>;
120 status = "disabled";
121 };
123 devbus_cs3: devbus-cs3 {
124 compatible = "marvell,mvebu-devbus";
125 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
126 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
127 #address-cells = <1>;
128 #size-cells = <1>;
129 clocks = <&coreclk 0>;
130 status = "disabled";
131 };
133 internal-regs {
134 compatible = "simple-bus";
135 #address-cells = <1>;
136 #size-cells = <1>;
137 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
139 L2: cache-controller@8000 {
140 compatible = "arm,pl310-cache";
141 reg = <0x8000 0x1000>;
142 cache-unified;
143 cache-level = <2>;
144 arm,double-linefill-incr = <0>;
145 arm,double-linefill-wrap = <0>;
146 arm,double-linefill = <0>;
147 prefetch-data = <1>;
148 };
150 scu: scu@c000 {
151 compatible = "arm,cortex-a9-scu";
152 reg = <0xc000 0x58>;
153 };
155 timer0: timer@c600 {
156 compatible = "arm,cortex-a9-twd-timer";
157 reg = <0xc600 0x20>;
158 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
159 clocks = <&coreclk 2>;
160 };
162 gic: interrupt-controller@d000 {
163 compatible = "arm,cortex-a9-gic";
164 #interrupt-cells = <3>;
165 #size-cells = <0>;
166 interrupt-controller;
167 reg = <0xd000 0x1000>,
168 <0xc100 0x100>;
169 };
171 mdio: mdio@c0054 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "marvell,orion-mdio";
175 reg = <0xc0054 0x4>;
176 clocks = <&gateclk 19>;
177 };
179 /* Network controller */
180 ethernet: ethernet@f0000 {
181 compatible = "marvell,armada-375-pp2";
182 reg = <0xf0000 0xa000>, /* Packet Processor regs */
183 <0xc0000 0x3060>, /* LMS regs */
184 <0xc4000 0x100>, /* eth0 regs */
185 <0xc5000 0x100>; /* eth1 regs */
186 clocks = <&gateclk 3>, <&gateclk 19>;
187 clock-names = "pp_clk", "gop_clk";
188 status = "disabled";
190 eth0: eth0 {
191 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
192 port-id = <0>;
193 status = "disabled";
194 };
196 eth1: eth1 {
197 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
198 port-id = <1>;
199 status = "disabled";
200 };
201 };
203 rtc: rtc@10300 {
204 compatible = "marvell,orion-rtc";
205 reg = <0x10300 0x20>;
206 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
207 };
209 spi0: spi@10600 {
210 compatible = "marvell,armada-375-spi",
211 "marvell,orion-spi";
212 reg = <0x10600 0x50>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 cell-index = <0>;
216 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&coreclk 0>;
218 status = "disabled";
219 };
221 spi1: spi@10680 {
222 compatible = "marvell,armada-375-spi",
223 "marvell,orion-spi";
224 reg = <0x10680 0x50>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227 cell-index = <1>;
228 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&coreclk 0>;
230 status = "disabled";
231 };
233 i2c0: i2c@11000 {
234 compatible = "marvell,mv64xxx-i2c";
235 reg = <0x11000 0x20>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&coreclk 0>;
240 status = "disabled";
241 };
243 i2c1: i2c@11100 {
244 compatible = "marvell,mv64xxx-i2c";
245 reg = <0x11100 0x20>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&coreclk 0>;
250 status = "disabled";
251 };
253 uart0: serial@12000 {
254 compatible = "snps,dw-apb-uart";
255 reg = <0x12000 0x100>;
256 reg-shift = <2>;
257 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
258 reg-io-width = <1>;
259 clocks = <&coreclk 0>;
260 status = "disabled";
261 };
263 uart1: serial@12100 {
264 compatible = "snps,dw-apb-uart";
265 reg = <0x12100 0x100>;
266 reg-shift = <2>;
267 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
268 reg-io-width = <1>;
269 clocks = <&coreclk 0>;
270 status = "disabled";
271 };
273 pinctrl: pinctrl@18000 {
274 compatible = "marvell,mv88f6720-pinctrl";
275 reg = <0x18000 0x24>;
277 i2c0_pins: i2c0-pins {
278 marvell,pins = "mpp14", "mpp15";
279 marvell,function = "i2c0";
280 };
282 i2c1_pins: i2c1-pins {
283 marvell,pins = "mpp61", "mpp62";
284 marvell,function = "i2c1";
285 };
287 nand_pins: nand-pins {
288 marvell,pins = "mpp0", "mpp1", "mpp2",
289 "mpp3", "mpp4", "mpp5",
290 "mpp6", "mpp7", "mpp8",
291 "mpp9", "mpp10", "mpp11",
292 "mpp12", "mpp13";
293 marvell,function = "nand";
294 };
296 sdio_pins: sdio-pins {
297 marvell,pins = "mpp24", "mpp25", "mpp26",
298 "mpp27", "mpp28", "mpp29";
299 marvell,function = "sd";
300 };
302 spi0_pins: spi0-pins {
303 marvell,pins = "mpp0", "mpp1", "mpp4",
304 "mpp5", "mpp8", "mpp9";
305 marvell,function = "spi0";
306 };
307 };
309 gpio0: gpio@18100 {
310 compatible = "marvell,orion-gpio";
311 reg = <0x18100 0x40>;
312 ngpios = <32>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
321 };
323 gpio1: gpio@18140 {
324 compatible = "marvell,orion-gpio";
325 reg = <0x18140 0x40>;
326 ngpios = <32>;
327 gpio-controller;
328 #gpio-cells = <2>;
329 interrupt-controller;
330 #interrupt-cells = <2>;
331 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
335 };
337 gpio2: gpio@18180 {
338 compatible = "marvell,orion-gpio";
339 reg = <0x18180 0x40>;
340 ngpios = <3>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
346 };
348 systemc: system-controller@18200 {
349 compatible = "marvell,armada-375-system-controller";
350 reg = <0x18200 0x100>;
351 };
353 gateclk: clock-gating-control@18220 {
354 compatible = "marvell,armada-375-gating-clock";
355 reg = <0x18220 0x4>;
356 clocks = <&coreclk 0>;
357 #clock-cells = <1>;
358 };
360 usbcluster: usb-cluster@18400 {
361 compatible = "marvell,armada-375-usb-cluster";
362 reg = <0x18400 0x4>;
363 #phy-cells = <1>;
364 };
366 mbusc: mbus-controller@20000 {
367 compatible = "marvell,mbus-controller";
368 reg = <0x20000 0x100>, <0x20180 0x20>;
369 };
371 mpic: interrupt-controller@20a00 {
372 compatible = "marvell,mpic";
373 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
374 #interrupt-cells = <1>;
375 #size-cells = <1>;
376 interrupt-controller;
377 msi-controller;
378 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
379 };
381 timer1: timer@20300 {
382 compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
383 reg = <0x20300 0x30>, <0x21040 0x30>;
384 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
385 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
386 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
387 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
388 <&mpic 5>,
389 <&mpic 6>;
390 clocks = <&coreclk 0>, <&refclk>;
391 clock-names = "nbclk", "fixed";
392 };
394 watchdog: watchdog@20300 {
395 compatible = "marvell,armada-375-wdt";
396 reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
397 clocks = <&coreclk 0>, <&refclk>;
398 clock-names = "nbclk", "fixed";
399 };
401 cpurst: cpurst@20800 {
402 compatible = "marvell,armada-370-cpu-reset";
403 reg = <0x20800 0x10>;
404 };
406 coherencyfab: coherency-fabric@21010 {
407 compatible = "marvell,armada-375-coherency-fabric";
408 reg = <0x21010 0x1c>;
409 };
411 usb0: usb@50000 {
412 compatible = "marvell,orion-ehci";
413 reg = <0x50000 0x500>;
414 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
415 clocks = <&gateclk 18>;
416 phys = <&usbcluster PHY_TYPE_USB2>;
417 phy-names = "usb";
418 status = "disabled";
419 };
421 usb1: usb@54000 {
422 compatible = "marvell,orion-ehci";
423 reg = <0x54000 0x500>;
424 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&gateclk 26>;
426 status = "disabled";
427 };
429 usb2: usb@58000 {
430 compatible = "marvell,armada-375-xhci";
431 reg = <0x58000 0x20000>,<0x5b880 0x80>;
432 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&gateclk 16>;
434 phys = <&usbcluster PHY_TYPE_USB3>;
435 phy-names = "usb";
436 status = "disabled";
437 };
439 xor0: xor@60800 {
440 compatible = "marvell,orion-xor";
441 reg = <0x60800 0x100
442 0x60A00 0x100>;
443 clocks = <&gateclk 22>;
444 status = "okay";
446 xor00 {
447 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
448 dmacap,memcpy;
449 dmacap,xor;
450 };
451 xor01 {
452 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
453 dmacap,memcpy;
454 dmacap,xor;
455 dmacap,memset;
456 };
457 };
459 xor1: xor@60900 {
460 compatible = "marvell,orion-xor";
461 reg = <0x60900 0x100
462 0x60b00 0x100>;
463 clocks = <&gateclk 23>;
464 status = "okay";
466 xor10 {
467 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
468 dmacap,memcpy;
469 dmacap,xor;
470 };
471 xor11 {
472 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
473 dmacap,memcpy;
474 dmacap,xor;
475 dmacap,memset;
476 };
477 };
479 cesa: crypto@90000 {
480 compatible = "marvell,armada-375-crypto";
481 reg = <0x90000 0x10000>;
482 reg-names = "regs";
483 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&gateclk 30>, <&gateclk 31>,
486 <&gateclk 28>, <&gateclk 29>;
487 clock-names = "cesa0", "cesa1",
488 "cesaz0", "cesaz1";
489 marvell,crypto-srams = <&crypto_sram0>,
490 <&crypto_sram1>;
491 marvell,crypto-sram-size = <0x800>;
492 };
494 sata: sata@a0000 {
495 compatible = "marvell,armada-370-sata";
496 reg = <0xa0000 0x5000>;
497 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&gateclk 14>, <&gateclk 20>;
499 clock-names = "0", "1";
500 status = "disabled";
501 };
503 nand_controller: nand-controller@d0000 {
504 compatible = "marvell,armada370-nand-controller";
505 reg = <0xd0000 0x54>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&gateclk 11>;
510 status = "disabled";
511 };
513 sdio: mvsdio@d4000 {
514 compatible = "marvell,orion-sdio";
515 reg = <0xd4000 0x200>;
516 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&gateclk 17>;
518 bus-width = <4>;
519 cap-sdio-irq;
520 cap-sd-highspeed;
521 cap-mmc-highspeed;
522 status = "disabled";
523 };
525 thermal: thermal@e8078 {
526 compatible = "marvell,armada375-thermal";
527 reg = <0xe8078 0x4>, <0xe807c 0x8>;
528 status = "okay";
529 };
531 coreclk: mvebu-sar@e8204 {
532 compatible = "marvell,armada-375-core-clock";
533 reg = <0xe8204 0x04>;
534 #clock-cells = <1>;
535 };
537 coredivclk: corediv-clock@e8250 {
538 compatible = "marvell,armada-375-corediv-clock";
539 reg = <0xe8250 0xc>;
540 #clock-cells = <1>;
541 clocks = <&mainpll>;
542 clock-output-names = "nand";
543 };
544 };
546 pciec: pcie@82000000 {
547 compatible = "marvell,armada-370-pcie";
548 status = "disabled";
549 device_type = "pci";
551 #address-cells = <3>;
552 #size-cells = <2>;
554 msi-parent = <&mpic>;
555 bus-range = <0x00 0xff>;
557 ranges =
558 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
559 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
560 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
561 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
562 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
563 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
565 pcie0: pcie@1,0 {
566 device_type = "pci";
567 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
568 reg = <0x0800 0 0 0 0>;
569 #address-cells = <3>;
570 #size-cells = <2>;
571 #interrupt-cells = <1>;
572 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
573 0x81000000 0 0 0x81000000 0x1 0 1 0>;
574 bus-range = <0x00 0xff>;
575 interrupt-map-mask = <0 0 0 0>;
576 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
577 marvell,pcie-port = <0>;
578 marvell,pcie-lane = <0>;
579 clocks = <&gateclk 5>;
580 status = "disabled";
581 };
583 pcie1: pcie@2,0 {
584 device_type = "pci";
585 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
586 reg = <0x1000 0 0 0 0>;
587 #address-cells = <3>;
588 #size-cells = <2>;
589 #interrupt-cells = <1>;
590 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
591 0x81000000 0 0 0x81000000 0x2 0 1 0>;
592 bus-range = <0x00 0xff>;
593 interrupt-map-mask = <0 0 0 0>;
594 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
595 marvell,pcie-port = <0>;
596 marvell,pcie-lane = <1>;
597 clocks = <&gateclk 6>;
598 status = "disabled";
599 };
601 };
603 crypto_sram0: sa-sram0 {
604 compatible = "mmio-sram";
605 reg = <MBUS_ID(0x09, 0x09) 0 0x800>;
606 clocks = <&gateclk 30>;
607 #address-cells = <1>;
608 #size-cells = <1>;
609 ranges = <0 MBUS_ID(0x09, 0x09) 0 0x800>;
610 };
612 crypto_sram1: sa-sram1 {
613 compatible = "mmio-sram";
614 reg = <MBUS_ID(0x09, 0x05) 0 0x800>;
615 clocks = <&gateclk 31>;
616 #address-cells = <1>;
617 #size-cells = <1>;
618 ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
619 };
620 };
621 };