arch/arm/boot/dts/armada-385-clearfog-gtr.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * Device Tree file for Clearfog GTR machines rev 1.0 (88F6825)
   4  *
   5  *  Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
   6  */
   7
   8 /*
   9         SERDES mapping -
  10         0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
  11         1. 6141 switch (2.5Gbps capable)
  12         2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
  13         3. USB 3.0 Host
  14         4. mini PCIe CON2 - PCIe2
  15         5. SFP connector, or optionally SGMII Ethernet 1512 PHY
  16
  17         USB 2.0 mapping -
  18         0. USB 2.0 - 0 USB pins header CON12
  19         1. USB 2.0 - 1 mini PCIe CON2
  20         2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
  21
  22         Pin mapping -
  23         0,1 - console UART
  24         2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
  25               front panel and PSE controller
  26         4,5 - MDC/MDIO
  27         6..17 - RGMII
  28         18 - Topaz switch reset (active low)
  29         19 - 1512 phy reset
  30         20 - 1512 phy reset (eth2, optional)
  31         21,28,37,38,39,40 - SD0
  32         22 - USB 3.0 current limiter enable (active high)
  33         24 - SFP TX fault (input active high)
  34         25 - SFP present (input active low)
  35         26,27 - I2C1 - connected to SFP
  36         29 - Fan PWM
  37         30 - CON4 mini PCIe wifi disable
  38         31 - CON3 mini PCIe wifi disable
  39         32 - Fuse programming power toggle (1.8v)
  40         33 - CON4 mini PCIe reset
  41         34 - CON2 mini PCIe wifi disable
  42         35 - CON3 mini PCIe reset
  43         36 - Rear button (GPIO active low)
  44         41 - CON1 front panel connector
  45         42 - Front LED1, or front panel CON1
  46         43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
  47         44 - CON2 mini PCIe reset
  48         45 - TPM PIRQ signal, or front panel CON1
  49         46 - SFP TX disable
  50         47 - Control isolation of boot sensitive SAR signals
  51         48 - PSE reset
  52         49 - PSE OSS signal
  53         50 - PSE interrupt
  54         52 - Front LED2, or front panel
  55         53 - Front button
  56         54 - SFP LOS (input active high)
  57         55 - Fan sense
  58         56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
  59         59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
  60 */
  61
  62 /dts-v1/;
  63 #include <dt-bindings/input/input.h>
  64 #include <dt-bindings/gpio/gpio.h>
  65 #include <dt-bindings/leds/common.h>
  66 #include "armada-385.dtsi"
  67
  68 / {
  69         compatible = "marvell,armada385", "marvell,armada380";
  70
  71         aliases {
  72                 /* So that mvebu u-boot can update the MAC addresses */
  73                 ethernet1 = &eth0;
  74                 ethernet2 = &eth1;
  75                 ethernet3 = &eth2;
  76                 i2c0 = &i2c0;
  77                 i2c1 = &i2c1;
  78         };
  79
  80         chosen {
  81                 stdout-path = "serial0:115200n8";
  82         };
  83
  84         memory {
  85                 device_type = "memory";
  86                 reg = <0x00000000 0x10000000>; /* 256 MB */
  87         };
  88
  89         reg_3p3v: regulator-3p3v {
  90                 compatible = "regulator-fixed";
  91                 regulator-name = "3P3V";
  92                 regulator-min-microvolt = <3300000>;
  93                 regulator-max-microvolt = <3300000>;
  94                 regulator-always-on;
  95         };
  96
  97         reg_5p0v: regulator-5p0v {
  98                 compatible = "regulator-fixed";
  99                 regulator-name = "5P0V";
 100                 regulator-min-microvolt = <5000000>;
 101                 regulator-max-microvolt = <5000000>;
 102                 regulator-always-on;
 103         };
 104
 105         v_usb3_con: regulator-v-usb3-con {
 106                 compatible = "regulator-fixed";
 107                 gpio = <&gpio0 22 GPIO_ACTIVE_LOW>;
 108                 pinctrl-names = "default";
 109                 pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
 110                 regulator-max-microvolt = <5000000>;
 111                 regulator-min-microvolt = <5000000>;
 112                 regulator-name = "v_usb3_con";
 113                 vin-supply = <&reg_5p0v>;
 114                 regulator-boot-on;
 115                 regulator-always-on;
 116         };
 117
 118         soc {
 119                 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
 120                           MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
 121                           MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
 122                           MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
 123                           MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
 124
 125                 internal-regs {
 126
 127                         rtc@a3800 {
 128                                 status = "okay";
 129                         };
 130
 131                         i2c@11000 { /* ROM, temp sensor and front panel */
 132                                 pinctrl-0 = <&i2c0_pins>;
 133                                 pinctrl-names = "default";
 134                                 status = "okay";
 135                         };
 136
 137                         i2c@11100 { /* SFP (CON5/CON6) */
 138                                 pinctrl-0 = <&cf_gtr_i2c1_pins>;
 139                                 pinctrl-names = "default";
 140                                 status = "okay";
 141                         };
 142
 143                         pinctrl@18000 {
 144                                 cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
 145                                         marvell,pins = "mpp18";
 146                                         marvell,function = "gpio";
 147                                 };
 148
 149                                 cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
 150                                         marvell,pins = "mpp22";
 151                                         marvell,function = "gpio";
 152                                 };
 153
 154                                 cf_gtr_fan_pwm: cf-gtr-fan-pwm {
 155                                         marvell,pins = "mpp23";
 156                                         marvell,function = "gpio";
 157                                 };
 158
 159                                 cf_gtr_i2c1_pins: i2c1-pins {
 160                                         /* SFP */
 161                                         marvell,pins = "mpp26", "mpp27";
 162                                         marvell,function = "i2c1";
 163                                 };
 164
 165                                 cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
 166                                         marvell,pins = "mpp21", "mpp28",
 167                                                        "mpp37", "mpp38",
 168                                                        "mpp39", "mpp40";
 169                                         marvell,function = "sd0";
 170                                 };
 171
 172                                 cf_gtr_isolation_pins: cf-gtr-isolation-pins {
 173                                         marvell,pins = "mpp47";
 174                                         marvell,function = "gpio";
 175                                 };
 176
 177                                 cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
 178                                         marvell,pins = "mpp48";
 179                                         marvell,function = "gpio";
 180                                 };
 181
 182                                 cf_gtr_spi1_cs_pins: spi1-cs-pins {
 183                                         marvell,pins = "mpp59";
 184                                         marvell,function = "spi1";
 185                                 };
 186
 187                                 cf_gtr_front_button_pins: cf-gtr-front-button-pins {
 188                                         marvell,pins = "mpp53";
 189                                         marvell,function = "gpio";
 190                                 };
 191
 192                                 cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
 193                                         marvell,pins = "mpp36";
 194                                         marvell,function = "gpio";
 195                                 };
 196                         };
 197
 198                         sdhci@d8000 {
 199                                 bus-width = <4>;
 200                                 no-1-8-v;
 201                                 non-removable;
 202                                 pinctrl-0 = <&cf_gtr_sdhci_pins>;
 203                                 pinctrl-names = "default";
 204                                 status = "okay";
 205                                 vmmc = <&reg_3p3v>;
 206                                 wp-inverted;
 207                         };
 208
 209                         usb@58000 {
 210                                 status = "okay";
 211                         };
 212
 213                         usb3@f0000 {
 214                                 status = "okay";
 215                         };
 216
 217                         usb3@f8000 {
 218                                 vbus-supply = <&v_usb3_con>;
 219                                 status = "okay";
 220                         };
 221                 };
 222
 223                 pcie {
 224                         status = "okay";
 225                         /*
 226                          * The PCIe units are accessible through
 227                          * the mini-PCIe connectors on the board.
 228                          */
 229                         pcie@1,0 {
 230                                 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
 231                                 status = "okay";
 232                         };
 233
 234                         pcie@2,0 {
 235                                 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
 236                                 status = "okay";
 237                         };
 238
 239                         pcie@3,0 {
 240                                 reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
 241                                 status = "okay";
 242                         };
 243                 };
 244         };
 245
 246         sfp0: sfp {
 247                 compatible = "sff,sfp";
 248                 i2c-bus = <&i2c1>;
 249                 los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
 250                 mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
 251                 tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 252         };
 253
 254         gpio-keys {
 255                 compatible = "gpio-keys";
 256                 pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
 257                 pinctrl-names = "default";
 258
 259                 button_0 {
 260                         label = "Rear Button";
 261                         gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 262                         linux,can-disable;
 263                         linux,code = <BTN_0>;
 264                 };
 265
 266                 button_1 {
 267                         label = "Front Button";
 268                         gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
 269                         linux,can-disable;
 270                         linux,code = <BTN_1>;
 271                 };
 272         };
 273
 274         gpio-leds {
 275                 compatible = "gpio-leds";
 276
 277                 led1 {
 278                         function = LED_FUNCTION_CPU;
 279                         color = <LED_COLOR_ID_GREEN>;
 280                         gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
 281                 };
 282
 283                 led2 {
 284                         function = LED_FUNCTION_HEARTBEAT;
 285                         color = <LED_COLOR_ID_GREEN>;
 286                         gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
 287                 };
 288         };
 289 };
 290
 291 &bm {
 292         status = "okay";
 293 };
 294
 295 &bm_bppi {
 296         status = "okay";
 297 };
 298
 299 &eth0 {
 300         /* ethernet@70000 */
 301         pinctrl-0 = <&ge0_rgmii_pins>;
 302         pinctrl-names = "default";
 303         phy = <&phy_dedicated>;
 304         phy-mode = "rgmii-id";
 305         buffer-manager = <&bm>;
 306         bm,pool-long = <0>;
 307         bm,pool-short = <1>;
 308         status = "okay";
 309 };
 310
 311 &eth1 {
 312         /* ethernet@30000 */
 313         bm,pool-long = <2>;
 314         bm,pool-short = <1>;
 315         buffer-manager = <&bm>;
 316         phys = <&comphy1 1>;
 317         phy-mode = "2500base-x";
 318         status = "okay";
 319
 320         fixed-link {
 321                 speed = <2500>;
 322                 full-duplex;
 323         };
 324 };
 325
 326 &eth2 {
 327         /* ethernet@34000 */
 328         bm,pool-long = <3>;
 329         bm,pool-short = <1>;
 330         buffer-manager = <&bm>;
 331         managed = "in-band-status";
 332         phys = <&comphy5 1>;
 333         phy-mode = "sgmii";
 334         sfp = <&sfp0>;
 335         status = "okay";
 336 };
 337
 338 &mdio {
 339         pinctrl-names = "default";
 340         pinctrl-0 = <&mdio_pins>;
 341         status = "okay";
 342
 343         phy_dedicated: ethernet-phy@0 {
 344                 /*
 345                  * Annoyingly, the marvell phy driver configures the LED
 346                  * register, rather than preserving reset-loaded setting.
 347                  * We undo that rubbish here.
 348                  */
 349                 marvell,reg-init = <3 16 0 0x1017>;
 350                 reg = <0>;
 351         };
 352 };
 353
 354 &uart0 {
 355         pinctrl-0 = <&uart0_pins>;
 356         pinctrl-names = "default";
 357         status = "okay";
 358 };
 359
 360 &spi1 {
 361         /*
 362          * CS0: W25Q32 flash
 363          */
 364         pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
 365         pinctrl-names = "default";
 366         status = "okay";
 367
 368         spi-flash@0 {
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 compatible = "w25q32", "jedec,spi-nor";
 372                 reg = <0>; /* Chip select 0 */
 373                 spi-max-frequency = <3000000>;
 374                 status = "okay";
 375         };
 376 };
 377
 378 &i2c0 {
 379         pinctrl-0 = <&i2c0_pins>;
 380         pinctrl-names = "default";
 381         status = "okay";
 382
 383         /* U26 temperature sensor placed near SoC */
 384         temp1: nct75@4c {
 385                 compatible = "lm75";
 386                 reg = <0x4c>;
 387         };
 388
 389         /* U27 temperature sensor placed near RTC battery */
 390         temp2: nct75@4d {
 391                 compatible = "lm75";
 392                 reg = <0x4d>;
 393         };
 394
 395         /* 2Kb eeprom */
 396         eeprom@53 {
 397                 compatible = "atmel,24c02";
 398                 reg = <0x53>;
 399         };
 400 };
 401
 402 &ahci0 {
 403         status = "okay";
 404 };
 405
 406 &ahci1 {
 407         status = "okay";
 408 };
 409
 410 &gpio0 {
 411         pinctrl-0 = <&cf_gtr_fan_pwm>;
 412         pinctrl-names = "default";
 413
 414         wifi-disable {
 415                 gpio-hog;
 416                 gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
 417                 output-low;
 418                 line-name = "wifi-disable";
 419         };
 420 };
 421
 422 &gpio1 {
 423         pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
 424         pinctrl-names = "default";
 425
 426         lte-disable {
 427                 gpio-hog;
 428                 gpios = <2 GPIO_ACTIVE_LOW>;
 429                 output-low;
 430                 line-name = "lte-disable";
 431         };
 432
 433         /*
 434          * This signal, when asserted, isolates Armada 38x sample at reset pins
 435          * from control of external devices. Should be de-asserted after reset.
 436          */
 437         sar-isolation {
 438                 gpio-hog;
 439                 gpios = <15 GPIO_ACTIVE_LOW>;
 440                 output-low;
 441                 line-name = "sar-isolation";
 442         };
 443
 444         poe-reset {
 445                 gpio-hog;
 446                 gpios = <16 GPIO_ACTIVE_LOW>;
 447                 output-low;
 448                 line-name = "poe-reset";
 449         };
 450 };