| blob | e0b7c2099831272334d9db9d9d4cea6644f7de83 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Marvell Armada 39x family of SoCs.
4 *
5 * Copyright (C) 2015 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 */
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
13 #define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
15 / {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 model = "Marvell Armada 39x family SoC";
19 compatible = "marvell,armada390";
21 aliases {
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 };
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "marvell,armada-390-smp";
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 reg = <0>;
39 };
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a9";
43 reg = <1>;
44 };
45 };
47 pmu {
48 compatible = "arm,cortex-a9-pmu";
49 interrupts-extended = <&mpic 3>;
50 };
52 soc {
53 compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
54 "simple-bus";
55 #address-cells = <2>;
56 #size-cells = <1>;
57 controller = <&mbusc>;
58 interrupt-parent = <&gic>;
59 pcie-mem-aperture = <0xe0000000 0x8000000>;
60 pcie-io-aperture = <0xe8000000 0x100000>;
62 bootrom {
63 compatible = "marvell,bootrom";
64 reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
65 };
67 internal-regs {
68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
73 L2: cache-controller@8000 {
74 compatible = "arm,pl310-cache";
75 reg = <0x8000 0x1000>;
76 cache-unified;
77 cache-level = <2>;
78 arm,double-linefill-incr = <0>;
79 arm,double-linefill-wrap = <0>;
80 arm,double-linefill = <0>;
81 prefetch-data = <1>;
82 };
84 scu@c000 {
85 compatible = "arm,cortex-a9-scu";
86 reg = <0xc000 0x100>;
87 };
89 timer@c600 {
90 compatible = "arm,cortex-a9-twd-timer";
91 reg = <0xc600 0x20>;
92 interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
93 clocks = <&coreclk 2>;
94 };
96 gic: interrupt-controller@d000 {
97 compatible = "arm,cortex-a9-gic";
98 #interrupt-cells = <3>;
99 #size-cells = <0>;
100 interrupt-controller;
101 reg = <0xd000 0x1000>,
102 <0xc100 0x100>;
103 };
105 i2c0: i2c@11000 {
106 compatible = "marvell,mv64xxx-i2c";
107 reg = <0x11000 0x20>;
108 #address-cells = <1>;
109 #size-cells = <0>;
110 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
111 clocks = <&coreclk 0>;
112 status = "disabled";
113 };
115 i2c1: i2c@11100 {
116 compatible = "marvell,mv64xxx-i2c";
117 reg = <0x11100 0x20>;
118 #address-cells = <1>;
119 #size-cells = <0>;
120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&coreclk 0>;
122 status = "disabled";
123 };
125 i2c2: i2c@11200 {
126 compatible = "marvell,mv64xxx-i2c";
127 reg = <0x11200 0x20>;
128 #address-cells = <1>;
129 #size-cells = <0>;
130 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
131 clocks = <&coreclk 0>;
132 status = "disabled";
133 };
135 i2c3: i2c@11300 {
136 compatible = "marvell,mv64xxx-i2c";
137 reg = <0x11300 0x20>;
138 #address-cells = <1>;
139 #size-cells = <0>;
140 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
141 clocks = <&coreclk 0>;
142 status = "disabled";
143 };
145 uart0: serial@12000 {
146 compatible = "snps,dw-apb-uart";
147 reg = <0x12000 0x100>;
148 reg-shift = <2>;
149 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
150 reg-io-width = <1>;
151 clocks = <&coreclk 0>;
152 status = "disabled";
153 };
155 uart1: serial@12100 {
156 compatible = "snps,dw-apb-uart";
157 reg = <0x12100 0x100>;
158 reg-shift = <2>;
159 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
160 reg-io-width = <1>;
161 clocks = <&coreclk 0>;
162 status = "disabled";
163 };
165 uart2: serial@12200 {
166 compatible = "snps,dw-apb-uart";
167 reg = <0x12200 0x100>;
168 reg-shift = <2>;
169 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
170 reg-io-width = <1>;
171 clocks = <&coreclk 0>;
172 status = "disabled";
173 };
175 uart3: serial@12300 {
176 compatible = "snps,dw-apb-uart";
177 reg = <0x12300 0x100>;
178 reg-shift = <2>;
179 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
180 reg-io-width = <1>;
181 clocks = <&coreclk 0>;
182 status = "disabled";
183 };
185 pinctrl@18000 {
186 i2c0_pins: i2c0-pins {
187 marvell,pins = "mpp2", "mpp3";
188 marvell,function = "i2c0";
189 };
191 uart0_pins: uart0-pins {
192 marvell,pins = "mpp0", "mpp1";
193 marvell,function = "ua0";
194 };
196 uart1_pins: uart1-pins {
197 marvell,pins = "mpp19", "mpp20";
198 marvell,function = "ua1";
199 };
201 spi1_pins: spi1-pins {
202 marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
203 marvell,function = "spi1";
204 };
206 nand_pins: nand-pins {
207 marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
208 "mpp38", "mpp28", "mpp40", "mpp42",
209 "mpp35", "mpp36", "mpp25", "mpp30",
210 "mpp32";
211 marvell,function = "dev";
212 };
213 };
215 gpio0: gpio@18100 {
216 compatible = "marvell,orion-gpio";
217 reg = <0x18100 0x40>;
218 ngpios = <32>;
219 gpio-controller;
220 #gpio-cells = <2>;
221 interrupt-controller;
222 #interrupt-cells = <2>;
223 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
227 };
229 gpio1: gpio@18140 {
230 compatible = "marvell,orion-gpio";
231 reg = <0x18140 0x40>;
232 ngpios = <28>;
233 gpio-controller;
234 #gpio-cells = <2>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
241 };
243 system-controller@18200 {
244 compatible = "marvell,armada-390-system-controller",
245 "marvell,armada-370-xp-system-controller";
246 reg = <0x18200 0x100>;
247 };
249 gateclk: clock-gating-control@18220 {
250 compatible = "marvell,armada-390-gating-clock";
251 reg = <0x18220 0x4>;
252 clocks = <&coreclk 0>;
253 #clock-cells = <1>;
254 };
256 coreclk: mvebu-sar@18600 {
257 compatible = "marvell,armada-390-core-clock";
258 reg = <0x18600 0x04>;
259 #clock-cells = <1>;
260 };
262 mbusc: mbus-controller@20000 {
263 compatible = "marvell,mbus-controller";
264 reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
265 };
267 mpic: interrupt-controller@20a00 {
268 compatible = "marvell,mpic";
269 reg = <0x20a00 0x2d0>, <0x21070 0x58>;
270 #interrupt-cells = <1>;
271 #size-cells = <1>;
272 interrupt-controller;
273 msi-controller;
274 interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
275 };
277 timer@20300 {
278 compatible = "marvell,armada-380-timer",
279 "marvell,armada-xp-timer";
280 reg = <0x20300 0x30>, <0x21040 0x30>;
281 interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
282 <&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
283 <&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
284 <&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
285 <&mpic 5>,
286 <&mpic 6>;
287 clocks = <&coreclk 2>, <&coreclk 5>;
288 clock-names = "nbclk", "fixed";
289 };
291 watchdog@20300 {
292 compatible = "marvell,armada-380-wdt";
293 reg = <0x20300 0x34>, <0x20704 0x4>,
294 <0x18260 0x4>;
295 clocks = <&coreclk 2>, <&refclk>;
296 clock-names = "nbclk", "fixed";
297 };
299 cpurst@20800 {
300 compatible = "marvell,armada-370-cpu-reset";
301 reg = <0x20800 0x10>;
302 };
304 mpcore-soc-ctrl@20d20 {
305 compatible = "marvell,armada-380-mpcore-soc-ctrl";
306 reg = <0x20d20 0x6c>;
307 };
309 coherency-fabric@21010 {
310 compatible = "marvell,armada-380-coherency-fabric";
311 reg = <0x21010 0x1c>;
312 };
314 pmsu@22000 {
315 compatible = "marvell,armada-390-pmsu",
316 "marvell,armada-380-pmsu";
317 reg = <0x22000 0x1000>;
318 };
320 xor@60800 {
321 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
322 reg = <0x60800 0x100
323 0x60a00 0x100>;
324 clocks = <&gateclk 22>;
325 status = "okay";
327 xor00 {
328 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
329 dmacap,memcpy;
330 dmacap,xor;
331 };
332 xor01 {
333 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
334 dmacap,memcpy;
335 dmacap,xor;
336 dmacap,memset;
337 };
338 };
340 xor@60900 {
341 compatible = "marvell,armada-380-xor", "marvell,orion-xor";
342 reg = <0x60900 0x100
343 0x60b00 0x100>;
344 clocks = <&gateclk 28>;
345 status = "okay";
347 xor10 {
348 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
349 dmacap,memcpy;
350 dmacap,xor;
351 };
352 xor11 {
353 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
354 dmacap,memcpy;
355 dmacap,xor;
356 dmacap,memset;
357 };
358 };
360 rtc@a3800 {
361 compatible = "marvell,armada-380-rtc";
362 reg = <0xa3800 0x20>, <0x184a0 0x0c>;
363 reg-names = "rtc", "rtc-soc";
364 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
365 };
367 nand_controller: nand-controller@d0000 {
368 compatible = "marvell,armada370-nand-controller";
369 reg = <0xd0000 0x54>;
370 #address-cells = <1>;
371 #size-cells = <0>;
372 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
373 clocks = <&coredivclk 0>;
374 status = "disabled";
375 };
377 sdhci@d8000 {
378 compatible = "marvell,armada-380-sdhci";
379 reg-names = "sdhci", "mbus", "conf-sdio3";
380 reg = <0xd8000 0x1000>,
381 <0xdc000 0x100>,
382 <0x18454 0x4>;
383 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&gateclk 17>;
385 mrvl,clk-delay-cycles = <0x1F>;
386 status = "disabled";
387 };
389 coredivclk: clock@e4250 {
390 compatible = "marvell,armada-390-corediv-clock",
391 "marvell,armada-380-corediv-clock";
392 reg = <0xe4250 0xc>;
393 #clock-cells = <1>;
394 clocks = <&mainpll>;
395 clock-output-names = "nand";
396 };
398 thermal@e8078 {
399 compatible = "marvell,armada380-thermal";
400 reg = <0xe4078 0x4>, <0xe4074 0x4>;
401 status = "okay";
402 };
403 };
405 pcie {
406 compatible = "marvell,armada-370-pcie";
407 status = "disabled";
408 device_type = "pci";
410 #address-cells = <3>;
411 #size-cells = <2>;
413 msi-parent = <&mpic>;
414 bus-range = <0x00 0xff>;
416 ranges =
417 <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
418 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
419 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
420 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
421 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
422 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
423 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
424 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
425 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
426 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
427 0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
428 0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
430 /*
431 * This port can be either x4 or x1. When
432 * configured in x4 by the bootloader, then
433 * pcie@4,0 is not available.
434 */
435 pcie@1,0 {
436 device_type = "pci";
437 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
438 reg = <0x0800 0 0 0 0>;
439 #address-cells = <3>;
440 #size-cells = <2>;
441 #interrupt-cells = <1>;
442 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
443 0x81000000 0 0 0x81000000 0x1 0 1 0>;
444 bus-range = <0x00 0xff>;
445 interrupt-map-mask = <0 0 0 0>;
446 interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
447 marvell,pcie-port = <0>;
448 marvell,pcie-lane = <0>;
449 clocks = <&gateclk 8>;
450 status = "disabled";
451 };
453 /* x1 port */
454 pcie@2,0 {
455 device_type = "pci";
456 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
457 reg = <0x1000 0 0 0 0>;
458 #address-cells = <3>;
459 #size-cells = <2>;
460 #interrupt-cells = <1>;
461 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
462 0x81000000 0 0 0x81000000 0x2 0 1 0>;
463 bus-range = <0x00 0xff>;
464 interrupt-map-mask = <0 0 0 0>;
465 interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
466 marvell,pcie-port = <1>;
467 marvell,pcie-lane = <0>;
468 clocks = <&gateclk 5>;
469 status = "disabled";
470 };
472 /* x1 port */
473 pcie@3,0 {
474 device_type = "pci";
475 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
476 reg = <0x1800 0 0 0 0>;
477 #address-cells = <3>;
478 #size-cells = <2>;
479 #interrupt-cells = <1>;
480 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
481 0x81000000 0 0 0x81000000 0x3 0 1 0>;
482 bus-range = <0x00 0xff>;
483 interrupt-map-mask = <0 0 0 0>;
484 interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
485 marvell,pcie-port = <2>;
486 marvell,pcie-lane = <0>;
487 clocks = <&gateclk 6>;
488 status = "disabled";
489 };
491 /*
492 * x1 port only available when pcie@1,0 is
493 * configured as a x1 port
494 */
495 pcie@4,0 {
496 device_type = "pci";
497 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
498 reg = <0x2000 0 0 0 0>;
499 #address-cells = <3>;
500 #size-cells = <2>;
501 #interrupt-cells = <1>;
502 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
503 0x81000000 0 0 0x81000000 0x4 0 1 0>;
504 bus-range = <0x00 0xff>;
505 interrupt-map-mask = <0 0 0 0>;
506 interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
507 marvell,pcie-port = <3>;
508 marvell,pcie-lane = <0>;
509 clocks = <&gateclk 7>;
510 status = "disabled";
511 };
512 };
514 spi0: spi@10600 {
515 compatible = "marvell,armada-390-spi",
516 "marvell,orion-spi";
517 reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 cell-index = <0>;
521 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&coreclk 0>;
523 status = "disabled";
524 };
526 spi1: spi@10680 {
527 compatible = "marvell,armada-390-spi",
528 "marvell,orion-spi";
529 reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 cell-index = <1>;
533 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&coreclk 0>;
535 status = "disabled";
536 };
537 };
539 clocks {
540 /* 1 GHz fixed main PLL */
541 mainpll: mainpll {
542 compatible = "fixed-clock";
543 #clock-cells = <0>;
544 clock-frequency = <1000000000>;
545 };
547 /* 25 MHz reference crystal */
548 refclk: oscillator {
549 compatible = "fixed-clock";
550 #clock-cells = <0>;
551 clock-frequency = <25000000>;
552 };
553 };
554 };