| blob | 8ac5d1524a437ea42f83d93d53b381f0d536648a |
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DTS file for CSR SiRFatlas6 SoC
4 *
5 * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
6 */
8 / {
9 compatible = "sirf,atlas6";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&intc>;
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
18 cpu@0 {
19 reg = <0x0>;
20 d-cache-line-size = <32>;
21 i-cache-line-size = <32>;
22 d-cache-size = <32768>;
23 i-cache-size = <32768>;
24 /* from bootloader */
25 timebase-frequency = <0>;
26 bus-frequency = <0>;
27 clock-frequency = <0>;
28 clocks = <&clks 12>;
29 operating-points = <
30 /* kHz uV */
31 200000 1025000
32 400000 1025000
33 600000 1050000
34 800000 1100000
35 >;
36 clock-latency = <150000>;
37 };
38 };
40 arm-pmu {
41 compatible = "arm,cortex-a9-pmu";
42 interrupts = <29>;
43 };
45 axi {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <1>;
49 ranges = <0x40000000 0x40000000 0x80000000>;
51 intc: interrupt-controller@80020000 {
52 #interrupt-cells = <1>;
53 interrupt-controller;
54 compatible = "sirf,prima2-intc";
55 reg = <0x80020000 0x1000>;
56 };
58 sys-iobg {
59 compatible = "simple-bus";
60 #address-cells = <1>;
61 #size-cells = <1>;
62 ranges = <0x88000000 0x88000000 0x40000>;
64 clks: clock-controller@88000000 {
65 compatible = "sirf,atlas6-clkc";
66 reg = <0x88000000 0x1000>;
67 interrupts = <3>;
68 #clock-cells = <1>;
69 };
71 rstc: reset-controller@88010000 {
72 compatible = "sirf,prima2-rstc";
73 reg = <0x88010000 0x1000>;
74 #reset-cells = <1>;
75 };
77 rsc-controller@88020000 {
78 compatible = "sirf,prima2-rsc";
79 reg = <0x88020000 0x1000>;
80 };
82 cphifbg@88030000 {
83 compatible = "sirf,prima2-cphifbg";
84 reg = <0x88030000 0x1000>;
85 clocks = <&clks 42>;
86 };
87 };
89 mem-iobg {
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <1>;
93 ranges = <0x90000000 0x90000000 0x10000>;
95 memory-controller@90000000 {
96 compatible = "sirf,prima2-memc";
97 reg = <0x90000000 0x2000>;
98 interrupts = <27>;
99 clocks = <&clks 5>;
100 };
102 memc-monitor {
103 compatible = "sirf,prima2-memcmon";
104 reg = <0x90002000 0x200>;
105 interrupts = <4>;
106 clocks = <&clks 32>;
107 };
108 };
110 disp-iobg {
111 compatible = "simple-bus";
112 #address-cells = <1>;
113 #size-cells = <1>;
114 ranges = <0x90010000 0x90010000 0x30000>;
116 lcd@90010000 {
117 compatible = "sirf,prima2-lcd";
118 reg = <0x90010000 0x20000>;
119 interrupts = <30>;
120 clocks = <&clks 34>;
121 display=<&display>;
122 /* later transfer to pwm */
123 bl-gpio = <&gpio 7 0>;
124 default-panel = <&panel0>;
125 };
127 vpp@90020000 {
128 compatible = "sirf,prima2-vpp";
129 reg = <0x90020000 0x10000>;
130 interrupts = <31>;
131 clocks = <&clks 35>;
132 resets = <&rstc 6>;
133 };
134 };
136 graphics-iobg {
137 compatible = "simple-bus";
138 #address-cells = <1>;
139 #size-cells = <1>;
140 ranges = <0x98000000 0x98000000 0x8000000>;
142 graphics@98000000 {
143 compatible = "powervr,sgx510";
144 reg = <0x98000000 0x8000000>;
145 interrupts = <6>;
146 clocks = <&clks 32>;
147 };
148 };
150 graphics2d-iobg {
151 compatible = "simple-bus";
152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges = <0xa0000000 0xa0000000 0x8000000>;
156 ble@a0000000 {
157 compatible = "sirf,atlas6-ble";
158 reg = <0xa0000000 0x2000>;
159 interrupts = <5>;
160 clocks = <&clks 33>;
161 };
162 };
164 dsp-iobg {
165 compatible = "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0xa8000000 0xa8000000 0x2000000>;
170 dspif@a8000000 {
171 compatible = "sirf,prima2-dspif";
172 reg = <0xa8000000 0x10000>;
173 interrupts = <9>;
174 resets = <&rstc 1>;
175 };
177 gps@a8010000 {
178 compatible = "sirf,prima2-gps";
179 reg = <0xa8010000 0x10000>;
180 interrupts = <7>;
181 clocks = <&clks 9>;
182 resets = <&rstc 2>;
183 };
185 dsp@a9000000 {
186 compatible = "sirf,prima2-dsp";
187 reg = <0xa9000000 0x1000000>;
188 interrupts = <8>;
189 clocks = <&clks 8>;
190 resets = <&rstc 0>;
191 };
192 };
194 peri-iobg {
195 compatible = "simple-bus";
196 #address-cells = <1>;
197 #size-cells = <1>;
198 ranges = <0xb0000000 0xb0000000 0x180000>,
199 <0x56000000 0x56000000 0x1b00000>;
201 timer@b0020000 {
202 compatible = "sirf,prima2-tick";
203 reg = <0xb0020000 0x1000>;
204 interrupts = <0>;
205 clocks = <&clks 11>;
206 };
208 nand@b0030000 {
209 compatible = "sirf,prima2-nand";
210 reg = <0xb0030000 0x10000>;
211 interrupts = <41>;
212 clocks = <&clks 26>;
213 };
215 audio@b0040000 {
216 compatible = "sirf,prima2-audio";
217 reg = <0xb0040000 0x10000>;
218 interrupts = <35>;
219 clocks = <&clks 27>;
220 };
222 uart0: uart@b0050000 {
223 cell-index = <0>;
224 compatible = "sirf,prima2-uart";
225 reg = <0xb0050000 0x1000>;
226 interrupts = <17>;
227 fifosize = <128>;
228 clocks = <&clks 13>;
229 dmas = <&dmac1 5>, <&dmac0 2>;
230 dma-names = "rx", "tx";
231 };
233 uart1: uart@b0060000 {
234 cell-index = <1>;
235 compatible = "sirf,prima2-uart";
236 reg = <0xb0060000 0x1000>;
237 interrupts = <18>;
238 fifosize = <32>;
239 clocks = <&clks 14>;
240 dma-names = "no-rx", "no-tx";
241 };
243 uart2: uart@b0070000 {
244 cell-index = <2>;
245 compatible = "sirf,prima2-uart";
246 reg = <0xb0070000 0x1000>;
247 interrupts = <19>;
248 fifosize = <128>;
249 clocks = <&clks 15>;
250 dmas = <&dmac0 6>, <&dmac0 7>;
251 dma-names = "rx", "tx";
252 };
254 usp0: usp@b0080000 {
255 cell-index = <0>;
256 compatible = "sirf,prima2-usp";
257 reg = <0xb0080000 0x10000>;
258 interrupts = <20>;
259 fifosize = <128>;
260 clocks = <&clks 28>;
261 dmas = <&dmac1 1>, <&dmac1 2>;
262 dma-names = "rx", "tx";
263 };
265 usp1: usp@b0090000 {
266 cell-index = <1>;
267 compatible = "sirf,prima2-usp";
268 reg = <0xb0090000 0x10000>;
269 interrupts = <21>;
270 fifosize = <128>;
271 clocks = <&clks 29>;
272 dmas = <&dmac0 14>, <&dmac0 15>;
273 dma-names = "rx", "tx";
274 };
276 dmac0: dma-controller@b00b0000 {
277 cell-index = <0>;
278 compatible = "sirf,prima2-dmac";
279 reg = <0xb00b0000 0x10000>;
280 interrupts = <12>;
281 clocks = <&clks 24>;
282 #dma-cells = <1>;
283 };
285 dmac1: dma-controller@b0160000 {
286 cell-index = <1>;
287 compatible = "sirf,prima2-dmac";
288 reg = <0xb0160000 0x10000>;
289 interrupts = <13>;
290 clocks = <&clks 25>;
291 #dma-cells = <1>;
292 };
294 vip@b00C0000 {
295 compatible = "sirf,prima2-vip";
296 reg = <0xb00C0000 0x10000>;
297 clocks = <&clks 31>;
298 interrupts = <14>;
299 sirf,vip-dma-rx-channel = <16>;
300 };
302 spi0: spi@b00d0000 {
303 cell-index = <0>;
304 compatible = "sirf,prima2-spi";
305 reg = <0xb00d0000 0x10000>;
306 interrupts = <15>;
307 sirf,spi-num-chipselects = <1>;
308 dmas = <&dmac1 9>,
309 <&dmac1 4>;
310 dma-names = "rx", "tx";
311 #address-cells = <1>;
312 #size-cells = <0>;
313 clocks = <&clks 19>;
314 resets = <&rstc 26>;
315 status = "disabled";
316 };
318 spi1: spi@b0170000 {
319 cell-index = <1>;
320 compatible = "sirf,prima2-spi";
321 reg = <0xb0170000 0x10000>;
322 interrupts = <16>;
323 sirf,spi-num-chipselects = <1>;
324 dmas = <&dmac0 12>,
325 <&dmac0 13>;
326 dma-names = "rx", "tx";
327 #address-cells = <1>;
328 #size-cells = <0>;
329 clocks = <&clks 20>;
330 resets = <&rstc 27>;
331 status = "disabled";
332 };
334 i2c0: i2c@b00e0000 {
335 cell-index = <0>;
336 compatible = "sirf,prima2-i2c";
337 reg = <0xb00e0000 0x10000>;
338 interrupts = <24>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 clocks = <&clks 17>;
342 };
344 i2c1: i2c@b00f0000 {
345 cell-index = <1>;
346 compatible = "sirf,prima2-i2c";
347 reg = <0xb00f0000 0x10000>;
348 interrupts = <25>;
349 #address-cells = <1>;
350 #size-cells = <0>;
351 clocks = <&clks 18>;
352 };
354 tsc@b0110000 {
355 compatible = "sirf,prima2-tsc";
356 reg = <0xb0110000 0x10000>;
357 interrupts = <33>;
358 clocks = <&clks 16>;
359 };
361 gpio: pinctrl@b0120000 {
362 #gpio-cells = <2>;
363 #interrupt-cells = <2>;
364 compatible = "sirf,atlas6-pinctrl";
365 reg = <0xb0120000 0x10000>;
366 interrupts = <43 44 45 46 47>;
367 gpio-controller;
368 interrupt-controller;
370 lcd_16pins_a: lcd0@0 {
371 lcd {
372 sirf,pins = "lcd_16bitsgrp";
373 sirf,function = "lcd_16bits";
374 };
375 };
376 lcd_18pins_a: lcd0@1 {
377 lcd {
378 sirf,pins = "lcd_18bitsgrp";
379 sirf,function = "lcd_18bits";
380 };
381 };
382 lcd_24pins_a: lcd0@2 {
383 lcd {
384 sirf,pins = "lcd_24bitsgrp";
385 sirf,function = "lcd_24bits";
386 };
387 };
388 lcdrom_pins_a: lcdrom0@0 {
389 lcd {
390 sirf,pins = "lcdromgrp";
391 sirf,function = "lcdrom";
392 };
393 };
394 uart0_pins_a: uart0@0 {
395 uart {
396 sirf,pins = "uart0grp";
397 sirf,function = "uart0";
398 };
399 };
400 uart0_noflow_pins_a: uart0@1 {
401 uart {
402 sirf,pins = "uart0_nostreamctrlgrp";
403 sirf,function = "uart0_nostreamctrl";
404 };
405 };
406 uart1_pins_a: uart1@0 {
407 uart {
408 sirf,pins = "uart1grp";
409 sirf,function = "uart1";
410 };
411 };
412 uart2_pins_a: uart2@0 {
413 uart {
414 sirf,pins = "uart2grp";
415 sirf,function = "uart2";
416 };
417 };
418 uart2_noflow_pins_a: uart2@1 {
419 uart {
420 sirf,pins = "uart2_nostreamctrlgrp";
421 sirf,function = "uart2_nostreamctrl";
422 };
423 };
424 spi0_pins_a: spi0@0 {
425 spi {
426 sirf,pins = "spi0grp";
427 sirf,function = "spi0";
428 };
429 };
430 spi1_pins_a: spi1@0 {
431 spi {
432 sirf,pins = "spi1grp";
433 sirf,function = "spi1";
434 };
435 };
436 i2c0_pins_a: i2c0@0 {
437 i2c {
438 sirf,pins = "i2c0grp";
439 sirf,function = "i2c0";
440 };
441 };
442 i2c1_pins_a: i2c1@0 {
443 i2c {
444 sirf,pins = "i2c1grp";
445 sirf,function = "i2c1";
446 };
447 };
448 pwm0_pins_a: pwm0@0 {
449 pwm {
450 sirf,pins = "pwm0grp";
451 sirf,function = "pwm0";
452 };
453 };
454 pwm1_pins_a: pwm1@0 {
455 pwm {
456 sirf,pins = "pwm1grp";
457 sirf,function = "pwm1";
458 };
459 };
460 pwm2_pins_a: pwm2@0 {
461 pwm {
462 sirf,pins = "pwm2grp";
463 sirf,function = "pwm2";
464 };
465 };
466 pwm3_pins_a: pwm3@0 {
467 pwm {
468 sirf,pins = "pwm3grp";
469 sirf,function = "pwm3";
470 };
471 };
472 pwm4_pins_a: pwm4@0 {
473 pwm {
474 sirf,pins = "pwm4grp";
475 sirf,function = "pwm4";
476 };
477 };
478 gps_pins_a: gps@0 {
479 gps {
480 sirf,pins = "gpsgrp";
481 sirf,function = "gps";
482 };
483 };
484 vip_pins_a: vip@0 {
485 vip {
486 sirf,pins = "vipgrp";
487 sirf,function = "vip";
488 };
489 };
490 sdmmc0_pins_a: sdmmc0@0 {
491 sdmmc0 {
492 sirf,pins = "sdmmc0grp";
493 sirf,function = "sdmmc0";
494 };
495 };
496 sdmmc1_pins_a: sdmmc1@0 {
497 sdmmc1 {
498 sirf,pins = "sdmmc1grp";
499 sirf,function = "sdmmc1";
500 };
501 };
502 sdmmc2_pins_a: sdmmc2@0 {
503 sdmmc2 {
504 sirf,pins = "sdmmc2grp";
505 sirf,function = "sdmmc2";
506 };
507 };
508 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
509 sdmmc2_nowp {
510 sirf,pins = "sdmmc2_nowpgrp";
511 sirf,function = "sdmmc2_nowp";
512 };
513 };
514 sdmmc3_pins_a: sdmmc3@0 {
515 sdmmc3 {
516 sirf,pins = "sdmmc3grp";
517 sirf,function = "sdmmc3";
518 };
519 };
520 sdmmc5_pins_a: sdmmc5@0 {
521 sdmmc5 {
522 sirf,pins = "sdmmc5grp";
523 sirf,function = "sdmmc5";
524 };
525 };
526 i2s_mclk_pins_a: i2s_mclk@0 {
527 i2s_mclk {
528 sirf,pins = "i2smclkgrp";
529 sirf,function = "i2s_mclk";
530 };
531 };
532 i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
533 i2s_ext_clk_input {
534 sirf,pins = "i2s_ext_clk_inputgrp";
535 sirf,function = "i2s_ext_clk_input";
536 };
537 };
538 i2s_pins_a: i2s@0 {
539 i2s {
540 sirf,pins = "i2sgrp";
541 sirf,function = "i2s";
542 };
543 };
544 i2s_no_din_pins_a: i2s_no_din@0 {
545 i2s_no_din {
546 sirf,pins = "i2s_no_dingrp";
547 sirf,function = "i2s_no_din";
548 };
549 };
550 i2s_6chn_pins_a: i2s_6chn@0 {
551 i2s_6chn {
552 sirf,pins = "i2s_6chngrp";
553 sirf,function = "i2s_6chn";
554 };
555 };
556 ac97_pins_a: ac97@0 {
557 ac97 {
558 sirf,pins = "ac97grp";
559 sirf,function = "ac97";
560 };
561 };
562 nand_pins_a: nand@0 {
563 nand {
564 sirf,pins = "nandgrp";
565 sirf,function = "nand";
566 };
567 };
568 usp0_pins_a: usp0@0 {
569 usp0 {
570 sirf,pins = "usp0grp";
571 sirf,function = "usp0";
572 };
573 };
574 usp0_uart_nostreamctrl_pins_a: usp0@1 {
575 usp0 {
576 sirf,pins = "usp0_uart_nostreamctrl_grp";
577 sirf,function = "usp0_uart_nostreamctrl";
578 };
579 };
580 usp0_only_utfs_pins_a: usp0@2 {
581 usp0 {
582 sirf,pins = "usp0_only_utfs_grp";
583 sirf,function = "usp0_only_utfs";
584 };
585 };
586 usp0_only_urfs_pins_a: usp0@3 {
587 usp0 {
588 sirf,pins = "usp0_only_urfs_grp";
589 sirf,function = "usp0_only_urfs";
590 };
591 };
592 usp1_pins_a: usp1@0 {
593 usp1 {
594 sirf,pins = "usp1grp";
595 sirf,function = "usp1";
596 };
597 };
598 usp1_uart_nostreamctrl_pins_a: usp1@1 {
599 usp1 {
600 sirf,pins = "usp1_uart_nostreamctrl_grp";
601 sirf,function = "usp1_uart_nostreamctrl";
602 };
603 };
604 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
605 usb0_upli_drvbus {
606 sirf,pins = "usb0_upli_drvbusgrp";
607 sirf,function = "usb0_upli_drvbus";
608 };
609 };
610 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
611 usb1_utmi_drvbus {
612 sirf,pins = "usb1_utmi_drvbusgrp";
613 sirf,function = "usb1_utmi_drvbus";
614 };
615 };
616 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
617 usb1_dp_dn {
618 sirf,pins = "usb1_dp_dngrp";
619 sirf,function = "usb1_dp_dn";
620 };
621 };
622 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
623 uart1_route_io_usb1 {
624 sirf,pins = "uart1_route_io_usb1grp";
625 sirf,function = "uart1_route_io_usb1";
626 };
627 };
628 warm_rst_pins_a: warm_rst@0 {
629 warm_rst {
630 sirf,pins = "warm_rstgrp";
631 sirf,function = "warm_rst";
632 };
633 };
634 pulse_count_pins_a: pulse_count@0 {
635 pulse_count {
636 sirf,pins = "pulse_countgrp";
637 sirf,function = "pulse_count";
638 };
639 };
640 cko0_pins_a: cko0@0 {
641 cko0 {
642 sirf,pins = "cko0grp";
643 sirf,function = "cko0";
644 };
645 };
646 cko1_pins_a: cko1@0 {
647 cko1 {
648 sirf,pins = "cko1grp";
649 sirf,function = "cko1";
650 };
651 };
652 };
654 pwm@b0130000 {
655 compatible = "sirf,prima2-pwm";
656 reg = <0xb0130000 0x10000>;
657 clocks = <&clks 21>;
658 };
660 efusesys@b0140000 {
661 compatible = "sirf,prima2-efuse";
662 reg = <0xb0140000 0x10000>;
663 clocks = <&clks 22>;
664 };
666 pulsec@b0150000 {
667 compatible = "sirf,prima2-pulsec";
668 reg = <0xb0150000 0x10000>;
669 interrupts = <48>;
670 clocks = <&clks 23>;
671 };
673 pci-iobg {
674 compatible = "sirf,prima2-pciiobg", "simple-bus";
675 #address-cells = <1>;
676 #size-cells = <1>;
677 ranges = <0x56000000 0x56000000 0x1b00000>;
679 sd0: sdhci@56000000 {
680 cell-index = <0>;
681 compatible = "sirf,prima2-sdhc";
682 reg = <0x56000000 0x100000>;
683 interrupts = <38>;
684 bus-width = <8>;
685 clocks = <&clks 36>;
686 };
688 sd1: sdhci@56100000 {
689 cell-index = <1>;
690 compatible = "sirf,prima2-sdhc";
691 reg = <0x56100000 0x100000>;
692 interrupts = <38>;
693 status = "disabled";
694 bus-width = <4>;
695 clocks = <&clks 36>;
696 };
698 sd2: sdhci@56200000 {
699 cell-index = <2>;
700 compatible = "sirf,prima2-sdhc";
701 reg = <0x56200000 0x100000>;
702 interrupts = <23>;
703 status = "disabled";
704 bus-width = <4>;
705 clocks = <&clks 37>;
706 };
708 sd3: sdhci@56300000 {
709 cell-index = <3>;
710 compatible = "sirf,prima2-sdhc";
711 reg = <0x56300000 0x100000>;
712 interrupts = <23>;
713 status = "disabled";
714 bus-width = <4>;
715 clocks = <&clks 37>;
716 };
718 sd5: sdhci@56500000 {
719 cell-index = <5>;
720 compatible = "sirf,prima2-sdhc";
721 reg = <0x56500000 0x100000>;
722 interrupts = <39>;
723 status = "disabled";
724 bus-width = <4>;
725 clocks = <&clks 38>;
726 };
728 pci-copy@57900000 {
729 compatible = "sirf,prima2-pcicp";
730 reg = <0x57900000 0x100000>;
731 interrupts = <40>;
732 };
734 rom-interface@57a00000 {
735 compatible = "sirf,prima2-romif";
736 reg = <0x57a00000 0x100000>;
737 };
738 };
739 };
741 rtc-iobg {
742 compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
743 #address-cells = <1>;
744 #size-cells = <1>;
745 reg = <0x80030000 0x10000>;
747 gpsrtc@1000 {
748 compatible = "sirf,prima2-gpsrtc";
749 reg = <0x1000 0x1000>;
750 interrupts = <55 56 57>;
751 };
753 sysrtc@2000 {
754 compatible = "sirf,prima2-sysrtc";
755 reg = <0x2000 0x1000>;
756 interrupts = <52 53 54>;
757 };
759 minigpsrtc@2000 {
760 compatible = "sirf,prima2-minigpsrtc";
761 reg = <0x2000 0x1000>;
762 interrupts = <54>;
763 };
765 pwrc@3000 {
766 compatible = "sirf,prima2-pwrc";
767 reg = <0x3000 0x1000>;
768 interrupts = <32>;
769 };
770 };
772 uus-iobg {
773 compatible = "simple-bus";
774 #address-cells = <1>;
775 #size-cells = <1>;
776 ranges = <0xb8000000 0xb8000000 0x40000>;
778 usb0: usb@b00e0000 {
779 compatible = "chipidea,ci13611a-prima2";
780 reg = <0xb8000000 0x10000>;
781 interrupts = <10>;
782 clocks = <&clks 40>;
783 };
785 usb1: usb@b00f0000 {
786 compatible = "chipidea,ci13611a-prima2";
787 reg = <0xb8010000 0x10000>;
788 interrupts = <11>;
789 clocks = <&clks 41>;
790 };
792 security@b00f0000 {
793 compatible = "sirf,prima2-security";
794 reg = <0xb8030000 0x10000>;
795 interrupts = <42>;
796 clocks = <&clks 7>;
797 };
798 };
799 };
800 };