| blob | 99c9d9d9267f36306ffc5405b6d6abbdc43b83a1 |
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * DTS file for CSR SiRFatlas7 SoC
4 *
5 * Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
6 */
8 / {
9 compatible = "sirf,atlas7";
10 #address-cells = <1>;
11 #size-cells = <1>;
12 interrupt-parent = <&gic>;
13 aliases {
14 serial0 = &uart0;
15 serial1 = &uart1;
16 serial2 = &uart2;
17 serial3 = &uart3;
18 serial4 = &uart4;
19 serial5 = &uart5;
20 serial6 = &uart6;
21 serial9 = &usp2;
22 spi1 = &spi1;
23 spi2 = &usp1;
24 spi3 = &usp2;
25 spi4 = &usp3;
26 };
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a7";
34 reg = <0>;
35 };
36 cpu@1 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a7";
39 reg = <1>;
40 };
41 };
43 clocks {
44 xinw {
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <32768>;
48 clock-output-names = "xinw";
49 };
50 xin {
51 compatible = "fixed-clock";
52 #clock-cells = <0>;
53 clock-frequency = <26000000>;
54 clock-output-names = "xin";
55 };
56 };
58 arm-pmu {
59 compatible = "arm,cortex-a7-pmu";
60 interrupts = <0 29 4>, <0 82 4>;
61 };
63 noc {
64 compatible = "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 ranges = <0x10000000 0x10000000 0xc0000000>;
69 gic: interrupt-controller@10301000 {
70 compatible = "arm,cortex-a9-gic";
71 interrupt-controller;
72 #interrupt-cells = <3>;
73 reg = <0x10301000 0x1000>,
74 <0x10302000 0x0100>;
75 };
77 pmu_regulator: pmu_regulator@10E30020 {
78 compatible = "sirf,atlas7-pmu-ldo";
79 reg = <0x10E30020 0x4>;
80 ldo: ldo {
81 regulator-name = "ldo";
82 };
83 };
85 atlas7_codec: atlas7_codec@10E30000 {
86 #sound-dai-cells = <0>;
87 compatible = "sirf,atlas7-codec";
88 reg = <0x10E30000 0x400>;
89 clocks = <&car 62>;
90 ldo-supply = <&ldo>;
91 };
93 atlas7_iacc: atlas7_iacc@10D01000 {
94 #sound-dai-cells = <0>;
95 compatible = "sirf,atlas7-iacc";
96 reg = <0x10D01000 0x100>;
97 dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
98 <&dmac3 3>, <&dmac3 9>;
99 dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
100 clocks = <&car 62>;
101 };
103 ipc@13240000 {
104 compatible = "sirf,atlas7-ipc";
105 ranges = <0x13240000 0x13240000 0x00010000>;
106 #address-cells = <1>;
107 #size-cells = <1>;
109 hwspinlock {
110 compatible = "sirf,hwspinlock";
111 reg = <0x13240000 0x00010000>;
113 num-spinlocks = <30>;
114 };
116 ns_m3_rproc@0 {
117 compatible = "sirf,ns2m30-rproc";
118 reg = <0x13240000 0x00010000>;
119 interrupts = <0 123 0>;
120 };
122 ns_m3_rproc@1 {
123 compatible = "sirf,ns2m31-rproc";
124 reg = <0x13240000 0x00010000>;
125 interrupts = <0 126 0>;
126 };
128 ns_kal_rproc@0 {
129 compatible = "sirf,ns2kal0-rproc";
130 reg = <0x13240000 0x00010000>;
131 interrupts = <0 124 0>;
132 };
134 ns_kal_rproc@1 {
135 compatible = "sirf,ns2kal1-rproc";
136 reg = <0x13240000 0x00010000>;
137 interrupts = <0 127 0>;
138 };
139 };
141 pinctrl: ioc@18880000 {
142 compatible = "sirf,atlas7-ioc";
143 reg = <0x18880000 0x1000>,
144 <0x10E40000 0x1000>;
146 audio_ac97_pmx: audio_ac97@0 {
147 audio_ac97 {
148 groups = "audio_ac97_grp";
149 function = "audio_ac97";
150 };
151 };
153 audio_func_dbg_pmx: audio_func_dbg@0 {
154 audio_func_dbg {
155 groups = "audio_func_dbg_grp";
156 function = "audio_func_dbg";
157 };
158 };
160 audio_i2s_pmx: audio_i2s@0 {
161 audio_i2s {
162 groups = "audio_i2s_grp";
163 function = "audio_i2s";
164 };
165 };
167 audio_i2s_2ch_pmx: audio_i2s_2ch@0 {
168 audio_i2s_2ch {
169 groups = "audio_i2s_2ch_grp";
170 function = "audio_i2s_2ch";
171 };
172 };
174 audio_i2s_extclk_pmx: audio_i2s_extclk@0 {
175 audio_i2s_extclk {
176 groups = "audio_i2s_extclk_grp";
177 function = "audio_i2s_extclk";
178 };
179 };
181 audio_uart0_pmx: audio_uart0@0 {
182 audio_uart0 {
183 groups = "audio_uart0_grp";
184 function = "audio_uart0";
185 };
186 };
188 audio_uart1_pmx: audio_uart1@0 {
189 audio_uart1 {
190 groups = "audio_uart1_grp";
191 function = "audio_uart1";
192 };
193 };
195 audio_uart2_pmx0: audio_uart2@0 {
196 audio_uart2_0 {
197 groups = "audio_uart2_grp0";
198 function = "audio_uart2_m0";
199 };
200 };
202 audio_uart2_pmx1: audio_uart2@1 {
203 audio_uart2_1 {
204 groups = "audio_uart2_grp1";
205 function = "audio_uart2_m1";
206 };
207 };
209 c_can_trnsvr_pmx: c_can_trnsvr@0 {
210 c_can_trnsvr {
211 groups = "c_can_trnsvr_grp";
212 function = "c_can_trnsvr";
213 };
214 };
216 c0_can_pmx0: c0_can@0 {
217 c0_can_0 {
218 groups = "c0_can_grp0";
219 function = "c0_can_m0";
220 };
221 };
223 c0_can_pmx1: c0_can@1 {
224 c0_can_1 {
225 groups = "c0_can_grp1";
226 function = "c0_can_m1";
227 };
228 };
230 c1_can_pmx0: c1_can@0 {
231 c1_can_0 {
232 groups = "c1_can_grp0";
233 function = "c1_can_m0";
234 };
235 };
237 c1_can_pmx1: c1_can@1 {
238 c1_can_1 {
239 groups = "c1_can_grp1";
240 function = "c1_can_m1";
241 };
242 };
244 c1_can_pmx2: c1_can@2 {
245 c1_can_2 {
246 groups = "c1_can_grp2";
247 function = "c1_can_m2";
248 };
249 };
251 ca_audio_lpc_pmx: ca_audio_lpc@0 {
252 ca_audio_lpc {
253 groups = "ca_audio_lpc_grp";
254 function = "ca_audio_lpc";
255 };
256 };
258 ca_bt_lpc_pmx: ca_bt_lpc@0 {
259 ca_bt_lpc {
260 groups = "ca_bt_lpc_grp";
261 function = "ca_bt_lpc";
262 };
263 };
265 ca_coex_pmx: ca_coex@0 {
266 ca_coex {
267 groups = "ca_coex_grp";
268 function = "ca_coex";
269 };
270 };
272 ca_curator_lpc_pmx: ca_curator_lpc@0 {
273 ca_curator_lpc {
274 groups = "ca_curator_lpc_grp";
275 function = "ca_curator_lpc";
276 };
277 };
279 ca_pcm_debug_pmx: ca_pcm_debug@0 {
280 ca_pcm_debug {
281 groups = "ca_pcm_debug_grp";
282 function = "ca_pcm_debug";
283 };
284 };
286 ca_pio_pmx: ca_pio@0 {
287 ca_pio {
288 groups = "ca_pio_grp";
289 function = "ca_pio";
290 };
291 };
293 ca_sdio_debug_pmx: ca_sdio_debug@0 {
294 ca_sdio_debug {
295 groups = "ca_sdio_debug_grp";
296 function = "ca_sdio_debug";
297 };
298 };
300 ca_spi_pmx: ca_spi@0 {
301 ca_spi {
302 groups = "ca_spi_grp";
303 function = "ca_spi";
304 };
305 };
307 ca_trb_pmx: ca_trb@0 {
308 ca_trb {
309 groups = "ca_trb_grp";
310 function = "ca_trb";
311 };
312 };
314 ca_uart_debug_pmx: ca_uart_debug@0 {
315 ca_uart_debug {
316 groups = "ca_uart_debug_grp";
317 function = "ca_uart_debug";
318 };
319 };
321 clkc_pmx0: clkc@0 {
322 clkc_0 {
323 groups = "clkc_grp0";
324 function = "clkc_m0";
325 };
326 };
328 clkc_pmx1: clkc@1 {
329 clkc_1 {
330 groups = "clkc_grp1";
331 function = "clkc_m1";
332 };
333 };
335 gn_gnss_i2c_pmx: gn_gnss_i2c@0 {
336 gn_gnss_i2c {
337 groups = "gn_gnss_i2c_grp";
338 function = "gn_gnss_i2c";
339 };
340 };
342 gn_gnss_uart_nopause_pmx: gn_gnss_uart_nopause@0 {
343 gn_gnss_uart_nopause {
344 groups = "gn_gnss_uart_nopause_grp";
345 function = "gn_gnss_uart_nopause";
346 };
347 };
349 gn_gnss_uart_pmx: gn_gnss_uart@0 {
350 gn_gnss_uart {
351 groups = "gn_gnss_uart_grp";
352 function = "gn_gnss_uart";
353 };
354 };
356 gn_trg_spi_pmx0: gn_trg_spi@0 {
357 gn_trg_spi_0 {
358 groups = "gn_trg_spi_grp0";
359 function = "gn_trg_spi_m0";
360 };
361 };
363 gn_trg_spi_pmx1: gn_trg_spi@1 {
364 gn_trg_spi_1 {
365 groups = "gn_trg_spi_grp1";
366 function = "gn_trg_spi_m1";
367 };
368 };
370 cvbs_dbg_pmx: cvbs_dbg@0 {
371 cvbs_dbg {
372 groups = "cvbs_dbg_grp";
373 function = "cvbs_dbg";
374 };
375 };
377 cvbs_dbg_test_pmx0: cvbs_dbg_test@0 {
378 cvbs_dbg_test_0 {
379 groups = "cvbs_dbg_test_grp0";
380 function = "cvbs_dbg_test_m0";
381 };
382 };
384 cvbs_dbg_test_pmx1: cvbs_dbg_test@1 {
385 cvbs_dbg_test_1 {
386 groups = "cvbs_dbg_test_grp1";
387 function = "cvbs_dbg_test_m1";
388 };
389 };
391 cvbs_dbg_test_pmx2: cvbs_dbg_test@2 {
392 cvbs_dbg_test_2 {
393 groups = "cvbs_dbg_test_grp2";
394 function = "cvbs_dbg_test_m2";
395 };
396 };
398 cvbs_dbg_test_pmx3: cvbs_dbg_test@3 {
399 cvbs_dbg_test_3 {
400 groups = "cvbs_dbg_test_grp3";
401 function = "cvbs_dbg_test_m3";
402 };
403 };
405 cvbs_dbg_test_pmx4: cvbs_dbg_test@4 {
406 cvbs_dbg_test_4 {
407 groups = "cvbs_dbg_test_grp4";
408 function = "cvbs_dbg_test_m4";
409 };
410 };
412 cvbs_dbg_test_pmx5: cvbs_dbg_test@5 {
413 cvbs_dbg_test_5 {
414 groups = "cvbs_dbg_test_grp5";
415 function = "cvbs_dbg_test_m5";
416 };
417 };
419 cvbs_dbg_test_pmx6: cvbs_dbg_test@6 {
420 cvbs_dbg_test_6 {
421 groups = "cvbs_dbg_test_grp6";
422 function = "cvbs_dbg_test_m6";
423 };
424 };
426 cvbs_dbg_test_pmx7: cvbs_dbg_test@7 {
427 cvbs_dbg_test_7 {
428 groups = "cvbs_dbg_test_grp7";
429 function = "cvbs_dbg_test_m7";
430 };
431 };
433 cvbs_dbg_test_pmx8: cvbs_dbg_test@8 {
434 cvbs_dbg_test_8 {
435 groups = "cvbs_dbg_test_grp8";
436 function = "cvbs_dbg_test_m8";
437 };
438 };
440 cvbs_dbg_test_pmx9: cvbs_dbg_test@9 {
441 cvbs_dbg_test_9 {
442 groups = "cvbs_dbg_test_grp9";
443 function = "cvbs_dbg_test_m9";
444 };
445 };
447 cvbs_dbg_test_pmx10: cvbs_dbg_test@10 {
448 cvbs_dbg_test_10 {
449 groups = "cvbs_dbg_test_grp10";
450 function = "cvbs_dbg_test_m10";
451 };
452 };
454 cvbs_dbg_test_pmx11: cvbs_dbg_test@11 {
455 cvbs_dbg_test_11 {
456 groups = "cvbs_dbg_test_grp11";
457 function = "cvbs_dbg_test_m11";
458 };
459 };
461 cvbs_dbg_test_pmx12: cvbs_dbg_test@12 {
462 cvbs_dbg_test_12 {
463 groups = "cvbs_dbg_test_grp12";
464 function = "cvbs_dbg_test_m12";
465 };
466 };
468 cvbs_dbg_test_pmx13: cvbs_dbg_test@13 {
469 cvbs_dbg_test_13 {
470 groups = "cvbs_dbg_test_grp13";
471 function = "cvbs_dbg_test_m13";
472 };
473 };
475 cvbs_dbg_test_pmx14: cvbs_dbg_test@14 {
476 cvbs_dbg_test_14 {
477 groups = "cvbs_dbg_test_grp14";
478 function = "cvbs_dbg_test_m14";
479 };
480 };
482 cvbs_dbg_test_pmx15: cvbs_dbg_test@15 {
483 cvbs_dbg_test_15 {
484 groups = "cvbs_dbg_test_grp15";
485 function = "cvbs_dbg_test_m15";
486 };
487 };
489 gn_gnss_power_pmx: gn_gnss_power@0 {
490 gn_gnss_power {
491 groups = "gn_gnss_power_grp";
492 function = "gn_gnss_power";
493 };
494 };
496 gn_gnss_sw_status_pmx: gn_gnss_sw_status@0 {
497 gn_gnss_sw_status {
498 groups = "gn_gnss_sw_status_grp";
499 function = "gn_gnss_sw_status";
500 };
501 };
503 gn_gnss_eclk_pmx: gn_gnss_eclk@0 {
504 gn_gnss_eclk {
505 groups = "gn_gnss_eclk_grp";
506 function = "gn_gnss_eclk";
507 };
508 };
510 gn_gnss_irq1_pmx0: gn_gnss_irq1@0 {
511 gn_gnss_irq1_0 {
512 groups = "gn_gnss_irq1_grp0";
513 function = "gn_gnss_irq1_m0";
514 };
515 };
517 gn_gnss_irq2_pmx0: gn_gnss_irq2@0 {
518 gn_gnss_irq2_0 {
519 groups = "gn_gnss_irq2_grp0";
520 function = "gn_gnss_irq2_m0";
521 };
522 };
524 gn_gnss_tm_pmx: gn_gnss_tm@0 {
525 gn_gnss_tm {
526 groups = "gn_gnss_tm_grp";
527 function = "gn_gnss_tm";
528 };
529 };
531 gn_gnss_tsync_pmx: gn_gnss_tsync@0 {
532 gn_gnss_tsync {
533 groups = "gn_gnss_tsync_grp";
534 function = "gn_gnss_tsync";
535 };
536 };
538 gn_io_gnsssys_sw_cfg_pmx: gn_io_gnsssys_sw_cfg@0 {
539 gn_io_gnsssys_sw_cfg {
540 groups = "gn_io_gnsssys_sw_cfg_grp";
541 function = "gn_io_gnsssys_sw_cfg";
542 };
543 };
545 gn_trg_pmx0: gn_trg@0 {
546 gn_trg_0 {
547 groups = "gn_trg_grp0";
548 function = "gn_trg_m0";
549 };
550 };
552 gn_trg_pmx1: gn_trg@1 {
553 gn_trg_1 {
554 groups = "gn_trg_grp1";
555 function = "gn_trg_m1";
556 };
557 };
559 gn_trg_shutdown_pmx0: gn_trg_shutdown@0 {
560 gn_trg_shutdown_0 {
561 groups = "gn_trg_shutdown_grp0";
562 function = "gn_trg_shutdown_m0";
563 };
564 };
566 gn_trg_shutdown_pmx1: gn_trg_shutdown@1 {
567 gn_trg_shutdown_1 {
568 groups = "gn_trg_shutdown_grp1";
569 function = "gn_trg_shutdown_m1";
570 };
571 };
573 gn_trg_shutdown_pmx2: gn_trg_shutdown@2 {
574 gn_trg_shutdown_2 {
575 groups = "gn_trg_shutdown_grp2";
576 function = "gn_trg_shutdown_m2";
577 };
578 };
580 gn_trg_shutdown_pmx3: gn_trg_shutdown@3 {
581 gn_trg_shutdown_3 {
582 groups = "gn_trg_shutdown_grp3";
583 function = "gn_trg_shutdown_m3";
584 };
585 };
587 i2c0_pmx: i2c0@0 {
588 i2c0 {
589 groups = "i2c0_grp";
590 function = "i2c0";
591 };
592 };
594 i2c1_pmx: i2c1@0 {
595 i2c1 {
596 groups = "i2c1_grp";
597 function = "i2c1";
598 };
599 };
601 jtag_pmx0: jtag@0 {
602 jtag_0 {
603 groups = "jtag_grp0";
604 function = "jtag_m0";
605 };
606 };
608 ks_kas_spi_pmx0: ks_kas_spi@0 {
609 ks_kas_spi_0 {
610 groups = "ks_kas_spi_grp0";
611 function = "ks_kas_spi_m0";
612 };
613 };
615 ld_ldd_pmx: ld_ldd@0 {
616 ld_ldd {
617 groups = "ld_ldd_grp";
618 function = "ld_ldd";
619 };
620 };
622 ld_ldd_16bit_pmx: ld_ldd_16bit@0 {
623 ld_ldd_16bit {
624 groups = "ld_ldd_16bit_grp";
625 function = "ld_ldd_16bit";
626 };
627 };
629 ld_ldd_fck_pmx: ld_ldd_fck@0 {
630 ld_ldd_fck {
631 groups = "ld_ldd_fck_grp";
632 function = "ld_ldd_fck";
633 };
634 };
636 ld_ldd_lck_pmx: ld_ldd_lck@0 {
637 ld_ldd_lck {
638 groups = "ld_ldd_lck_grp";
639 function = "ld_ldd_lck";
640 };
641 };
643 lr_lcdrom_pmx: lr_lcdrom@0 {
644 lr_lcdrom {
645 groups = "lr_lcdrom_grp";
646 function = "lr_lcdrom";
647 };
648 };
650 lvds_analog_pmx: lvds_analog@0 {
651 lvds_analog {
652 groups = "lvds_analog_grp";
653 function = "lvds_analog";
654 };
655 };
657 nd_df_pmx: nd_df@0 {
658 nd_df {
659 groups = "nd_df_grp";
660 function = "nd_df";
661 };
662 };
664 nd_df_nowp_pmx: nd_df_nowp@0 {
665 nd_df_nowp {
666 groups = "nd_df_nowp_grp";
667 function = "nd_df_nowp";
668 };
669 };
671 ps_pmx: ps@0 {
672 ps {
673 groups = "ps_grp";
674 function = "ps";
675 };
676 };
678 pwc_core_on_pmx: pwc_core_on@0 {
679 pwc_core_on {
680 groups = "pwc_core_on_grp";
681 function = "pwc_core_on";
682 };
683 };
685 pwc_ext_on_pmx: pwc_ext_on@0 {
686 pwc_ext_on {
687 groups = "pwc_ext_on_grp";
688 function = "pwc_ext_on";
689 };
690 };
692 pwc_gpio3_clk_pmx: pwc_gpio3_clk@0 {
693 pwc_gpio3_clk {
694 groups = "pwc_gpio3_clk_grp";
695 function = "pwc_gpio3_clk";
696 };
697 };
699 pwc_io_on_pmx: pwc_io_on@0 {
700 pwc_io_on {
701 groups = "pwc_io_on_grp";
702 function = "pwc_io_on";
703 };
704 };
706 pwc_lowbatt_b_pmx0: pwc_lowbatt_b@0 {
707 pwc_lowbatt_b_0 {
708 groups = "pwc_lowbatt_b_grp0";
709 function = "pwc_lowbatt_b_m0";
710 };
711 };
713 pwc_mem_on_pmx: pwc_mem_on@0 {
714 pwc_mem_on {
715 groups = "pwc_mem_on_grp";
716 function = "pwc_mem_on";
717 };
718 };
720 pwc_on_key_b_pmx0: pwc_on_key_b@0 {
721 pwc_on_key_b_0 {
722 groups = "pwc_on_key_b_grp0";
723 function = "pwc_on_key_b_m0";
724 };
725 };
727 pwc_wakeup_src0_pmx: pwc_wakeup_src0@0 {
728 pwc_wakeup_src0 {
729 groups = "pwc_wakeup_src0_grp";
730 function = "pwc_wakeup_src0";
731 };
732 };
734 pwc_wakeup_src1_pmx: pwc_wakeup_src1@0 {
735 pwc_wakeup_src1 {
736 groups = "pwc_wakeup_src1_grp";
737 function = "pwc_wakeup_src1";
738 };
739 };
741 pwc_wakeup_src2_pmx: pwc_wakeup_src2@0 {
742 pwc_wakeup_src2 {
743 groups = "pwc_wakeup_src2_grp";
744 function = "pwc_wakeup_src2";
745 };
746 };
748 pwc_wakeup_src3_pmx: pwc_wakeup_src3@0 {
749 pwc_wakeup_src3 {
750 groups = "pwc_wakeup_src3_grp";
751 function = "pwc_wakeup_src3";
752 };
753 };
755 pw_cko0_pmx0: pw_cko0@0 {
756 pw_cko0_0 {
757 groups = "pw_cko0_grp0";
758 function = "pw_cko0_m0";
759 };
760 };
762 pw_cko0_pmx1: pw_cko0@1 {
763 pw_cko0_1 {
764 groups = "pw_cko0_grp1";
765 function = "pw_cko0_m1";
766 };
767 };
769 pw_cko0_pmx2: pw_cko0@2 {
770 pw_cko0_2 {
771 groups = "pw_cko0_grp2";
772 function = "pw_cko0_m2";
773 };
774 };
776 pw_cko1_pmx0: pw_cko1@0 {
777 pw_cko1_0 {
778 groups = "pw_cko1_grp0";
779 function = "pw_cko1_m0";
780 };
781 };
783 pw_cko1_pmx1: pw_cko1@1 {
784 pw_cko1_1 {
785 groups = "pw_cko1_grp1";
786 function = "pw_cko1_m1";
787 };
788 };
790 pw_i2s01_clk_pmx0: pw_i2s01_clk@0 {
791 pw_i2s01_clk_0 {
792 groups = "pw_i2s01_clk_grp0";
793 function = "pw_i2s01_clk_m0";
794 };
795 };
797 pw_i2s01_clk_pmx1: pw_i2s01_clk@1 {
798 pw_i2s01_clk_1 {
799 groups = "pw_i2s01_clk_grp1";
800 function = "pw_i2s01_clk_m1";
801 };
802 };
804 pw_pwm0_pmx: pw_pwm0@0 {
805 pw_pwm0 {
806 groups = "pw_pwm0_grp";
807 function = "pw_pwm0";
808 };
809 };
811 pw_pwm1_pmx: pw_pwm1@0 {
812 pw_pwm1 {
813 groups = "pw_pwm1_grp";
814 function = "pw_pwm1";
815 };
816 };
818 pw_pwm2_pmx0: pw_pwm2@0 {
819 pw_pwm2_0 {
820 groups = "pw_pwm2_grp0";
821 function = "pw_pwm2_m0";
822 };
823 };
825 pw_pwm2_pmx1: pw_pwm2@1 {
826 pw_pwm2_1 {
827 groups = "pw_pwm2_grp1";
828 function = "pw_pwm2_m1";
829 };
830 };
832 pw_pwm3_pmx0: pw_pwm3@0 {
833 pw_pwm3_0 {
834 groups = "pw_pwm3_grp0";
835 function = "pw_pwm3_m0";
836 };
837 };
839 pw_pwm3_pmx1: pw_pwm3@1 {
840 pw_pwm3_1 {
841 groups = "pw_pwm3_grp1";
842 function = "pw_pwm3_m1";
843 };
844 };
846 pw_pwm_cpu_vol_pmx0: pw_pwm_cpu_vol@0 {
847 pw_pwm_cpu_vol_0 {
848 groups = "pw_pwm_cpu_vol_grp0";
849 function = "pw_pwm_cpu_vol_m0";
850 };
851 };
853 pw_pwm_cpu_vol_pmx1: pw_pwm_cpu_vol@1 {
854 pw_pwm_cpu_vol_1 {
855 groups = "pw_pwm_cpu_vol_grp1";
856 function = "pw_pwm_cpu_vol_m1";
857 };
858 };
860 pw_backlight_pmx0: pw_backlight@0 {
861 pw_backlight_0 {
862 groups = "pw_backlight_grp0";
863 function = "pw_backlight_m0";
864 };
865 };
867 pw_backlight_pmx1: pw_backlight@1 {
868 pw_backlight_1 {
869 groups = "pw_backlight_grp1";
870 function = "pw_backlight_m1";
871 };
872 };
874 rg_eth_mac_pmx: rg_eth_mac@0 {
875 rg_eth_mac {
876 groups = "rg_eth_mac_grp";
877 function = "rg_eth_mac";
878 };
879 };
881 rg_gmac_phy_intr_n_pmx: rg_gmac_phy_intr_n@0 {
882 rg_gmac_phy_intr_n {
883 groups = "rg_gmac_phy_intr_n_grp";
884 function = "rg_gmac_phy_intr_n";
885 };
886 };
888 rg_rgmii_mac_pmx: rg_rgmii_mac@0 {
889 rg_rgmii_mac {
890 groups = "rg_rgmii_mac_grp";
891 function = "rg_rgmii_mac";
892 };
893 };
895 rg_rgmii_phy_ref_clk_pmx0: rg_rgmii_phy_ref_clk@0 {
896 rg_rgmii_phy_ref_clk_0 {
897 groups =
898 "rg_rgmii_phy_ref_clk_grp0";
899 function =
900 "rg_rgmii_phy_ref_clk_m0";
901 };
902 };
904 rg_rgmii_phy_ref_clk_pmx1: rg_rgmii_phy_ref_clk@1 {
905 rg_rgmii_phy_ref_clk_1 {
906 groups =
907 "rg_rgmii_phy_ref_clk_grp1";
908 function =
909 "rg_rgmii_phy_ref_clk_m1";
910 };
911 };
913 sd0_pmx: sd0@0 {
914 sd0 {
915 groups = "sd0_grp";
916 function = "sd0";
917 };
918 };
920 sd0_4bit_pmx: sd0_4bit@0 {
921 sd0_4bit {
922 groups = "sd0_4bit_grp";
923 function = "sd0_4bit";
924 };
925 };
927 sd1_pmx: sd1@0 {
928 sd1 {
929 groups = "sd1_grp";
930 function = "sd1";
931 };
932 };
934 sd1_4bit_pmx0: sd1_4bit@0 {
935 sd1_4bit_0 {
936 groups = "sd1_4bit_grp0";
937 function = "sd1_4bit_m0";
938 };
939 };
941 sd1_4bit_pmx1: sd1_4bit@1 {
942 sd1_4bit_1 {
943 groups = "sd1_4bit_grp1";
944 function = "sd1_4bit_m1";
945 };
946 };
948 sd2_pmx0: sd2@0 {
949 sd2_0 {
950 groups = "sd2_grp0";
951 function = "sd2_m0";
952 };
953 };
955 sd2_no_cdb_pmx0: sd2_no_cdb@0 {
956 sd2_no_cdb_0 {
957 groups = "sd2_no_cdb_grp0";
958 function = "sd2_no_cdb_m0";
959 };
960 };
962 sd3_pmx: sd3@0 {
963 sd3 {
964 groups = "sd3_grp";
965 function = "sd3";
966 };
967 };
969 sd5_pmx: sd5@0 {
970 sd5 {
971 groups = "sd5_grp";
972 function = "sd5";
973 };
974 };
976 sd6_pmx0: sd6@0 {
977 sd6_0 {
978 groups = "sd6_grp0";
979 function = "sd6_m0";
980 };
981 };
983 sd6_pmx1: sd6@1 {
984 sd6_1 {
985 groups = "sd6_grp1";
986 function = "sd6_m1";
987 };
988 };
990 sp0_ext_ldo_on_pmx: sp0_ext_ldo_on@0 {
991 sp0_ext_ldo_on {
992 groups = "sp0_ext_ldo_on_grp";
993 function = "sp0_ext_ldo_on";
994 };
995 };
997 sp0_qspi_pmx: sp0_qspi@0 {
998 sp0_qspi {
999 groups = "sp0_qspi_grp";
1000 function = "sp0_qspi";
1001 };
1002 };
1004 sp1_spi_pmx: sp1_spi@0 {
1005 sp1_spi {
1006 groups = "sp1_spi_grp";
1007 function = "sp1_spi";
1008 };
1009 };
1011 tpiu_trace_pmx: tpiu_trace@0 {
1012 tpiu_trace {
1013 groups = "tpiu_trace_grp";
1014 function = "tpiu_trace";
1015 };
1016 };
1018 uart0_pmx: uart0@0 {
1019 uart0 {
1020 groups = "uart0_grp";
1021 function = "uart0";
1022 };
1023 };
1025 uart0_nopause_pmx: uart0_nopause@0 {
1026 uart0_nopause {
1027 groups = "uart0_nopause_grp";
1028 function = "uart0_nopause";
1029 };
1030 };
1032 uart1_pmx: uart1@0 {
1033 uart1 {
1034 groups = "uart1_grp";
1035 function = "uart1";
1036 };
1037 };
1039 uart2_pmx: uart2@0 {
1040 uart2 {
1041 groups = "uart2_grp";
1042 function = "uart2";
1043 };
1044 };
1046 uart3_pmx0: uart3@0 {
1047 uart3_0 {
1048 groups = "uart3_grp0";
1049 function = "uart3_m0";
1050 };
1051 };
1053 uart3_pmx1: uart3@1 {
1054 uart3_1 {
1055 groups = "uart3_grp1";
1056 function = "uart3_m1";
1057 };
1058 };
1060 uart3_pmx2: uart3@2 {
1061 uart3_2 {
1062 groups = "uart3_grp2";
1063 function = "uart3_m2";
1064 };
1065 };
1067 uart3_pmx3: uart3@3 {
1068 uart3_3 {
1069 groups = "uart3_grp3";
1070 function = "uart3_m3";
1071 };
1072 };
1074 uart3_nopause_pmx0: uart3_nopause@0 {
1075 uart3_nopause_0 {
1076 groups = "uart3_nopause_grp0";
1077 function = "uart3_nopause_m0";
1078 };
1079 };
1081 uart3_nopause_pmx1: uart3_nopause@1 {
1082 uart3_nopause_1 {
1083 groups = "uart3_nopause_grp1";
1084 function = "uart3_nopause_m1";
1085 };
1086 };
1088 uart4_pmx0: uart4@0 {
1089 uart4_0 {
1090 groups = "uart4_grp0";
1091 function = "uart4_m0";
1092 };
1093 };
1095 uart4_pmx1: uart4@1 {
1096 uart4_1 {
1097 groups = "uart4_grp1";
1098 function = "uart4_m1";
1099 };
1100 };
1102 uart4_pmx2: uart4@2 {
1103 uart4_2 {
1104 groups = "uart4_grp2";
1105 function = "uart4_m2";
1106 };
1107 };
1109 uart4_nopause_pmx: uart4_nopause@0 {
1110 uart4_nopause {
1111 groups = "uart4_nopause_grp";
1112 function = "uart4_nopause";
1113 };
1114 };
1116 usb0_drvvbus_pmx: usb0_drvvbus@0 {
1117 usb0_drvvbus {
1118 groups = "usb0_drvvbus_grp";
1119 function = "usb0_drvvbus";
1120 };
1121 };
1123 usb1_drvvbus_pmx: usb1_drvvbus@0 {
1124 usb1_drvvbus {
1125 groups = "usb1_drvvbus_grp";
1126 function = "usb1_drvvbus";
1127 };
1128 };
1130 visbus_dout_pmx: visbus_dout@0 {
1131 visbus_dout {
1132 groups = "visbus_dout_grp";
1133 function = "visbus_dout";
1134 };
1135 };
1137 vi_vip1_pmx: vi_vip1@0 {
1138 vi_vip1 {
1139 groups = "vi_vip1_grp";
1140 function = "vi_vip1";
1141 };
1142 };
1144 vi_vip1_ext_pmx: vi_vip1_ext@0 {
1145 vi_vip1_ext {
1146 groups = "vi_vip1_ext_grp";
1147 function = "vi_vip1_ext";
1148 };
1149 };
1151 vi_vip1_low8bit_pmx: vi_vip1_low8bit@0 {
1152 vi_vip1_low8bit {
1153 groups = "vi_vip1_low8bit_grp";
1154 function = "vi_vip1_low8bit";
1155 };
1156 };
1158 vi_vip1_high8bit_pmx: vi_vip1_high8bit@0 {
1159 vi_vip1_high8bit {
1160 groups = "vi_vip1_high8bit_grp";
1161 function = "vi_vip1_high8bit";
1162 };
1163 };
1164 };
1166 pmipc {
1167 compatible = "arteris, flexnoc", "simple-bus";
1168 #address-cells = <1>;
1169 #size-cells = <1>;
1170 ranges = <0x13240000 0x13240000 0x00010000>;
1171 pmipc@0x13240000 {
1172 compatible = "sirf,atlas7-pmipc";
1173 reg = <0x13240000 0x00010000>;
1174 };
1175 };
1177 dramfw {
1178 compatible = "arteris, flexnoc", "simple-bus";
1179 #address-cells = <1>;
1180 #size-cells = <1>;
1181 ranges = <0x10830000 0x10830000 0x18000>;
1182 dramfw@10820000 {
1183 compatible = "sirf,nocfw-dramfw";
1184 reg = <0x10830000 0x18000>;
1185 };
1186 };
1188 spramfw {
1189 compatible = "arteris, flexnoc", "simple-bus";
1190 #address-cells = <1>;
1191 #size-cells = <1>;
1192 ranges = <0x10250000 0x10250000 0x3000>;
1193 spramfw@10820000 {
1194 compatible = "sirf,nocfw-spramfw";
1195 reg = <0x10250000 0x3000>;
1196 };
1197 };
1199 cpum {
1200 compatible = "arteris, flexnoc", "simple-bus";
1201 #address-cells = <1>;
1202 #size-cells = <1>;
1203 ranges = <0x10200000 0x10200000 0x3000>;
1204 cpum@10200000 {
1205 compatible = "sirf,nocfw-cpum";
1206 reg = <0x10200000 0x3000>;
1207 };
1208 };
1210 cgum {
1211 compatible = "arteris, flexnoc", "simple-bus";
1212 #address-cells = <1>;
1213 #size-cells = <1>;
1214 ranges = <0x18641000 0x18641000 0x3000>,
1215 <0x18620000 0x18620000 0x1000>,
1216 <0x18630000 0x18630000 0x10000>;
1218 cgum@18641000 {
1219 compatible = "sirf,nocfw-cgum";
1220 reg = <0x18641000 0x3000>;
1221 };
1223 car: clock-controller@18620000 {
1224 compatible = "sirf,atlas7-car";
1225 reg = <0x18620000 0x1000>;
1226 #clock-cells = <1>;
1227 #reset-cells = <1>;
1228 };
1229 pwm: pwm@18630000 {
1230 compatible = "sirf,prima2-pwm";
1231 #pwm-cells = <2>;
1232 reg = <0x18630000 0x10000>;
1233 clocks = <&car 138>, <&car 139>, <&car 237>,
1234 <&car 240>, <&car 140>, <&car 246>;
1235 clock-names = "pwmc", "sigsrc0", "sigsrc1",
1236 "sigsrc2", "sigsrc3", "sigsrc4";
1237 };
1238 };
1240 gnssm {
1241 compatible = "arteris, flexnoc", "simple-bus";
1242 #address-cells = <1>;
1243 #size-cells = <1>;
1244 ranges = <0x18000000 0x18000000 0x0000ffff>,
1245 <0x18010000 0x18010000 0x1000>,
1246 <0x18020000 0x18020000 0x1000>,
1247 <0x18030000 0x18030000 0x1000>,
1248 <0x18040000 0x18040000 0x1000>,
1249 <0x18050000 0x18050000 0x1000>,
1250 <0x18060000 0x18060000 0x1000>,
1251 <0x180b0000 0x180b0000 0x4000>,
1252 <0x18100000 0x18100000 0x3000>,
1253 <0x18250000 0x18250000 0x10000>,
1254 <0x18200000 0x18200000 0x1000>;
1256 dmac0: dma-controller@18000000 {
1257 cell-index = <0>;
1258 compatible = "sirf,atlas7-dmac";
1259 reg = <0x18000000 0x1000>;
1260 interrupts = <0 12 0>;
1261 clocks = <&car 89>;
1262 dma-channels = <16>;
1263 #dma-cells = <1>;
1264 };
1266 gnssmfw@0x18100000 {
1267 compatible = "sirf,nocfw-gnssm";
1268 reg = <0x18100000 0x3000>;
1269 };
1271 uart0: uart@18010000 {
1272 cell-index = <0>;
1273 compatible = "sirf,atlas7-uart";
1274 reg = <0x18010000 0x1000>;
1275 interrupts = <0 17 0>;
1276 clocks = <&car 90>;
1277 fifosize = <128>;
1278 dmas = <&dmac0 3>, <&dmac0 2>;
1279 dma-names = "rx", "tx";
1280 };
1282 uart1: uart@18020000 {
1283 cell-index = <1>;
1284 compatible = "sirf,atlas7-uart";
1285 reg = <0x18020000 0x1000>;
1286 interrupts = <0 18 0>;
1287 clocks = <&car 88>;
1288 fifosize = <32>;
1289 };
1291 uart2: uart@18030000 {
1292 cell-index = <2>;
1293 compatible = "sirf,atlas7-uart";
1294 reg = <0x18030000 0x1000>;
1295 interrupts = <0 19 0>;
1296 clocks = <&car 91>;
1297 fifosize = <128>;
1298 dmas = <&dmac0 6>, <&dmac0 7>;
1299 dma-names = "rx", "tx";
1300 status = "disabled";
1301 };
1302 uart3: uart@18040000 {
1303 cell-index = <3>;
1304 compatible = "sirf,atlas7-uart";
1305 reg = <0x18040000 0x1000>;
1306 interrupts = <0 66 0>;
1307 clocks = <&car 92>;
1308 fifosize = <128>;
1309 dmas = <&dmac0 4>, <&dmac0 5>;
1310 dma-names = "rx", "tx";
1311 status = "disabled";
1312 };
1313 uart4: uart@18050000 {
1314 cell-index = <4>;
1315 compatible = "sirf,atlas7-uart";
1316 reg = <0x18050000 0x1000>;
1317 interrupts = <0 69 0>;
1318 clocks = <&car 93>;
1319 fifosize = <128>;
1320 dmas = <&dmac0 0>, <&dmac0 1>;
1321 dma-names = "rx", "tx";
1322 status = "disabled";
1323 };
1324 uart5: uart@18060000 {
1325 cell-index = <5>;
1326 compatible = "sirf,atlas7-uart";
1327 reg = <0x18060000 0x1000>;
1328 interrupts = <0 71 0>;
1329 clocks = <&car 94>;
1330 fifosize = <128>;
1331 dmas = <&dmac0 8>, <&dmac0 9>;
1332 dma-names = "rx", "tx";
1333 status = "disabled";
1334 };
1335 gmac: eth@180b0000 {
1336 compatible = "snps, dwc-eth-qos";
1337 reg = <0x180b0000 0x4000>;
1338 interrupts = <0 59 0>, <0 70 0>;
1339 interrupt-names = "macirq", "macpmt";
1340 clocks = <&car 39>, <&car 45>,
1341 <&car 86>, <&car 87>;
1342 clock-names = "gnssm_rgmii", "gnssm_gmac",
1343 "rgmii", "gmac";
1344 local-mac-address = [00 00 00 00 00 00];
1345 phy-mode = "rgmii";
1346 };
1347 dspub@18250000 {
1348 compatible = "dx,cc44p";
1349 reg = <0x18250000 0x10000>;
1350 interrupts = <0 27 0>;
1351 };
1353 spi1: spi@18200000 {
1354 compatible = "sirf,prima2-spi";
1355 reg = <0x18200000 0x1000>;
1356 interrupts = <0 16 0>;
1357 clocks = <&car 95>;
1358 #address-cells = <1>;
1359 #size-cells = <0>;
1360 dmas = <&dmac0 12>, <&dmac0 13>;
1361 dma-names = "rx", "tx";
1362 status = "disabled";
1363 };
1364 };
1367 gpum {
1368 compatible = "arteris, flexnoc", "simple-bus";
1369 #address-cells = <1>;
1370 #size-cells = <1>;
1371 ranges = <0x13000000 0x13000000 0x3000>,
1372 <0x13010000 0x13010000 0x1400>,
1373 <0x13010800 0x13010800 0x100>,
1374 <0x13011000 0x13011000 0x100>;
1375 gpum@0x13000000 {
1376 compatible = "sirf,nocfw-gpum";
1377 reg = <0x13000000 0x3000>;
1378 };
1379 dmacsdrr: dma-controller@13010800 {
1380 cell-index = <5>;
1381 compatible = "sirf,atlas7-dmac-v2";
1382 reg = <0x13010800 0x100>;
1383 interrupts = <0 8 0>;
1384 clocks = <&car 127>;
1385 #dma-cells = <1>;
1386 #dma-channels = <1>;
1387 };
1388 dmacsdrw: dma-controller@13011000 {
1389 cell-index = <6>;
1390 compatible = "sirf,atlas7-dmac-v2";
1391 reg = <0x13011000 0x100>;
1392 interrupts = <0 9 0>;
1393 clocks = <&car 127>;
1394 #dma-cells = <1>;
1395 #dma-channels = <1>;
1396 };
1397 sdr@0x13010000 {
1398 compatible = "sirf,atlas7-sdr";
1399 reg = <0x13010000 0x1400>;
1400 interrupts = <0 7 0>,
1401 <0 8 0>,
1402 <0 9 0>;
1403 clocks = <&car 127>;
1404 dmas = <&dmacsdrr 0>, <&dmacsdrw 0>;
1405 dma-names = "tx", "rx";
1406 };
1407 };
1409 mediam {
1410 compatible = "arteris, flexnoc", "simple-bus";
1411 #address-cells = <1>;
1412 #size-cells = <1>;
1413 ranges = <0x15000000 0x15000000 0x00600000>,
1414 <0x16000000 0x16000000 0x00200000>,
1415 <0x17000000 0x17000000 0x10000>,
1416 <0x17020000 0x17020000 0x1000>,
1417 <0x17030000 0x17030000 0x1000>,
1418 <0x17040000 0x17040000 0x1000>,
1419 <0x17050000 0x17050000 0x10000>,
1420 <0x17060000 0x17060000 0x200>,
1421 <0x17060200 0x17060200 0x100>,
1422 <0x17070000 0x17070000 0x200>,
1423 <0x17070200 0x17070200 0x100>,
1424 <0x170A0000 0x170A0000 0x3000>;
1426 multimedia@15000000 {
1427 compatible = "sirf,atlas7-video-codec";
1428 reg = <0x15000000 0x10000>;
1429 interrupts = <0 5 0>;
1430 clocks = <&car 102>;
1431 };
1433 mediam@170A0000 {
1434 compatible = "sirf,nocfw-mediam";
1435 reg = <0x170A0000 0x3000>;
1436 };
1438 gpio_0: gpio_mediam@17040000 {
1439 #gpio-cells = <2>;
1440 #interrupt-cells = <2>;
1441 compatible = "sirf,atlas7-gpio";
1442 reg = <0x17040000 0x1000>;
1443 interrupts = <0 13 0>, <0 14 0>;
1444 clocks = <&car 107>;
1445 clock-names = "gpio0_io";
1446 gpio-controller;
1447 interrupt-controller;
1449 gpio-banks = <2>;
1450 gpio-ranges = <&pinctrl 0 0 0>,
1451 <&pinctrl 32 0 0>;
1452 gpio-ranges-group-names = "lvds_gpio_grp",
1453 "uart_nand_gpio_grp";
1454 };
1456 nand@17050000 {
1457 compatible = "sirf,atlas7-nand";
1458 reg = <0x17050000 0x10000>;
1459 pinctrl-names = "default";
1460 pinctrl-0 = <&nd_df_pmx>;
1461 interrupts = <0 41 0>;
1462 clocks = <&car 108>, <&car 112>;
1463 clock-names = "nand_io", "nand_nand";
1464 };
1466 sd0: sdhci@16000000 {
1467 cell-index = <0>;
1468 compatible = "sirf,atlas7-sdhc";
1469 reg = <0x16000000 0x100000>;
1470 interrupts = <0 38 0>;
1471 clocks = <&car 109>, <&car 111>;
1472 clock-names = "core", "iface";
1473 wp-inverted;
1474 non-removable;
1475 status = "disabled";
1476 bus-width = <8>;
1477 };
1479 sd1: sdhci@16100000 {
1480 cell-index = <1>;
1481 compatible = "sirf,atlas7-sdhc";
1482 reg = <0x16100000 0x100000>;
1483 interrupts = <0 38 0>;
1484 clocks = <&car 109>, <&car 111>;
1485 clock-names = "core", "iface";
1486 non-removable;
1487 status = "disabled";
1488 bus-width = <8>;
1489 };
1491 jpeg@17000000 {
1492 compatible = "sirf,atlas7-jpeg";
1493 reg = <0x17000000 0x10000>;
1494 interrupts = <0 72 0>,
1495 <0 73 0>;
1496 clocks = <&car 103>;
1497 };
1499 usb0: usb@17060000 {
1500 cell-index = <0>;
1501 compatible = "sirf,atlas7-usb";
1502 reg = <0x17060000 0x200>;
1503 interrupts = <0 10 0>;
1504 clocks = <&car 113>;
1505 sirf,usbphy = <&usbphy0>;
1506 phy_type = "utmi";
1507 dr_mode = "otg";
1508 maximum-speed = "high-speed";
1509 status = "okay";
1510 };
1512 usb1: usb@17070000 {
1513 cell-index = <1>;
1514 compatible = "sirf,atlas7-usb";
1515 reg = <0x17070000 0x200>;
1516 interrupts = <0 11 0>;
1517 clocks = <&car 114>;
1518 sirf,usbphy = <&usbphy1>;
1519 phy_type = "utmi";
1520 dr_mode = "host";
1521 maximum-speed = "high-speed";
1522 status = "okay";
1523 };
1525 usbphy0: usbphy@0 {
1526 compatible = "sirf,atlas7-usbphy";
1527 reg = <0x17060200 0x100>;
1528 clocks = <&car 115>;
1529 status = "okay";
1530 };
1532 usbphy1: usbphy@1 {
1533 compatible = "sirf,atlas7-usbphy";
1534 reg = <0x17070200 0x100>;
1535 clocks = <&car 116>;
1536 status = "okay";
1537 };
1539 i2c0: i2c@17020000 {
1540 cell-index = <0>;
1541 compatible = "sirf,prima2-i2c";
1542 reg = <0x17020000 0x1000>;
1543 interrupts = <0 24 0>;
1544 clocks = <&car 105>;
1545 #address-cells = <1>;
1546 #size-cells = <0>;
1547 };
1549 };
1551 vdifm {
1552 compatible = "arteris, flexnoc", "simple-bus";
1553 #address-cells = <1>;
1554 #size-cells = <1>;
1555 ranges = <0x13290000 0x13290000 0x3000>,
1556 <0x13300000 0x13300000 0x1000>,
1557 <0x14200000 0x14200000 0x600000>;
1559 vdifm@13290000 {
1560 compatible = "sirf,nocfw-vdifm";
1561 reg = <0x13290000 0x3000>;
1562 };
1564 gpio_1: gpio_vdifm@13300000 {
1565 #gpio-cells = <2>;
1566 #interrupt-cells = <2>;
1567 compatible = "sirf,atlas7-gpio";
1568 reg = <0x13300000 0x1000>;
1569 interrupts = <0 43 0>, <0 44 0>,
1570 <0 45 0>, <0 46 0>;
1571 clocks = <&car 84>;
1572 clock-names = "gpio1_io";
1573 gpio-controller;
1574 interrupt-controller;
1576 gpio-banks = <4>;
1577 gpio-ranges = <&pinctrl 0 0 0>,
1578 <&pinctrl 32 0 0>,
1579 <&pinctrl 64 0 0>,
1580 <&pinctrl 96 0 0>;
1581 gpio-ranges-group-names = "gnss_gpio_grp",
1582 "lcd_vip_gpio_grp",
1583 "sdio_i2s_gpio_grp",
1584 "sp_rgmii_gpio_grp";
1585 };
1587 sd2: sdhci@14200000 {
1588 cell-index = <2>;
1589 compatible = "sirf,atlas7-sdhc";
1590 reg = <0x14200000 0x100000>;
1591 interrupts = <0 23 0>;
1592 clocks = <&car 70>, <&car 75>;
1593 clock-names = "core", "iface";
1594 status = "disabled";
1595 bus-width = <4>;
1596 sd-uhs-sdr50;
1597 vqmmc-supply = <&vqmmc>;
1598 vqmmc: vqmmc@2 {
1599 regulator-min-microvolt = <1650000>;
1600 regulator-max-microvolt = <1950000>;
1601 regulator-name = "vqmmc-ldo";
1602 regulator-type = "voltage";
1603 regulator-boot-on;
1604 regulator-allow-bypass;
1605 };
1606 };
1608 sd3: sdhci@14300000 {
1609 cell-index = <3>;
1610 compatible = "sirf,atlas7-sdhc";
1611 reg = <0x14300000 0x100000>;
1612 interrupts = <0 23 0>;
1613 clocks = <&car 76>, <&car 81>;
1614 clock-names = "core", "iface";
1615 status = "disabled";
1616 bus-width = <4>;
1617 };
1619 sd5: sdhci@14500000 {
1620 cell-index = <5>;
1621 compatible = "sirf,atlas7-sdhc";
1622 reg = <0x14500000 0x100000>;
1623 interrupts = <0 39 0>;
1624 clocks = <&car 71>, <&car 76>;
1625 clock-names = "core", "iface";
1626 status = "disabled";
1627 bus-width = <4>;
1628 loop-dma;
1629 };
1631 sd6: sdhci@14600000 {
1632 cell-index = <6>;
1633 compatible = "sirf,atlas7-sdhc";
1634 reg = <0x14600000 0x100000>;
1635 interrupts = <0 98 0>;
1636 clocks = <&car 72>, <&car 77>;
1637 clock-names = "core", "iface";
1638 status = "disabled";
1639 bus-width = <4>;
1640 };
1642 sd7: sdhci@14700000 {
1643 cell-index = <7>;
1644 compatible = "sirf,atlas7-sdhc";
1645 reg = <0x14700000 0x100000>;
1646 interrupts = <0 98 0>;
1647 clocks = <&car 72>, <&car 77>;
1648 clock-names = "core", "iface";
1649 status = "disabled";
1650 bus-width = <4>;
1651 };
1652 };
1654 audiom {
1655 compatible = "arteris, flexnoc", "simple-bus";
1656 #address-cells = <1>;
1657 #size-cells = <1>;
1658 ranges = <0x10d50000 0x10d50000 0x0000ffff>,
1659 <0x10d60000 0x10d60000 0x0000ffff>,
1660 <0x10d80000 0x10d80000 0x0000ffff>,
1661 <0x10d90000 0x10d90000 0x0000ffff>,
1662 <0x10ED0000 0x10ED0000 0x3000>,
1663 <0x10dc8000 0x10dc8000 0x1000>,
1664 <0x10dc0000 0x10dc0000 0x1000>,
1665 <0x10db0000 0x10db0000 0x4000>,
1666 <0x10d40000 0x10d40000 0x1000>,
1667 <0x10d30000 0x10d30000 0x1000>;
1669 timer@10dc0000 {
1670 compatible = "sirf,atlas7-tick";
1671 reg = <0x10dc0000 0x1000>;
1672 interrupts = <0 0 0>,
1673 <0 1 0>,
1674 <0 2 0>,
1675 <0 49 0>,
1676 <0 50 0>,
1677 <0 51 0>;
1678 clocks = <&car 47>;
1679 };
1681 timerb@10dc8000 {
1682 compatible = "sirf,atlas7-tick";
1683 reg = <0x10dc8000 0x1000>;
1684 interrupts = <0 74 0>,
1685 <0 75 0>,
1686 <0 76 0>,
1687 <0 77 0>,
1688 <0 78 0>,
1689 <0 79 0>;
1690 clocks = <&car 47>;
1691 };
1693 vip0@10db0000 {
1694 compatible = "sirf,atlas7-vip0";
1695 reg = <0x10db0000 0x2000>;
1696 interrupts = <0 85 0>;
1697 sirf,vip_cma_size = <0xC00000>;
1698 };
1700 cvd@10db2000 {
1701 compatible = "sirf,cvd";
1702 reg = <0x10db2000 0x2000>;
1703 clocks = <&car 46>;
1704 };
1706 dmac2: dma-controller@10d50000 {
1707 cell-index = <2>;
1708 compatible = "sirf,atlas7-dmac";
1709 reg = <0x10d50000 0xffff>;
1710 interrupts = <0 55 0>;
1711 clocks = <&car 60>;
1712 dma-channels = <16>;
1713 #dma-cells = <1>;
1714 };
1716 dmac3: dma-controller@10d60000 {
1717 cell-index = <3>;
1718 compatible = "sirf,atlas7-dmac";
1719 reg = <0x10d60000 0xffff>;
1720 interrupts = <0 56 0>;
1721 clocks = <&car 61>;
1722 dma-channels = <16>;
1723 #dma-cells = <1>;
1724 };
1726 adc: adc@10d80000 {
1727 compatible = "sirf,atlas7-adc";
1728 reg = <0x10d80000 0xffff>;
1729 interrupts = <0 34 0>;
1730 clocks = <&car 49>;
1731 #io-channel-cells = <1>;
1732 };
1734 pulsec@10d90000 {
1735 compatible = "sirf,prima2-pulsec";
1736 reg = <0x10d90000 0xffff>;
1737 interrupts = <0 42 0>;
1738 clocks = <&car 54>;
1739 };
1741 audiom@10ED0000 {
1742 compatible = "sirf,nocfw-audiom";
1743 reg = <0x10ED0000 0x3000>;
1744 interrupts = <0 102 0>;
1745 };
1747 usp1: usp@10d30000 {
1748 cell-index = <1>;
1749 reg = <0x10d30000 0x1000>;
1750 fifosize = <512>;
1751 clocks = <&car 58>;
1752 dmas = <&dmac2 6>, <&dmac2 7>;
1753 dma-names = "rx", "tx";
1754 };
1756 usp2: usp@10d40000 {
1757 cell-index = <2>;
1758 reg = <0x10d40000 0x1000>;
1759 interrupts = <0 22 0>;
1760 clocks = <&car 59>;
1761 dmas = <&dmac2 12>, <&dmac2 13>;
1762 dma-names = "rx", "tx";
1763 #address-cells = <1>;
1764 #size-cells = <0>;
1765 status = "disabled";
1766 };
1767 };
1769 ddrm {
1770 compatible = "arteris, flexnoc", "simple-bus";
1771 #address-cells = <1>;
1772 #size-cells = <1>;
1773 ranges = <0x10820000 0x10820000 0x3000>,
1774 <0x10800000 0x10800000 0x2000>;
1775 ddrm@10820000 {
1776 compatible = "sirf,nocfw-ddrm";
1777 reg = <0x10820000 0x3000>;
1778 interrupts = <0 105 0>;
1779 };
1781 memory-controller@0x10800000 {
1782 compatible = "sirf,atlas7-memc";
1783 reg = <0x10800000 0x2000>;
1784 };
1786 };
1788 btm {
1789 compatible = "arteris, flexnoc", "simple-bus";
1790 #address-cells = <1>;
1791 #size-cells = <1>;
1792 ranges = <0x11002000 0x11002000 0x0000ffff>,
1793 <0x11010000 0x11010000 0x3000>,
1794 <0x11000000 0x11000000 0x1000>,
1795 <0x11001000 0x11001000 0x1000>;
1797 dmac4: dma-controller@11002000 {
1798 cell-index = <4>;
1799 compatible = "sirf,atlas7-dmac";
1800 reg = <0x11002000 0x1000>;
1801 interrupts = <0 99 0>;
1802 clocks = <&car 130>;
1803 dma-channels = <16>;
1804 #dma-cells = <1>;
1805 };
1806 uart6: uart@11000000 {
1807 cell-index = <6>;
1808 compatible = "sirf,atlas7-bt-uart",
1809 "sirf,atlas7-uart";
1810 reg = <0x11000000 0x1000>;
1811 interrupts = <0 100 0>;
1812 clocks = <&car 131>, <&car 133>, <&car 134>;
1813 clock-names = "uart", "general", "noc";
1814 fifosize = <128>;
1815 dmas = <&dmac4 12>, <&dmac4 13>;
1816 dma-names = "rx", "tx";
1817 status = "disabled";
1818 };
1820 usp3: usp@11001000 {
1821 compatible = "sirf,atlas7-bt-usp",
1822 "sirf,prima2-usp-pcm";
1823 cell-index = <3>;
1824 reg = <0x11001000 0x1000>;
1825 fifosize = <512>;
1826 clocks = <&car 132>, <&car 129>, <&car 133>,
1827 <&car 134>, <&car 135>;
1828 clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
1829 "noc_btm_io", "thbtm_io";
1830 dmas = <&dmac4 0>, <&dmac4 1>;
1831 dma-names = "rx", "tx";
1832 };
1834 btm@11010000 {
1835 compatible = "sirf,nocfw-btm";
1836 reg = <0x11010000 0x3000>;
1837 };
1838 };
1840 rtcm {
1841 compatible = "arteris, flexnoc", "simple-bus";
1842 #address-cells = <1>;
1843 #size-cells = <1>;
1844 ranges = <0x18810000 0x18810000 0x3000>,
1845 <0x18840000 0x18840000 0x1000>,
1846 <0x18890000 0x18890000 0x1000>,
1847 <0x188B0000 0x188B0000 0x10000>,
1848 <0x188D0000 0x188D0000 0x1000>;
1849 rtcm@18810000 {
1850 compatible = "sirf,nocfw-rtcm";
1851 reg = <0x18810000 0x3000>;
1852 interrupts = <0 109 0>;
1853 };
1855 gpio_2: gpio_rtcm@18890000 {
1856 #gpio-cells = <2>;
1857 #interrupt-cells = <2>;
1858 compatible = "sirf,atlas7-gpio";
1859 reg = <0x18890000 0x1000>;
1860 interrupts = <0 47 0>;
1861 gpio-controller;
1862 interrupt-controller;
1864 gpio-banks = <1>;
1865 gpio-ranges = <&pinctrl 0 0 0>;
1866 gpio-ranges-group-names = "rtc_gpio_grp";
1867 };
1869 rtc-iobg@18840000 {
1870 compatible = "sirf,prima2-rtciobg",
1871 "sirf-prima2-rtciobg-bus",
1872 "simple-bus";
1873 #address-cells = <1>;
1874 #size-cells = <1>;
1875 reg = <0x18840000 0x1000>;
1877 sysrtc@2000 {
1878 compatible = "sirf,prima2-sysrtc";
1879 reg = <0x2000 0x100>;
1880 interrupts = <0 52 0>;
1881 };
1882 pwrc@3000 {
1883 compatible = "sirf,atlas7-pwrc";
1884 reg = <0x3000 0x100>;
1885 };
1886 };
1888 qspi: flash@188B0000 {
1889 cell-index = <0>;
1890 compatible = "sirf,atlas7-qspi-nor";
1891 reg = <0x188B0000 0x10000>;
1892 interrupts = <0 15 0>;
1893 #address-cells = <1>;
1894 #size-cells = <0>;
1895 };
1897 retain@0x188D0000 {
1898 compatible = "sirf,atlas7-retain";
1899 reg = <0x188D0000 0x1000>;
1900 };
1902 };
1903 disp-iobg {
1904 /* lcdc0 */
1905 compatible = "simple-bus";
1906 #address-cells = <1>;
1907 #size-cells = <1>;
1908 ranges = <0x13100000 0x13100000 0x20000>,
1909 <0x10e10000 0x10e10000 0x10000>,
1910 <0x17010000 0x17010000 0x10000>;
1912 lcd@13100000 {
1913 compatible = "sirf,atlas7-lcdc";
1914 reg = <0x13100000 0x10000>;
1915 interrupts = <0 30 0>;
1916 clocks = <&car 79>;
1917 };
1918 vpp@13110000 {
1919 compatible = "sirf,atlas7-vpp";
1920 reg = <0x13110000 0x10000>;
1921 interrupts = <0 31 0>;
1922 clocks = <&car 78>;
1923 resets = <&car 29>;
1924 };
1925 lvds@10e10000 {
1926 compatible = "sirf,atlas7-lvdsc";
1927 reg = <0x10e10000 0x10000>;
1928 interrupts = <0 64 0>;
1929 clocks = <&car 54>;
1930 resets = <&car 29>;
1931 };
1932 g2d@17010000 {
1933 compatible = "sirf, atlas7-g2d";
1934 reg = <0x17010000 0x10000>;
1935 interrupts = <0 61 0>;
1936 clocks = <&car 104>;
1937 };
1939 };
1941 graphics-iobg {
1942 compatible = "simple-bus";
1943 #address-cells = <1>;
1944 #size-cells = <1>;
1945 ranges = <0x12000000 0x12000000 0x1000000>;
1947 graphics@12000000 {
1948 compatible = "powervr,sgx531";
1949 reg = <0x12000000 0x1000000>;
1950 interrupts = <0 6 0>;
1951 clocks = <&car 126>;
1952 };
1953 };
1954 };
1955 };