arch/arm/boot/dts/bcm-cygnus.dtsi

   1 /*
   2  *  BSD LICENSE
   3  *
   4  *  Copyright(c) 2014 Broadcom Corporation.  All rights reserved.
   5  *
   6  *  Redistribution and use in source and binary forms, with or without
   7  *  modification, are permitted provided that the following conditions
   8  *  are met:
   9  *
  10  *    * Redistributions of source code must retain the above copyright
  11  *      notice, this list of conditions and the following disclaimer.
  12  *    * Redistributions in binary form must reproduce the above copyright
  13  *      notice, this list of conditions and the following disclaimer in
  14  *      the documentation and/or other materials provided with the
  15  *      distribution.
  16  *    * Neither the name of Broadcom Corporation nor the names of its
  17  *      contributors may be used to endorse or promote products derived
  18  *      from this software without specific prior written permission.
  19  *
  20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <dt-bindings/interrupt-controller/arm-gic.h>
  34 #include <dt-bindings/interrupt-controller/irq.h>
  35 #include <dt-bindings/clock/bcm-cygnus.h>
  36
  37 / {
  38         #address-cells = <1>;
  39         #size-cells = <1>;
  40         compatible = "brcm,cygnus";
  41         model = "Broadcom Cygnus SoC";
  42         interrupt-parent = <&gic>;
  43
  44         aliases {
  45                 ethernet0 = &eth0;
  46         };
  47
  48         memory@0 {
  49                 device_type = "memory";
  50                 reg = <0 0>;
  51         };
  52
  53         cpus {
  54                 #address-cells = <1>;
  55                 #size-cells = <0>;
  56
  57                 cpu@0 {
  58                         device_type = "cpu";
  59                         compatible = "arm,cortex-a9";
  60                         next-level-cache = <&L2>;
  61                         reg = <0x0>;
  62                 };
  63         };
  64
  65         /include/ "bcm-cygnus-clock.dtsi"
  66
  67         pmu {
  68                 compatible = "arm,cortex-a9-pmu";
  69                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
  70         };
  71
  72         core@19000000 {
  73                 compatible = "simple-bus";
  74                 ranges = <0x00000000 0x19000000 0x1000000>;
  75                 #address-cells = <1>;
  76                 #size-cells = <1>;
  77
  78                 timer@20200 {
  79                         compatible = "arm,cortex-a9-global-timer";
  80                         reg = <0x20200 0x100>;
  81                         interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
  82                         clocks = <&periph_clk>;
  83                 };
  84
  85                 gic: interrupt-controller@21000 {
  86                         compatible = "arm,cortex-a9-gic";
  87                         #interrupt-cells = <3>;
  88                         #address-cells = <0>;
  89                         interrupt-controller;
  90                         reg = <0x21000 0x1000>,
  91                               <0x20100 0x100>;
  92                 };
  93
  94                 L2: cache-controller@22000 {
  95                         compatible = "arm,pl310-cache";
  96                         reg = <0x22000 0x1000>;
  97                         cache-unified;
  98                         cache-level = <2>;
  99                 };
 100         };
 101
 102         axi {
 103                 compatible = "simple-bus";
 104                 ranges;
 105                 #address-cells = <1>;
 106                 #size-cells = <1>;
 107
 108                 otp: otp@301c800 {
 109                         compatible = "brcm,ocotp";
 110                         reg = <0x0301c800 0x2c>;
 111                         brcm,ocotp-size = <2048>;
 112                         status = "disabled";
 113                 };
 114
 115                 pcie_phy: phy@301d0a0 {
 116                         compatible = "brcm,cygnus-pcie-phy";
 117                         reg = <0x0301d0a0 0x14>;
 118                         #address-cells = <1>;
 119                         #size-cells = <0>;
 120
 121                         pcie0_phy: phy@0 {
 122                                 reg = <0>;
 123                                 #phy-cells = <0>;
 124                         };
 125
 126                         pcie1_phy: phy@1 {
 127                                 reg = <1>;
 128                                 #phy-cells = <0>;
 129                         };
 130                 };
 131
 132                 pinctrl: pinctrl@301d0c8 {
 133                         compatible = "brcm,cygnus-pinmux";
 134                         reg = <0x0301d0c8 0x30>,
 135                               <0x0301d24c 0x2c>;
 136
 137                         spi_0: spi_0 {
 138                                 function = "spi0";
 139                                 groups = "spi0_grp";
 140                         };
 141
 142                         spi_1: spi_1 {
 143                                 function = "spi1";
 144                                 groups = "spi1_grp";
 145                         };
 146
 147                         spi_2: spi_2 {
 148                                 function = "spi2";
 149                                 groups = "spi2_grp";
 150                         };
 151                 };
 152
 153                 mailbox: mailbox@3024024 {
 154                         compatible = "brcm,iproc-mailbox";
 155                         reg = <0x03024024 0x40>;
 156                         interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
 157                         #interrupt-cells = <1>;
 158                         interrupt-controller;
 159                         #mbox-cells = <1>;
 160                 };
 161
 162                 gpio_crmu: gpio@3024800 {
 163                         compatible = "brcm,cygnus-crmu-gpio";
 164                         reg = <0x03024800 0x50>,
 165                               <0x03024008 0x18>;
 166                         ngpios = <6>;
 167                         #gpio-cells = <2>;
 168                         gpio-controller;
 169                         interrupt-controller;
 170                         interrupt-parent = <&mailbox>;
 171                         interrupts = <0>;
 172                 };
 173
 174                 mdio: mdio@18002000 {
 175                         compatible = "brcm,iproc-mdio";
 176                         reg = <0x18002000 0x8>;
 177                         #size-cells = <0>;
 178                         #address-cells = <1>;
 179                         status = "disabled";
 180
 181                         gphy0: ethernet-phy@0 {
 182                                 reg = <0>;
 183                         };
 184
 185                         gphy1: ethernet-phy@1 {
 186                                 reg = <1>;
 187                         };
 188                 };
 189
 190                 switch: switch@18007000 {
 191                         compatible = "brcm,bcm11360-srab", "brcm,cygnus-srab";
 192                         reg = <0x18007000 0x1000>;
 193                         status = "disabled";
 194
 195                         ports {
 196                                 #address-cells = <1>;
 197                                 #size-cells = <0>;
 198
 199                                 port@0 {
 200                                         reg = <0>;
 201                                         phy-handle = <&gphy0>;
 202                                         phy-mode = "rgmii";
 203                                 };
 204
 205                                 port@1 {
 206                                         reg = <1>;
 207                                         phy-handle = <&gphy1>;
 208                                         phy-mode = "rgmii";
 209                                 };
 210
 211                                 port@8 {
 212                                         reg = <8>;
 213                                         label = "cpu";
 214                                         ethernet = <&eth0>;
 215                                         fixed-link {
 216                                                 speed = <1000>;
 217                                                 full-duplex;
 218                                         };
 219                                 };
 220                         };
 221                 };
 222
 223                 i2c0: i2c@18008000 {
 224                         compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 225                         reg = <0x18008000 0x100>;
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 229                         clock-frequency = <100000>;
 230                         status = "disabled";
 231                 };
 232
 233                 wdt0: wdt@18009000 {
 234                         compatible = "arm,sp805" , "arm,primecell";
 235                         reg = <0x18009000 0x1000>;
 236                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 237                         clocks = <&axi81_clk>, <&axi81_clk>;
 238                         clock-names = "wdog_clk", "apb_pclk";
 239                 };
 240
 241                 gpio_ccm: gpio@1800a000 {
 242                         compatible = "brcm,cygnus-ccm-gpio";
 243                         reg = <0x1800a000 0x50>,
 244                               <0x0301d164 0x20>;
 245                         ngpios = <24>;
 246                         #gpio-cells = <2>;
 247                         gpio-controller;
 248                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
 249                         interrupt-controller;
 250                 };
 251
 252                 i2c1: i2c@1800b000 {
 253                         compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
 254                         reg = <0x1800b000 0x100>;
 255                         #address-cells = <1>;
 256                         #size-cells = <0>;
 257                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 258                         clock-frequency = <100000>;
 259                         status = "disabled";
 260                 };
 261
 262                 pcie0: pcie@18012000 {
 263                         compatible = "brcm,iproc-pcie";
 264                         reg = <0x18012000 0x1000>;
 265
 266                         #interrupt-cells = <1>;
 267                         interrupt-map-mask = <0 0 0 0>;
 268                         interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 269
 270                         linux,pci-domain = <0>;
 271
 272                         bus-range = <0x00 0xff>;
 273
 274                         #address-cells = <3>;
 275                         #size-cells = <2>;
 276                         device_type = "pci";
 277                         ranges = <0x81000000 0 0          0x28000000 0 0x00010000
 278                                   0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
 279
 280                         phys = <&pcie0_phy>;
 281                         phy-names = "pcie-phy";
 282
 283                         status = "disabled";
 284
 285                         msi-parent = <&msi0>;
 286                         msi0: msi-controller {
 287                                 compatible = "brcm,iproc-msi";
 288                                 msi-controller;
 289                                 interrupt-parent = <&gic>;
 290                                 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 291                                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 292                                              <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 293                                              <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 294                         };
 295                 };
 296
 297                 pcie1: pcie@18013000 {
 298                         compatible = "brcm,iproc-pcie";
 299                         reg = <0x18013000 0x1000>;
 300
 301                         #interrupt-cells = <1>;
 302                         interrupt-map-mask = <0 0 0 0>;
 303                         interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 304
 305                         linux,pci-domain = <1>;
 306
 307                         bus-range = <0x00 0xff>;
 308
 309                         #address-cells = <3>;
 310                         #size-cells = <2>;
 311                         device_type = "pci";
 312                         ranges = <0x81000000 0 0          0x48000000 0 0x00010000
 313                                   0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
 314
 315                         phys = <&pcie1_phy>;
 316                         phy-names = "pcie-phy";
 317
 318                         status = "disabled";
 319
 320                         msi-parent = <&msi1>;
 321                         msi1: msi-controller {
 322                                 compatible = "brcm,iproc-msi";
 323                                 msi-controller;
 324                                 interrupt-parent = <&gic>;
 325                                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 326                                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 327                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
 328                                              <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 329                         };
 330                 };
 331
 332                 dma0: dma@18018000 {
 333                         compatible = "arm,pl330", "arm,primecell";
 334                         reg = <0x18018000 0x1000>;
 335                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 336                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 337                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 338                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 339                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 340                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 341                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 342                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 343                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 344                         clocks = <&apb_clk>;
 345                         clock-names = "apb_pclk";
 346                         #dma-cells = <1>;
 347                 };
 348
 349                 uart0: serial@18020000 {
 350                         compatible = "snps,dw-apb-uart";
 351                         reg = <0x18020000 0x100>;
 352                         reg-shift = <2>;
 353                         reg-io-width = <4>;
 354                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 355                         clocks = <&axi81_clk>;
 356                         clock-frequency = <100000000>;
 357                         status = "disabled";
 358                 };
 359
 360                 uart1: serial@18021000 {
 361                         compatible = "snps,dw-apb-uart";
 362                         reg = <0x18021000 0x100>;
 363                         reg-shift = <2>;
 364                         reg-io-width = <4>;
 365                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 366                         clocks = <&axi81_clk>;
 367                         clock-frequency = <100000000>;
 368                         status = "disabled";
 369                 };
 370
 371                 uart2: serial@18022000 {
 372                         compatible = "snps,dw-apb-uart";
 373                         reg = <0x18022000 0x100>;
 374                         reg-shift = <2>;
 375                         reg-io-width = <4>;
 376                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 377                         clocks = <&axi81_clk>;
 378                         clock-frequency = <100000000>;
 379                         status = "disabled";
 380                 };
 381
 382                 uart3: serial@18023000 {
 383                         compatible = "snps,dw-apb-uart";
 384                         reg = <0x18023000 0x100>;
 385                         reg-shift = <2>;
 386                         reg-io-width = <4>;
 387                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&axi81_clk>;
 389                         clock-frequency = <100000000>;
 390                         status = "disabled";
 391                 };
 392
 393                 spi0: spi@18028000 {
 394                         compatible = "arm,pl022", "arm,primecell";
 395                         reg = <0x18028000 0x1000>;
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 399                         pinctrl-0 = <&spi_0>;
 400                         clocks = <&axi81_clk>;
 401                         clock-names = "apb_pclk";
 402                         status = "disabled";
 403                 };
 404
 405                 spi1: spi@18029000 {
 406                         compatible = "arm,pl022", "arm,primecell";
 407                         reg = <0x18029000 0x1000>;
 408                         #address-cells = <1>;
 409                         #size-cells = <0>;
 410                         interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 411                         pinctrl-0 = <&spi_1>;
 412                         clocks = <&axi81_clk>;
 413                         clock-names = "apb_pclk";
 414                         status = "disabled";
 415                 };
 416
 417                 spi2: spi@1802a000 {
 418                         compatible = "arm,pl022", "arm,primecell";
 419                         reg = <0x1802a000 0x1000>;
 420                         #address-cells = <1>;
 421                         #size-cells = <0>;
 422                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 423                         pinctrl-0 = <&spi_2>;
 424                         clocks = <&axi81_clk>;
 425                         clock-names = "apb_pclk";
 426                         status = "disabled";
 427                 };
 428
 429                 rng: rng@18032000 {
 430                         compatible = "brcm,iproc-rng200";
 431                         reg = <0x18032000 0x28>;
 432                 };
 433
 434                 sdhci0: sdhci@18041000 {
 435                         compatible = "brcm,sdhci-iproc-cygnus";
 436                         reg = <0x18041000 0x100>;
 437                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 438                         clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
 439                         bus-width = <4>;
 440                         sdhci,auto-cmd12;
 441                         status = "disabled";
 442                 };
 443
 444                 eth0: ethernet@18042000 {
 445                         compatible = "brcm,amac";
 446                         reg = <0x18042000 0x1000>,
 447                               <0x18110000 0x1000>;
 448                         reg-names = "amac_base", "idm_base";
 449                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 450                         status = "disabled";
 451                 };
 452
 453                 sdhci1: sdhci@18043000 {
 454                         compatible = "brcm,sdhci-iproc-cygnus";
 455                         reg = <0x18043000 0x100>;
 456                         interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 457                         clocks = <&lcpll0 BCM_CYGNUS_LCPLL0_SDIO_CLK>;
 458                         bus-width = <4>;
 459                         sdhci,auto-cmd12;
 460                         status = "disabled";
 461                 };
 462
 463                 nand: nand@18046000 {
 464                         compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
 465                         reg = <0x18046000 0x600>, <0xf8105408 0x600>,
 466                               <0x18046f00 0x20>;
 467                         reg-names = "nand", "iproc-idm", "iproc-ext";
 468                         interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 469
 470                         #address-cells = <1>;
 471                         #size-cells = <0>;
 472
 473                         brcm,nand-has-wp;
 474                 };
 475
 476                 ehci0: usb@18048000 {
 477                         compatible = "generic-ehci";
 478                         reg = <0x18048000 0x100>;
 479                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 480                         status = "disabled";
 481                 };
 482
 483                 ohci0: usb@18048800 {
 484                         compatible = "generic-ohci";
 485                         reg = <0x18048800 0x100>;
 486                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 487                         status = "disabled";
 488                 };
 489
 490                 clcd: clcd@180a0000 {
 491                         compatible = "arm,pl111", "arm,primecell";
 492                         reg = <0x180a0000 0x1000>;
 493                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 494                         interrupt-names = "combined";
 495                         clocks = <&axi41_clk>, <&apb_clk>;
 496                         clock-names = "clcdclk", "apb_pclk";
 497                         status = "disabled";
 498                 };
 499
 500                 v3d: v3d@180a2000 {
 501                         compatible = "brcm,cygnus-v3d";
 502                         reg = <0x180a2000 0x1000>;
 503                         clocks = <&mipipll BCM_CYGNUS_MIPIPLL_CH2_V3D>;
 504                         clock-names = "v3d_clk";
 505                         interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
 506                         status = "disabled";
 507                 };
 508
 509                 vc4: gpu {
 510                         compatible = "brcm,cygnus-vc4";
 511                 };
 512
 513                 gpio_asiu: gpio@180a5000 {
 514                         compatible = "brcm,cygnus-asiu-gpio";
 515                         reg = <0x180a5000 0x668>;
 516                         ngpios = <146>;
 517                         #gpio-cells = <2>;
 518                         gpio-controller;
 519
 520                         interrupt-controller;
 521                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
 522                         gpio-ranges = <&pinctrl 0 42 1>,
 523                                         <&pinctrl 1 44 3>,
 524                                         <&pinctrl 4 48 1>,
 525                                         <&pinctrl 5 50 3>,
 526                                         <&pinctrl 8 126 1>,
 527                                         <&pinctrl 9 155 1>,
 528                                         <&pinctrl 10 152 1>,
 529                                         <&pinctrl 11 154 1>,
 530                                         <&pinctrl 12 153 1>,
 531                                         <&pinctrl 13 127 3>,
 532                                         <&pinctrl 16 140 1>,
 533                                         <&pinctrl 17 145 7>,
 534                                         <&pinctrl 24 130 10>,
 535                                         <&pinctrl 34 141 4>,
 536                                         <&pinctrl 38 54 1>,
 537                                         <&pinctrl 39 56 3>,
 538                                         <&pinctrl 42 60 3>,
 539                                         <&pinctrl 45 64 3>,
 540                                         <&pinctrl 48 68 2>,
 541                                         <&pinctrl 50 84 6>,
 542                                         <&pinctrl 56 94 6>,
 543                                         <&pinctrl 62 72 1>,
 544                                         <&pinctrl 63 70 1>,
 545                                         <&pinctrl 64 80 1>,
 546                                         <&pinctrl 65 74 3>,
 547                                         <&pinctrl 68 78 1>,
 548                                         <&pinctrl 69 82 1>,
 549                                         <&pinctrl 70 156 17>,
 550                                         <&pinctrl 87 104 12>,
 551                                         <&pinctrl 99 102 2>,
 552                                         <&pinctrl 101 90 4>,
 553                                         <&pinctrl 105 116 6>,
 554                                         <&pinctrl 111 100 2>,
 555                                         <&pinctrl 113 122 4>,
 556                                         <&pinctrl 123 11 1>,
 557                                         <&pinctrl 124 38 4>,
 558                                         <&pinctrl 128 43 1>,
 559                                         <&pinctrl 129 47 1>,
 560                                         <&pinctrl 130 49 1>,
 561                                         <&pinctrl 131 53 1>,
 562                                         <&pinctrl 132 55 1>,
 563                                         <&pinctrl 133 59 1>,
 564                                         <&pinctrl 134 63 1>,
 565                                         <&pinctrl 135 67 1>,
 566                                         <&pinctrl 136 71 1>,
 567                                         <&pinctrl 137 73 1>,
 568                                         <&pinctrl 138 77 1>,
 569                                         <&pinctrl 139 79 1>,
 570                                         <&pinctrl 140 81 1>,
 571                                         <&pinctrl 141 83 1>,
 572                                         <&pinctrl 142 10 1>;
 573                 };
 574
 575                 ts_adc_syscon: ts_adc_syscon@180a6000 {
 576                         compatible = "brcm,iproc-ts-adc-syscon", "syscon";
 577                         reg = <0x180a6000 0xc30>;
 578                 };
 579
 580                 touchscreen: touchscreen@180a6000 {
 581                         compatible = "brcm,iproc-touchscreen";
 582                         #address-cells = <1>;
 583                         #size-cells = <1>;
 584                         ts_syscon = <&ts_adc_syscon>;
 585                         clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
 586                         clock-names = "tsc_clk";
 587                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 588                         status = "disabled";
 589                 };
 590
 591                 adc: adc@180a6000 {
 592                         compatible = "brcm,iproc-static-adc";
 593                         #io-channel-cells = <1>;
 594                         adc-syscon = <&ts_adc_syscon>;
 595                         clocks = <&asiu_clks BCM_CYGNUS_ASIU_ADC_CLK>;
 596                         clock-names = "tsc_clk";
 597                         interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
 598                         status = "disabled";
 599                 };
 600
 601                 pwm: pwm@180aa500 {
 602                         compatible = "brcm,kona-pwm";
 603                         reg = <0x180aa500 0xc4>;
 604                         #pwm-cells = <3>;
 605                         clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>;
 606                         status = "disabled";
 607                 };
 608
 609                 keypad: keypad@180ac000 {
 610                         compatible = "brcm,bcm-keypad";
 611                         reg = <0x180ac000 0x14c>;
 612                         interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
 613                         clocks = <&asiu_clks BCM_CYGNUS_ASIU_KEYPAD_CLK>;
 614                         clock-names = "peri_clk";
 615                         clock-frequency = <31250>;
 616                         pull-up-enabled;
 617                         col-debounce-filter-period = <0>;
 618                         status-debounce-filter-period = <0>;
 619                         row-output-enabled;
 620                         status = "disabled";
 621                 };
 622         };
 623 };