| blob | b83a864e2e8ba1a8326cadce40bfd6cac15830a2 |
1 #include <dt-bindings/pinctrl/bcm2835.h>
2 #include <dt-bindings/clock/bcm2835.h>
3 #include <dt-bindings/clock/bcm2835-aux.h>
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include <dt-bindings/soc/bcm2835-pm.h>
8 /* firmware-provided startup stubs live here, where the secondary CPUs are
9 * spinning.
10 */
11 /memreserve/ 0x00000000 0x00001000;
13 /* This include file covers the common peripherals and configuration between
14 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
15 * bcm2835.dtsi and bcm2836.dtsi.
16 */
18 / {
19 compatible = "brcm,bcm2835";
20 model = "BCM2835";
21 #address-cells = <1>;
22 #size-cells = <1>;
24 aliases {
25 serial0 = &uart0;
26 serial1 = &uart1;
27 };
29 chosen {
30 stdout-path = "serial0:115200n8";
31 };
33 rmem: reserved-memory {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 ranges;
38 cma: linux,cma {
39 compatible = "shared-dma-pool";
40 size = <0x4000000>; /* 64MB */
41 reusable;
42 linux,cma-default;
43 };
44 };
46 thermal-zones {
47 cpu_thermal: cpu-thermal {
48 polling-delay-passive = <0>;
49 polling-delay = <1000>;
51 trips {
52 cpu-crit {
53 temperature = <90000>;
54 hysteresis = <0>;
55 type = "critical";
56 };
57 };
59 cooling-maps {
60 };
61 };
62 };
64 soc {
65 compatible = "simple-bus";
66 #address-cells = <1>;
67 #size-cells = <1>;
69 system_timer: timer@7e003000 {
70 compatible = "brcm,bcm2835-system-timer";
71 reg = <0x7e003000 0x1000>;
72 interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
73 /* This could be a reference to BCM2835_CLOCK_TIMER,
74 * but we don't have the driver using the common clock
75 * support yet.
76 */
77 clock-frequency = <1000000>;
78 };
80 txp: txp@7e004000 {
81 compatible = "brcm,bcm2835-txp";
82 reg = <0x7e004000 0x20>;
83 interrupts = <1 11>;
84 };
86 clocks: cprman@7e101000 {
87 compatible = "brcm,bcm2835-cprman";
88 #clock-cells = <1>;
89 reg = <0x7e101000 0x2000>;
91 /* CPRMAN derives almost everything from the
92 * platform's oscillator. However, the DSI
93 * pixel clocks come from the DSI analog PHY.
94 */
95 clocks = <&clk_osc>,
96 <&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
97 <&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
98 };
100 mailbox: mailbox@7e00b880 {
101 compatible = "brcm,bcm2835-mbox";
102 reg = <0x7e00b880 0x40>;
103 interrupts = <0 1>;
104 #mbox-cells = <0>;
105 };
107 gpio: gpio@7e200000 {
108 compatible = "brcm,bcm2835-gpio";
109 reg = <0x7e200000 0xb4>;
110 /*
111 * The GPIO IP block is designed for 3 banks of GPIOs.
112 * Each bank has a GPIO interrupt for itself.
113 * There is an overall "any bank" interrupt.
114 * In order, these are GIC interrupts 17, 18, 19, 20.
115 * Since the BCM2835 only has 2 banks, the 2nd bank
116 * interrupt output appears to be mirrored onto the
117 * 3rd bank's interrupt signal.
118 * So, a bank0 interrupt shows up on 17, 20, and
119 * a bank1 interrupt shows up on 18, 19, 20!
120 */
121 interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
123 gpio-controller;
124 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <2>;
129 /* Defines common pin muxing groups
130 *
131 * While each pin can have its mux selected
132 * for various functions individually, some
133 * groups only make sense to switch to a
134 * particular function together.
135 */
136 dpi_gpio0: dpi_gpio0 {
137 brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
138 12 13 14 15 16 17 18 19
139 20 21 22 23 24 25 26 27>;
140 brcm,function = <BCM2835_FSEL_ALT2>;
141 };
142 emmc_gpio22: emmc_gpio22 {
143 brcm,pins = <22 23 24 25 26 27>;
144 brcm,function = <BCM2835_FSEL_ALT3>;
145 };
146 emmc_gpio34: emmc_gpio34 {
147 brcm,pins = <34 35 36 37 38 39>;
148 brcm,function = <BCM2835_FSEL_ALT3>;
149 brcm,pull = <BCM2835_PUD_OFF
150 BCM2835_PUD_UP
151 BCM2835_PUD_UP
152 BCM2835_PUD_UP
153 BCM2835_PUD_UP
154 BCM2835_PUD_UP>;
155 };
156 emmc_gpio48: emmc_gpio48 {
157 brcm,pins = <48 49 50 51 52 53>;
158 brcm,function = <BCM2835_FSEL_ALT3>;
159 };
161 gpclk0_gpio4: gpclk0_gpio4 {
162 brcm,pins = <4>;
163 brcm,function = <BCM2835_FSEL_ALT0>;
164 };
165 gpclk1_gpio5: gpclk1_gpio5 {
166 brcm,pins = <5>;
167 brcm,function = <BCM2835_FSEL_ALT0>;
168 };
169 gpclk1_gpio42: gpclk1_gpio42 {
170 brcm,pins = <42>;
171 brcm,function = <BCM2835_FSEL_ALT0>;
172 };
173 gpclk1_gpio44: gpclk1_gpio44 {
174 brcm,pins = <44>;
175 brcm,function = <BCM2835_FSEL_ALT0>;
176 };
177 gpclk2_gpio6: gpclk2_gpio6 {
178 brcm,pins = <6>;
179 brcm,function = <BCM2835_FSEL_ALT0>;
180 };
181 gpclk2_gpio43: gpclk2_gpio43 {
182 brcm,pins = <43>;
183 brcm,function = <BCM2835_FSEL_ALT0>;
184 brcm,pull = <BCM2835_PUD_OFF>;
185 };
187 i2c0_gpio0: i2c0_gpio0 {
188 brcm,pins = <0 1>;
189 brcm,function = <BCM2835_FSEL_ALT0>;
190 };
191 i2c0_gpio28: i2c0_gpio28 {
192 brcm,pins = <28 29>;
193 brcm,function = <BCM2835_FSEL_ALT0>;
194 };
195 i2c0_gpio44: i2c0_gpio44 {
196 brcm,pins = <44 45>;
197 brcm,function = <BCM2835_FSEL_ALT1>;
198 };
199 i2c1_gpio2: i2c1_gpio2 {
200 brcm,pins = <2 3>;
201 brcm,function = <BCM2835_FSEL_ALT0>;
202 };
203 i2c1_gpio44: i2c1_gpio44 {
204 brcm,pins = <44 45>;
205 brcm,function = <BCM2835_FSEL_ALT2>;
206 };
208 jtag_gpio22: jtag_gpio22 {
209 brcm,pins = <22 23 24 25 26 27>;
210 brcm,function = <BCM2835_FSEL_ALT4>;
211 };
213 pcm_gpio18: pcm_gpio18 {
214 brcm,pins = <18 19 20 21>;
215 brcm,function = <BCM2835_FSEL_ALT0>;
216 };
217 pcm_gpio28: pcm_gpio28 {
218 brcm,pins = <28 29 30 31>;
219 brcm,function = <BCM2835_FSEL_ALT2>;
220 };
222 sdhost_gpio48: sdhost_gpio48 {
223 brcm,pins = <48 49 50 51 52 53>;
224 brcm,function = <BCM2835_FSEL_ALT0>;
225 };
227 spi0_gpio7: spi0_gpio7 {
228 brcm,pins = <7 8 9 10 11>;
229 brcm,function = <BCM2835_FSEL_ALT0>;
230 };
231 spi0_gpio35: spi0_gpio35 {
232 brcm,pins = <35 36 37 38 39>;
233 brcm,function = <BCM2835_FSEL_ALT0>;
234 };
235 spi1_gpio16: spi1_gpio16 {
236 brcm,pins = <16 17 18 19 20 21>;
237 brcm,function = <BCM2835_FSEL_ALT4>;
238 };
239 spi2_gpio40: spi2_gpio40 {
240 brcm,pins = <40 41 42 43 44 45>;
241 brcm,function = <BCM2835_FSEL_ALT4>;
242 };
244 uart0_gpio14: uart0_gpio14 {
245 brcm,pins = <14 15>;
246 brcm,function = <BCM2835_FSEL_ALT0>;
247 };
248 /* Separate from the uart0_gpio14 group
249 * because it conflicts with spi1_gpio16, and
250 * people often run uart0 on the two pins
251 * without flow control.
252 */
253 uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
254 brcm,pins = <16 17>;
255 brcm,function = <BCM2835_FSEL_ALT3>;
256 };
257 uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
258 brcm,pins = <30 31>;
259 brcm,function = <BCM2835_FSEL_ALT3>;
260 brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
261 };
262 uart0_gpio32: uart0_gpio32 {
263 brcm,pins = <32 33>;
264 brcm,function = <BCM2835_FSEL_ALT3>;
265 brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
266 };
267 uart0_gpio36: uart0_gpio36 {
268 brcm,pins = <36 37>;
269 brcm,function = <BCM2835_FSEL_ALT2>;
270 };
271 uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
272 brcm,pins = <38 39>;
273 brcm,function = <BCM2835_FSEL_ALT2>;
274 };
276 uart1_gpio14: uart1_gpio14 {
277 brcm,pins = <14 15>;
278 brcm,function = <BCM2835_FSEL_ALT5>;
279 };
280 uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
281 brcm,pins = <16 17>;
282 brcm,function = <BCM2835_FSEL_ALT5>;
283 };
284 uart1_gpio32: uart1_gpio32 {
285 brcm,pins = <32 33>;
286 brcm,function = <BCM2835_FSEL_ALT5>;
287 };
288 uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
289 brcm,pins = <30 31>;
290 brcm,function = <BCM2835_FSEL_ALT5>;
291 };
292 uart1_gpio40: uart1_gpio40 {
293 brcm,pins = <40 41>;
294 brcm,function = <BCM2835_FSEL_ALT5>;
295 };
296 uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
297 brcm,pins = <42 43>;
298 brcm,function = <BCM2835_FSEL_ALT5>;
299 };
300 };
302 uart0: serial@7e201000 {
303 compatible = "arm,pl011", "arm,primecell";
304 reg = <0x7e201000 0x200>;
305 interrupts = <2 25>;
306 clocks = <&clocks BCM2835_CLOCK_UART>,
307 <&clocks BCM2835_CLOCK_VPU>;
308 clock-names = "uartclk", "apb_pclk";
309 arm,primecell-periphid = <0x00241011>;
310 };
312 sdhost: mmc@7e202000 {
313 compatible = "brcm,bcm2835-sdhost";
314 reg = <0x7e202000 0x100>;
315 interrupts = <2 24>;
316 clocks = <&clocks BCM2835_CLOCK_VPU>;
317 status = "disabled";
318 };
320 i2s: i2s@7e203000 {
321 compatible = "brcm,bcm2835-i2s";
322 reg = <0x7e203000 0x24>;
323 clocks = <&clocks BCM2835_CLOCK_PCM>;
324 status = "disabled";
325 };
327 spi: spi@7e204000 {
328 compatible = "brcm,bcm2835-spi";
329 reg = <0x7e204000 0x200>;
330 interrupts = <2 22>;
331 clocks = <&clocks BCM2835_CLOCK_VPU>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 status = "disabled";
335 };
337 i2c0: i2c@7e205000 {
338 compatible = "brcm,bcm2835-i2c";
339 reg = <0x7e205000 0x200>;
340 interrupts = <2 21>;
341 clocks = <&clocks BCM2835_CLOCK_VPU>;
342 #address-cells = <1>;
343 #size-cells = <0>;
344 status = "disabled";
345 };
347 dpi: dpi@7e208000 {
348 compatible = "brcm,bcm2835-dpi";
349 reg = <0x7e208000 0x8c>;
350 clocks = <&clocks BCM2835_CLOCK_VPU>,
351 <&clocks BCM2835_CLOCK_DPI>;
352 clock-names = "core", "pixel";
353 #address-cells = <1>;
354 #size-cells = <0>;
355 status = "disabled";
356 };
358 dsi0: dsi@7e209000 {
359 compatible = "brcm,bcm2835-dsi0";
360 reg = <0x7e209000 0x78>;
361 interrupts = <2 4>;
362 #address-cells = <1>;
363 #size-cells = <0>;
364 #clock-cells = <1>;
366 clocks = <&clocks BCM2835_PLLA_DSI0>,
367 <&clocks BCM2835_CLOCK_DSI0E>,
368 <&clocks BCM2835_CLOCK_DSI0P>;
369 clock-names = "phy", "escape", "pixel";
371 clock-output-names = "dsi0_byte",
372 "dsi0_ddr2",
373 "dsi0_ddr";
375 status = "disabled";
376 };
378 aux: aux@7e215000 {
379 compatible = "brcm,bcm2835-aux";
380 #clock-cells = <1>;
381 reg = <0x7e215000 0x8>;
382 clocks = <&clocks BCM2835_CLOCK_VPU>;
383 };
385 uart1: serial@7e215040 {
386 compatible = "brcm,bcm2835-aux-uart";
387 reg = <0x7e215040 0x40>;
388 interrupts = <1 29>;
389 clocks = <&aux BCM2835_AUX_CLOCK_UART>;
390 status = "disabled";
391 };
393 spi1: spi@7e215080 {
394 compatible = "brcm,bcm2835-aux-spi";
395 reg = <0x7e215080 0x40>;
396 interrupts = <1 29>;
397 clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
398 #address-cells = <1>;
399 #size-cells = <0>;
400 status = "disabled";
401 };
403 spi2: spi@7e2150c0 {
404 compatible = "brcm,bcm2835-aux-spi";
405 reg = <0x7e2150c0 0x40>;
406 interrupts = <1 29>;
407 clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
408 #address-cells = <1>;
409 #size-cells = <0>;
410 status = "disabled";
411 };
413 pwm: pwm@7e20c000 {
414 compatible = "brcm,bcm2835-pwm";
415 reg = <0x7e20c000 0x28>;
416 clocks = <&clocks BCM2835_CLOCK_PWM>;
417 assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
418 assigned-clock-rates = <10000000>;
419 #pwm-cells = <2>;
420 status = "disabled";
421 };
423 sdhci: sdhci@7e300000 {
424 compatible = "brcm,bcm2835-sdhci";
425 reg = <0x7e300000 0x100>;
426 interrupts = <2 30>;
427 clocks = <&clocks BCM2835_CLOCK_EMMC>;
428 status = "disabled";
429 };
431 hvs@7e400000 {
432 compatible = "brcm,bcm2835-hvs";
433 reg = <0x7e400000 0x6000>;
434 interrupts = <2 1>;
435 };
437 dsi1: dsi@7e700000 {
438 compatible = "brcm,bcm2835-dsi1";
439 reg = <0x7e700000 0x8c>;
440 interrupts = <2 12>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 #clock-cells = <1>;
445 clocks = <&clocks BCM2835_PLLD_DSI1>,
446 <&clocks BCM2835_CLOCK_DSI1E>,
447 <&clocks BCM2835_CLOCK_DSI1P>;
448 clock-names = "phy", "escape", "pixel";
450 clock-output-names = "dsi1_byte",
451 "dsi1_ddr2",
452 "dsi1_ddr";
454 status = "disabled";
455 };
457 i2c1: i2c@7e804000 {
458 compatible = "brcm,bcm2835-i2c";
459 reg = <0x7e804000 0x1000>;
460 interrupts = <2 21>;
461 clocks = <&clocks BCM2835_CLOCK_VPU>;
462 #address-cells = <1>;
463 #size-cells = <0>;
464 status = "disabled";
465 };
467 vec: vec@7e806000 {
468 compatible = "brcm,bcm2835-vec";
469 reg = <0x7e806000 0x1000>;
470 clocks = <&clocks BCM2835_CLOCK_VEC>;
471 interrupts = <2 27>;
472 status = "disabled";
473 };
475 usb: usb@7e980000 {
476 compatible = "brcm,bcm2835-usb";
477 reg = <0x7e980000 0x10000>;
478 interrupts = <1 9>;
479 #address-cells = <1>;
480 #size-cells = <0>;
481 clocks = <&clk_usb>;
482 clock-names = "otg";
483 phys = <&usbphy>;
484 phy-names = "usb2-phy";
485 };
486 };
488 clocks {
489 /* The oscillator is the root of the clock tree. */
490 clk_osc: clk-osc {
491 compatible = "fixed-clock";
492 #clock-cells = <0>;
493 clock-output-names = "osc";
494 clock-frequency = <19200000>;
495 };
497 clk_usb: clk-usb {
498 compatible = "fixed-clock";
499 #clock-cells = <0>;
500 clock-output-names = "otg";
501 clock-frequency = <480000000>;
502 };
503 };
505 usbphy: phy {
506 compatible = "usb-nop-xceiv";
507 #phy-cells = <0>;
508 };
509 };