| blob | 3bf90d9e33353b366d826b876d0b40101ad01e36 |
1 &l4_cfg { /* 0x4a000000 */
2 compatible = "ti,dra7-l4-cfg", "simple-bus";
3 reg = <0x4a000000 0x800>,
4 <0x4a000800 0x800>,
5 <0x4a001000 0x1000>;
6 reg-names = "ap", "la", "ia0";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 ranges = <0x00000000 0x4a000000 0x100000>, /* segment 0 */
10 <0x00100000 0x4a100000 0x100000>, /* segment 1 */
11 <0x00200000 0x4a200000 0x100000>; /* segment 2 */
13 segment@0 { /* 0x4a000000 */
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
18 <0x00000800 0x00000800 0x000800>, /* ap 1 */
19 <0x00001000 0x00001000 0x001000>, /* ap 2 */
20 <0x00002000 0x00002000 0x002000>, /* ap 3 */
21 <0x00004000 0x00004000 0x001000>, /* ap 4 */
22 <0x00005000 0x00005000 0x001000>, /* ap 5 */
23 <0x00006000 0x00006000 0x001000>, /* ap 6 */
24 <0x00008000 0x00008000 0x002000>, /* ap 7 */
25 <0x0000a000 0x0000a000 0x001000>, /* ap 8 */
26 <0x00056000 0x00056000 0x001000>, /* ap 9 */
27 <0x00057000 0x00057000 0x001000>, /* ap 10 */
28 <0x0005e000 0x0005e000 0x002000>, /* ap 11 */
29 <0x00060000 0x00060000 0x001000>, /* ap 12 */
30 <0x00080000 0x00080000 0x008000>, /* ap 13 */
31 <0x00088000 0x00088000 0x001000>, /* ap 14 */
32 <0x000a0000 0x000a0000 0x008000>, /* ap 15 */
33 <0x000a8000 0x000a8000 0x001000>, /* ap 16 */
34 <0x000d9000 0x000d9000 0x001000>, /* ap 17 */
35 <0x000da000 0x000da000 0x001000>, /* ap 18 */
36 <0x000dd000 0x000dd000 0x001000>, /* ap 19 */
37 <0x000de000 0x000de000 0x001000>, /* ap 20 */
38 <0x000e0000 0x000e0000 0x001000>, /* ap 21 */
39 <0x000e1000 0x000e1000 0x001000>, /* ap 22 */
40 <0x000f4000 0x000f4000 0x001000>, /* ap 23 */
41 <0x000f5000 0x000f5000 0x001000>, /* ap 24 */
42 <0x000f6000 0x000f6000 0x001000>, /* ap 25 */
43 <0x000f7000 0x000f7000 0x001000>, /* ap 26 */
44 <0x00090000 0x00090000 0x008000>, /* ap 59 */
45 <0x00098000 0x00098000 0x001000>; /* ap 60 */
47 target-module@2000 { /* 0x4a002000, ap 3 08.0 */
48 compatible = "ti,sysc-omap4", "ti,sysc";
49 reg = <0x2000 0x4>;
50 reg-names = "rev";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges = <0x0 0x2000 0x2000>;
55 scm: scm@0 {
56 compatible = "ti,dra7-scm-core", "simple-bus";
57 reg = <0 0x2000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges = <0 0 0x2000>;
62 scm_conf: scm_conf@0 {
63 compatible = "syscon", "simple-bus";
64 reg = <0x0 0x1400>;
65 #address-cells = <1>;
66 #size-cells = <1>;
67 ranges = <0 0x0 0x1400>;
69 pbias_regulator: pbias_regulator@e00 {
70 compatible = "ti,pbias-dra7", "ti,pbias-omap";
71 reg = <0xe00 0x4>;
72 syscon = <&scm_conf>;
73 pbias_mmc_reg: pbias_mmc_omap5 {
74 regulator-name = "pbias_mmc_omap5";
75 regulator-min-microvolt = <1800000>;
76 regulator-max-microvolt = <3300000>;
77 };
78 };
80 phy_gmii_sel: phy-gmii-sel {
81 compatible = "ti,dra7xx-phy-gmii-sel";
82 reg = <0x554 0x4>;
83 #phy-cells = <1>;
84 };
86 scm_conf_clocks: clocks {
87 #address-cells = <1>;
88 #size-cells = <0>;
89 };
90 };
92 dra7_pmx_core: pinmux@1400 {
93 compatible = "ti,dra7-padconf",
94 "pinctrl-single";
95 reg = <0x1400 0x0468>;
96 #address-cells = <1>;
97 #size-cells = <0>;
98 #pinctrl-cells = <1>;
99 #interrupt-cells = <1>;
100 interrupt-controller;
101 pinctrl-single,register-width = <32>;
102 pinctrl-single,function-mask = <0x3fffffff>;
103 };
105 scm_conf1: scm_conf@1c04 {
106 compatible = "syscon";
107 reg = <0x1c04 0x0020>;
108 #syscon-cells = <2>;
109 };
111 scm_conf_pcie: scm_conf@1c24 {
112 compatible = "syscon";
113 reg = <0x1c24 0x0024>;
114 };
116 sdma_xbar: dma-router@b78 {
117 compatible = "ti,dra7-dma-crossbar";
118 reg = <0xb78 0xfc>;
119 #dma-cells = <1>;
120 dma-requests = <205>;
121 ti,dma-safe-map = <0>;
122 dma-masters = <&sdma>;
123 };
125 edma_xbar: dma-router@c78 {
126 compatible = "ti,dra7-dma-crossbar";
127 reg = <0xc78 0x7c>;
128 #dma-cells = <2>;
129 dma-requests = <204>;
130 ti,dma-safe-map = <0>;
131 dma-masters = <&edma>;
132 };
133 };
134 };
136 target-module@5000 { /* 0x4a005000, ap 5 10.0 */
137 compatible = "ti,sysc-omap4", "ti,sysc";
138 reg = <0x5000 0x4>;
139 reg-names = "rev";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x0 0x5000 0x1000>;
144 cm_core_aon: cm_core_aon@0 {
145 compatible = "ti,dra7-cm-core-aon",
146 "simple-bus";
147 #address-cells = <1>;
148 #size-cells = <1>;
149 reg = <0 0x2000>;
150 ranges = <0 0 0x2000>;
152 cm_core_aon_clocks: clocks {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 };
157 cm_core_aon_clockdomains: clockdomains {
158 };
159 };
160 };
162 target-module@8000 { /* 0x4a008000, ap 7 0e.0 */
163 compatible = "ti,sysc-omap4", "ti,sysc";
164 reg = <0x8000 0x4>;
165 reg-names = "rev";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges = <0x0 0x8000 0x2000>;
170 cm_core: cm_core@0 {
171 compatible = "ti,dra7-cm-core", "simple-bus";
172 #address-cells = <1>;
173 #size-cells = <1>;
174 reg = <0 0x3000>;
175 ranges = <0 0 0x3000>;
177 cm_core_clocks: clocks {
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
182 cm_core_clockdomains: clockdomains {
183 };
184 };
185 };
187 target-module@56000 { /* 0x4a056000, ap 9 02.0 */
188 compatible = "ti,sysc-omap2", "ti,sysc";
189 reg = <0x56000 0x4>,
190 <0x5602c 0x4>,
191 <0x56028 0x4>;
192 reg-names = "rev", "sysc", "syss";
193 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
194 SYSC_OMAP2_EMUFREE |
195 SYSC_OMAP2_SOFTRESET |
196 SYSC_OMAP2_AUTOIDLE)>;
197 ti,sysc-midle = <SYSC_IDLE_FORCE>,
198 <SYSC_IDLE_NO>,
199 <SYSC_IDLE_SMART>,
200 <SYSC_IDLE_SMART_WKUP>;
201 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
202 <SYSC_IDLE_NO>,
203 <SYSC_IDLE_SMART>,
204 <SYSC_IDLE_SMART_WKUP>;
205 ti,syss-mask = <1>;
206 /* Domains (P, C): core_pwrdm, dma_clkdm */
207 clocks = <&dma_clkctrl DRA7_DMA_DMA_SYSTEM_CLKCTRL 0>;
208 clock-names = "fck";
209 #address-cells = <1>;
210 #size-cells = <1>;
211 ranges = <0x0 0x56000 0x1000>;
213 sdma: dma-controller@0 {
214 compatible = "ti,omap4430-sdma", "ti,omap-sdma";
215 reg = <0x0 0x1000>;
216 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
220 #dma-cells = <1>;
221 dma-channels = <32>;
222 dma-requests = <127>;
223 };
224 };
226 target-module@5e000 { /* 0x4a05e000, ap 11 1a.0 */
227 compatible = "ti,sysc";
228 status = "disabled";
229 #address-cells = <1>;
230 #size-cells = <1>;
231 ranges = <0x0 0x5e000 0x2000>;
232 };
234 target-module@80000 { /* 0x4a080000, ap 13 20.0 */
235 compatible = "ti,sysc-omap2", "ti,sysc";
236 reg = <0x80000 0x4>,
237 <0x80010 0x4>,
238 <0x80014 0x4>;
239 reg-names = "rev", "sysc", "syss";
240 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
241 SYSC_OMAP2_AUTOIDLE)>;
242 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
243 <SYSC_IDLE_NO>,
244 <SYSC_IDLE_SMART>;
245 ti,syss-mask = <1>;
246 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
247 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP1_CLKCTRL 0>;
248 clock-names = "fck";
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges = <0x0 0x80000 0x8000>;
253 ocp2scp@0 {
254 compatible = "ti,omap-ocp2scp";
255 #address-cells = <1>;
256 #size-cells = <1>;
257 ranges = <0 0 0x8000>;
258 reg = <0x0 0x20>;
260 usb2_phy1: phy@4000 {
261 compatible = "ti,dra7x-usb2", "ti,omap-usb2";
262 reg = <0x4000 0x400>;
263 syscon-phy-power = <&scm_conf 0x300>;
264 clocks = <&usb_phy1_always_on_clk32k>,
265 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
266 clock-names = "wkupclk",
267 "refclk";
268 #phy-cells = <0>;
269 };
271 usb2_phy2: phy@5000 {
272 compatible = "ti,dra7x-usb2-phy2",
273 "ti,omap-usb2";
274 reg = <0x5000 0x400>;
275 syscon-phy-power = <&scm_conf 0xe74>;
276 clocks = <&usb_phy2_always_on_clk32k>,
277 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 8>;
278 clock-names = "wkupclk",
279 "refclk";
280 #phy-cells = <0>;
281 };
283 usb3_phy1: phy@4400 {
284 compatible = "ti,omap-usb3";
285 reg = <0x4400 0x80>,
286 <0x4800 0x64>,
287 <0x4c00 0x40>;
288 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
289 syscon-phy-power = <&scm_conf 0x370>;
290 clocks = <&usb_phy3_always_on_clk32k>,
291 <&sys_clkin1>,
292 <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 8>;
293 clock-names = "wkupclk",
294 "sysclk",
295 "refclk";
296 #phy-cells = <0>;
297 };
298 };
299 };
301 target-module@90000 { /* 0x4a090000, ap 59 42.0 */
302 compatible = "ti,sysc-omap2", "ti,sysc";
303 reg = <0x90000 0x4>,
304 <0x90010 0x4>,
305 <0x90014 0x4>;
306 reg-names = "rev", "sysc", "syss";
307 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
308 SYSC_OMAP2_AUTOIDLE)>;
309 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
310 <SYSC_IDLE_NO>,
311 <SYSC_IDLE_SMART>;
312 ti,syss-mask = <1>;
313 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
314 clocks = <&l3init_clkctrl DRA7_L3INIT_OCP2SCP3_CLKCTRL 0>;
315 clock-names = "fck";
316 #address-cells = <1>;
317 #size-cells = <1>;
318 ranges = <0x0 0x90000 0x8000>;
320 ocp2scp@0 {
321 compatible = "ti,omap-ocp2scp";
322 #address-cells = <1>;
323 #size-cells = <1>;
324 ranges = <0 0 0x8000>;
325 reg = <0x0 0x20>;
327 pcie1_phy: pciephy@4000 {
328 compatible = "ti,phy-pipe3-pcie";
329 reg = <0x4000 0x80>, /* phy_rx */
330 <0x4400 0x64>; /* phy_tx */
331 reg-names = "phy_rx", "phy_tx";
332 syscon-phy-power = <&scm_conf_pcie 0x1c>;
333 syscon-pcs = <&scm_conf_pcie 0x10>;
334 clocks = <&dpll_pcie_ref_ck>,
335 <&dpll_pcie_ref_m2ldo_ck>,
336 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 8>,
337 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
338 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>,
339 <&optfclk_pciephy_div>,
340 <&sys_clkin1>;
341 clock-names = "dpll_ref", "dpll_ref_m2",
342 "wkupclk", "refclk",
343 "div-clk", "phy-div", "sysclk";
344 #phy-cells = <0>;
345 };
347 pcie2_phy: pciephy@5000 {
348 compatible = "ti,phy-pipe3-pcie";
349 reg = <0x5000 0x80>, /* phy_rx */
350 <0x5400 0x64>; /* phy_tx */
351 reg-names = "phy_rx", "phy_tx";
352 syscon-phy-power = <&scm_conf_pcie 0x20>;
353 syscon-pcs = <&scm_conf_pcie 0x10>;
354 clocks = <&dpll_pcie_ref_ck>,
355 <&dpll_pcie_ref_m2ldo_ck>,
356 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 8>,
357 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
358 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>,
359 <&optfclk_pciephy_div>,
360 <&sys_clkin1>;
361 clock-names = "dpll_ref", "dpll_ref_m2",
362 "wkupclk", "refclk",
363 "div-clk", "phy-div", "sysclk";
364 #phy-cells = <0>;
365 status = "disabled";
366 };
368 sata_phy: phy@6000 {
369 compatible = "ti,phy-pipe3-sata";
370 reg = <0x6000 0x80>, /* phy_rx */
371 <0x6400 0x64>, /* phy_tx */
372 <0x6800 0x40>; /* pll_ctrl */
373 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
374 syscon-phy-power = <&scm_conf 0x374>;
375 clocks = <&sys_clkin1>,
376 <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
377 clock-names = "sysclk", "refclk";
378 syscon-pllreset = <&scm_conf 0x3fc>;
379 #phy-cells = <0>;
380 };
381 };
382 };
384 target-module@a0000 { /* 0x4a0a0000, ap 15 40.0 */
385 compatible = "ti,sysc";
386 status = "disabled";
387 #address-cells = <1>;
388 #size-cells = <1>;
389 ranges = <0x0 0xa0000 0x8000>;
390 };
392 target-module@d9000 { /* 0x4a0d9000, ap 17 72.0 */
393 compatible = "ti,sysc-omap4-sr", "ti,sysc";
394 reg = <0xd9038 0x4>;
395 reg-names = "sysc";
396 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
397 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
398 <SYSC_IDLE_NO>,
399 <SYSC_IDLE_SMART>,
400 <SYSC_IDLE_SMART_WKUP>;
401 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
402 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_MPU_CLKCTRL 0>;
403 clock-names = "fck";
404 #address-cells = <1>;
405 #size-cells = <1>;
406 ranges = <0x0 0xd9000 0x1000>;
408 /* SmartReflex child device marked reserved in TRM */
409 };
411 target-module@dd000 { /* 0x4a0dd000, ap 19 18.0 */
412 compatible = "ti,sysc-omap4-sr", "ti,sysc";
413 reg = <0xdd038 0x4>;
414 reg-names = "sysc";
415 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
416 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
417 <SYSC_IDLE_NO>,
418 <SYSC_IDLE_SMART>,
419 <SYSC_IDLE_SMART_WKUP>;
420 /* Domains (P, C): coreaon_pwrdm, coreaon_clkdm */
421 clocks = <&coreaon_clkctrl DRA7_COREAON_SMARTREFLEX_CORE_CLKCTRL 0>;
422 clock-names = "fck";
423 #address-cells = <1>;
424 #size-cells = <1>;
425 ranges = <0x0 0xdd000 0x1000>;
427 /* SmartReflex child device marked reserved in TRM */
428 };
430 target-module@e0000 { /* 0x4a0e0000, ap 21 28.0 */
431 compatible = "ti,sysc";
432 status = "disabled";
433 #address-cells = <1>;
434 #size-cells = <1>;
435 ranges = <0x0 0xe0000 0x1000>;
436 };
438 target-module@f4000 { /* 0x4a0f4000, ap 23 04.0 */
439 compatible = "ti,sysc-omap4", "ti,sysc";
440 reg = <0xf4000 0x4>,
441 <0xf4010 0x4>;
442 reg-names = "rev", "sysc";
443 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
444 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
445 <SYSC_IDLE_NO>,
446 <SYSC_IDLE_SMART>;
447 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
448 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX1_CLKCTRL 0>;
449 clock-names = "fck";
450 #address-cells = <1>;
451 #size-cells = <1>;
452 ranges = <0x0 0xf4000 0x1000>;
454 mailbox1: mailbox@0 {
455 compatible = "ti,omap4-mailbox";
456 reg = <0x0 0x200>;
457 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
460 #mbox-cells = <1>;
461 ti,mbox-num-users = <3>;
462 ti,mbox-num-fifos = <8>;
463 status = "disabled";
464 };
465 };
467 target-module@f6000 { /* 0x4a0f6000, ap 25 78.0 */
468 compatible = "ti,sysc-omap2", "ti,sysc";
469 reg = <0xf6000 0x4>,
470 <0xf6010 0x4>,
471 <0xf6014 0x4>;
472 reg-names = "rev", "sysc", "syss";
473 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
474 SYSC_OMAP2_SOFTRESET |
475 SYSC_OMAP2_AUTOIDLE)>;
476 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
477 <SYSC_IDLE_NO>,
478 <SYSC_IDLE_SMART>;
479 ti,syss-mask = <1>;
480 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
481 clocks = <&l4cfg_clkctrl DRA7_L4CFG_SPINLOCK_CLKCTRL 0>;
482 clock-names = "fck";
483 #address-cells = <1>;
484 #size-cells = <1>;
485 ranges = <0x0 0xf6000 0x1000>;
487 hwspinlock: spinlock@0 {
488 compatible = "ti,omap4-hwspinlock";
489 reg = <0x0 0x1000>;
490 #hwlock-cells = <1>;
491 };
492 };
493 };
495 segment@100000 { /* 0x4a100000 */
496 compatible = "simple-bus";
497 #address-cells = <1>;
498 #size-cells = <1>;
499 ranges = <0x00002000 0x00102000 0x001000>, /* ap 27 */
500 <0x00003000 0x00103000 0x001000>, /* ap 28 */
501 <0x00008000 0x00108000 0x001000>, /* ap 29 */
502 <0x00009000 0x00109000 0x001000>, /* ap 30 */
503 <0x00040000 0x00140000 0x010000>, /* ap 31 */
504 <0x00050000 0x00150000 0x001000>, /* ap 32 */
505 <0x00051000 0x00151000 0x001000>, /* ap 33 */
506 <0x00052000 0x00152000 0x001000>, /* ap 34 */
507 <0x00053000 0x00153000 0x001000>, /* ap 35 */
508 <0x00054000 0x00154000 0x001000>, /* ap 36 */
509 <0x00055000 0x00155000 0x001000>, /* ap 37 */
510 <0x00056000 0x00156000 0x001000>, /* ap 38 */
511 <0x00057000 0x00157000 0x001000>, /* ap 39 */
512 <0x00058000 0x00158000 0x001000>, /* ap 40 */
513 <0x0005b000 0x0015b000 0x001000>, /* ap 41 */
514 <0x0005c000 0x0015c000 0x001000>, /* ap 42 */
515 <0x0005d000 0x0015d000 0x001000>, /* ap 45 */
516 <0x0005e000 0x0015e000 0x001000>, /* ap 46 */
517 <0x0005f000 0x0015f000 0x001000>, /* ap 47 */
518 <0x00060000 0x00160000 0x001000>, /* ap 48 */
519 <0x00061000 0x00161000 0x001000>, /* ap 49 */
520 <0x00062000 0x00162000 0x001000>, /* ap 50 */
521 <0x00063000 0x00163000 0x001000>, /* ap 51 */
522 <0x00064000 0x00164000 0x001000>, /* ap 52 */
523 <0x00065000 0x00165000 0x001000>, /* ap 53 */
524 <0x00066000 0x00166000 0x001000>, /* ap 54 */
525 <0x00067000 0x00167000 0x001000>, /* ap 55 */
526 <0x00068000 0x00168000 0x001000>, /* ap 56 */
527 <0x0006d000 0x0016d000 0x001000>, /* ap 57 */
528 <0x0006e000 0x0016e000 0x001000>, /* ap 58 */
529 <0x00071000 0x00171000 0x001000>, /* ap 61 */
530 <0x00072000 0x00172000 0x001000>, /* ap 62 */
531 <0x00073000 0x00173000 0x001000>, /* ap 63 */
532 <0x00074000 0x00174000 0x001000>, /* ap 64 */
533 <0x00075000 0x00175000 0x001000>, /* ap 65 */
534 <0x00076000 0x00176000 0x001000>, /* ap 66 */
535 <0x00077000 0x00177000 0x001000>, /* ap 67 */
536 <0x00078000 0x00178000 0x001000>, /* ap 68 */
537 <0x00081000 0x00181000 0x001000>, /* ap 69 */
538 <0x00082000 0x00182000 0x001000>, /* ap 70 */
539 <0x00083000 0x00183000 0x001000>, /* ap 71 */
540 <0x00084000 0x00184000 0x001000>, /* ap 72 */
541 <0x00085000 0x00185000 0x001000>, /* ap 73 */
542 <0x00086000 0x00186000 0x001000>, /* ap 74 */
543 <0x00087000 0x00187000 0x001000>, /* ap 75 */
544 <0x00088000 0x00188000 0x001000>, /* ap 76 */
545 <0x00069000 0x00169000 0x001000>, /* ap 103 */
546 <0x0006a000 0x0016a000 0x001000>, /* ap 104 */
547 <0x00079000 0x00179000 0x001000>, /* ap 105 */
548 <0x0007a000 0x0017a000 0x001000>, /* ap 106 */
549 <0x0006b000 0x0016b000 0x001000>, /* ap 107 */
550 <0x0006c000 0x0016c000 0x001000>, /* ap 108 */
551 <0x0007b000 0x0017b000 0x001000>, /* ap 121 */
552 <0x0007c000 0x0017c000 0x001000>, /* ap 122 */
553 <0x0007d000 0x0017d000 0x001000>, /* ap 123 */
554 <0x0007e000 0x0017e000 0x001000>, /* ap 124 */
555 <0x00059000 0x00159000 0x001000>, /* ap 125 */
556 <0x0005a000 0x0015a000 0x001000>; /* ap 126 */
558 target-module@2000 { /* 0x4a102000, ap 27 3c.0 */
559 compatible = "ti,sysc";
560 status = "disabled";
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges = <0x0 0x2000 0x1000>;
564 };
566 target-module@8000 { /* 0x4a108000, ap 29 1e.0 */
567 compatible = "ti,sysc";
568 status = "disabled";
569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges = <0x0 0x8000 0x1000>;
572 };
574 target-module@40000 { /* 0x4a140000, ap 31 06.0 */
575 compatible = "ti,sysc";
576 status = "disabled";
577 #address-cells = <1>;
578 #size-cells = <1>;
579 ranges = <0x0 0x40000 0x10000>;
580 };
582 target-module@51000 { /* 0x4a151000, ap 33 50.0 */
583 compatible = "ti,sysc";
584 status = "disabled";
585 #address-cells = <1>;
586 #size-cells = <1>;
587 ranges = <0x0 0x51000 0x1000>;
588 };
590 target-module@53000 { /* 0x4a153000, ap 35 54.0 */
591 compatible = "ti,sysc";
592 status = "disabled";
593 #address-cells = <1>;
594 #size-cells = <1>;
595 ranges = <0x0 0x53000 0x1000>;
596 };
598 target-module@55000 { /* 0x4a155000, ap 37 46.0 */
599 compatible = "ti,sysc";
600 status = "disabled";
601 #address-cells = <1>;
602 #size-cells = <1>;
603 ranges = <0x0 0x55000 0x1000>;
604 };
606 target-module@57000 { /* 0x4a157000, ap 39 58.0 */
607 compatible = "ti,sysc";
608 status = "disabled";
609 #address-cells = <1>;
610 #size-cells = <1>;
611 ranges = <0x0 0x57000 0x1000>;
612 };
614 target-module@59000 { /* 0x4a159000, ap 125 6a.0 */
615 compatible = "ti,sysc";
616 status = "disabled";
617 #address-cells = <1>;
618 #size-cells = <1>;
619 ranges = <0x0 0x59000 0x1000>;
620 };
622 target-module@5b000 { /* 0x4a15b000, ap 41 60.0 */
623 compatible = "ti,sysc";
624 status = "disabled";
625 #address-cells = <1>;
626 #size-cells = <1>;
627 ranges = <0x0 0x5b000 0x1000>;
628 };
630 target-module@5d000 { /* 0x4a15d000, ap 45 3a.0 */
631 compatible = "ti,sysc";
632 status = "disabled";
633 #address-cells = <1>;
634 #size-cells = <1>;
635 ranges = <0x0 0x5d000 0x1000>;
636 };
638 target-module@5f000 { /* 0x4a15f000, ap 47 56.0 */
639 compatible = "ti,sysc";
640 status = "disabled";
641 #address-cells = <1>;
642 #size-cells = <1>;
643 ranges = <0x0 0x5f000 0x1000>;
644 };
646 target-module@61000 { /* 0x4a161000, ap 49 32.0 */
647 compatible = "ti,sysc";
648 status = "disabled";
649 #address-cells = <1>;
650 #size-cells = <1>;
651 ranges = <0x0 0x61000 0x1000>;
652 };
654 target-module@63000 { /* 0x4a163000, ap 51 5c.0 */
655 compatible = "ti,sysc";
656 status = "disabled";
657 #address-cells = <1>;
658 #size-cells = <1>;
659 ranges = <0x0 0x63000 0x1000>;
660 };
662 target-module@65000 { /* 0x4a165000, ap 53 4e.0 */
663 compatible = "ti,sysc";
664 status = "disabled";
665 #address-cells = <1>;
666 #size-cells = <1>;
667 ranges = <0x0 0x65000 0x1000>;
668 };
670 target-module@67000 { /* 0x4a167000, ap 55 5e.0 */
671 compatible = "ti,sysc";
672 status = "disabled";
673 #address-cells = <1>;
674 #size-cells = <1>;
675 ranges = <0x0 0x67000 0x1000>;
676 };
678 target-module@69000 { /* 0x4a169000, ap 103 4a.0 */
679 compatible = "ti,sysc";
680 status = "disabled";
681 #address-cells = <1>;
682 #size-cells = <1>;
683 ranges = <0x0 0x69000 0x1000>;
684 };
686 target-module@6b000 { /* 0x4a16b000, ap 107 52.0 */
687 compatible = "ti,sysc";
688 status = "disabled";
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0x0 0x6b000 0x1000>;
692 };
694 target-module@6d000 { /* 0x4a16d000, ap 57 68.0 */
695 compatible = "ti,sysc";
696 status = "disabled";
697 #address-cells = <1>;
698 #size-cells = <1>;
699 ranges = <0x0 0x6d000 0x1000>;
700 };
702 target-module@71000 { /* 0x4a171000, ap 61 48.0 */
703 compatible = "ti,sysc";
704 status = "disabled";
705 #address-cells = <1>;
706 #size-cells = <1>;
707 ranges = <0x0 0x71000 0x1000>;
708 };
710 target-module@73000 { /* 0x4a173000, ap 63 2a.0 */
711 compatible = "ti,sysc";
712 status = "disabled";
713 #address-cells = <1>;
714 #size-cells = <1>;
715 ranges = <0x0 0x73000 0x1000>;
716 };
718 target-module@75000 { /* 0x4a175000, ap 65 64.0 */
719 compatible = "ti,sysc";
720 status = "disabled";
721 #address-cells = <1>;
722 #size-cells = <1>;
723 ranges = <0x0 0x75000 0x1000>;
724 };
726 target-module@77000 { /* 0x4a177000, ap 67 66.0 */
727 compatible = "ti,sysc";
728 status = "disabled";
729 #address-cells = <1>;
730 #size-cells = <1>;
731 ranges = <0x0 0x77000 0x1000>;
732 };
734 target-module@79000 { /* 0x4a179000, ap 105 34.0 */
735 compatible = "ti,sysc";
736 status = "disabled";
737 #address-cells = <1>;
738 #size-cells = <1>;
739 ranges = <0x0 0x79000 0x1000>;
740 };
742 target-module@7b000 { /* 0x4a17b000, ap 121 7c.0 */
743 compatible = "ti,sysc";
744 status = "disabled";
745 #address-cells = <1>;
746 #size-cells = <1>;
747 ranges = <0x0 0x7b000 0x1000>;
748 };
750 target-module@7d000 { /* 0x4a17d000, ap 123 7e.0 */
751 compatible = "ti,sysc";
752 status = "disabled";
753 #address-cells = <1>;
754 #size-cells = <1>;
755 ranges = <0x0 0x7d000 0x1000>;
756 };
758 target-module@81000 { /* 0x4a181000, ap 69 26.0 */
759 compatible = "ti,sysc";
760 status = "disabled";
761 #address-cells = <1>;
762 #size-cells = <1>;
763 ranges = <0x0 0x81000 0x1000>;
764 };
766 target-module@83000 { /* 0x4a183000, ap 71 2e.0 */
767 compatible = "ti,sysc";
768 status = "disabled";
769 #address-cells = <1>;
770 #size-cells = <1>;
771 ranges = <0x0 0x83000 0x1000>;
772 };
774 target-module@85000 { /* 0x4a185000, ap 73 36.0 */
775 compatible = "ti,sysc";
776 status = "disabled";
777 #address-cells = <1>;
778 #size-cells = <1>;
779 ranges = <0x0 0x85000 0x1000>;
780 };
782 target-module@87000 { /* 0x4a187000, ap 75 74.0 */
783 compatible = "ti,sysc";
784 status = "disabled";
785 #address-cells = <1>;
786 #size-cells = <1>;
787 ranges = <0x0 0x87000 0x1000>;
788 };
789 };
791 segment@200000 { /* 0x4a200000 */
792 compatible = "simple-bus";
793 #address-cells = <1>;
794 #size-cells = <1>;
795 ranges = <0x00018000 0x00218000 0x001000>, /* ap 43 */
796 <0x00019000 0x00219000 0x001000>, /* ap 44 */
797 <0x00000000 0x00200000 0x001000>, /* ap 77 */
798 <0x00001000 0x00201000 0x001000>, /* ap 78 */
799 <0x0000a000 0x0020a000 0x001000>, /* ap 79 */
800 <0x0000b000 0x0020b000 0x001000>, /* ap 80 */
801 <0x0000c000 0x0020c000 0x001000>, /* ap 81 */
802 <0x0000d000 0x0020d000 0x001000>, /* ap 82 */
803 <0x0000e000 0x0020e000 0x001000>, /* ap 83 */
804 <0x0000f000 0x0020f000 0x001000>, /* ap 84 */
805 <0x00010000 0x00210000 0x001000>, /* ap 85 */
806 <0x00011000 0x00211000 0x001000>, /* ap 86 */
807 <0x00012000 0x00212000 0x001000>, /* ap 87 */
808 <0x00013000 0x00213000 0x001000>, /* ap 88 */
809 <0x00014000 0x00214000 0x001000>, /* ap 89 */
810 <0x00015000 0x00215000 0x001000>, /* ap 90 */
811 <0x0002a000 0x0022a000 0x001000>, /* ap 91 */
812 <0x0002b000 0x0022b000 0x001000>, /* ap 92 */
813 <0x0001c000 0x0021c000 0x001000>, /* ap 93 */
814 <0x0001d000 0x0021d000 0x001000>, /* ap 94 */
815 <0x0001e000 0x0021e000 0x001000>, /* ap 95 */
816 <0x0001f000 0x0021f000 0x001000>, /* ap 96 */
817 <0x00020000 0x00220000 0x001000>, /* ap 97 */
818 <0x00021000 0x00221000 0x001000>, /* ap 98 */
819 <0x00024000 0x00224000 0x001000>, /* ap 99 */
820 <0x00025000 0x00225000 0x001000>, /* ap 100 */
821 <0x00026000 0x00226000 0x001000>, /* ap 101 */
822 <0x00027000 0x00227000 0x001000>, /* ap 102 */
823 <0x0002c000 0x0022c000 0x001000>, /* ap 109 */
824 <0x0002d000 0x0022d000 0x001000>, /* ap 110 */
825 <0x0002e000 0x0022e000 0x001000>, /* ap 111 */
826 <0x0002f000 0x0022f000 0x001000>, /* ap 112 */
827 <0x00030000 0x00230000 0x001000>, /* ap 113 */
828 <0x00031000 0x00231000 0x001000>, /* ap 114 */
829 <0x00032000 0x00232000 0x001000>, /* ap 115 */
830 <0x00033000 0x00233000 0x001000>, /* ap 116 */
831 <0x00034000 0x00234000 0x001000>, /* ap 117 */
832 <0x00035000 0x00235000 0x001000>, /* ap 118 */
833 <0x00036000 0x00236000 0x001000>, /* ap 119 */
834 <0x00037000 0x00237000 0x001000>, /* ap 120 */
835 <0x0001a000 0x0021a000 0x001000>, /* ap 127 */
836 <0x0001b000 0x0021b000 0x001000>; /* ap 128 */
838 target-module@0 { /* 0x4a200000, ap 77 3e.0 */
839 compatible = "ti,sysc";
840 status = "disabled";
841 #address-cells = <1>;
842 #size-cells = <1>;
843 ranges = <0x0 0x0 0x1000>;
844 };
846 target-module@a000 { /* 0x4a20a000, ap 79 30.0 */
847 compatible = "ti,sysc";
848 status = "disabled";
849 #address-cells = <1>;
850 #size-cells = <1>;
851 ranges = <0x0 0xa000 0x1000>;
852 };
854 target-module@c000 { /* 0x4a20c000, ap 81 0c.0 */
855 compatible = "ti,sysc";
856 status = "disabled";
857 #address-cells = <1>;
858 #size-cells = <1>;
859 ranges = <0x0 0xc000 0x1000>;
860 };
862 target-module@e000 { /* 0x4a20e000, ap 83 22.0 */
863 compatible = "ti,sysc";
864 status = "disabled";
865 #address-cells = <1>;
866 #size-cells = <1>;
867 ranges = <0x0 0xe000 0x1000>;
868 };
870 target-module@10000 { /* 0x4a210000, ap 85 14.0 */
871 compatible = "ti,sysc";
872 status = "disabled";
873 #address-cells = <1>;
874 #size-cells = <1>;
875 ranges = <0x0 0x10000 0x1000>;
876 };
878 target-module@12000 { /* 0x4a212000, ap 87 16.0 */
879 compatible = "ti,sysc";
880 status = "disabled";
881 #address-cells = <1>;
882 #size-cells = <1>;
883 ranges = <0x0 0x12000 0x1000>;
884 };
886 target-module@14000 { /* 0x4a214000, ap 89 1c.0 */
887 compatible = "ti,sysc";
888 status = "disabled";
889 #address-cells = <1>;
890 #size-cells = <1>;
891 ranges = <0x0 0x14000 0x1000>;
892 };
894 target-module@18000 { /* 0x4a218000, ap 43 12.0 */
895 compatible = "ti,sysc";
896 status = "disabled";
897 #address-cells = <1>;
898 #size-cells = <1>;
899 ranges = <0x0 0x18000 0x1000>;
900 };
902 target-module@1a000 { /* 0x4a21a000, ap 127 7a.0 */
903 compatible = "ti,sysc";
904 status = "disabled";
905 #address-cells = <1>;
906 #size-cells = <1>;
907 ranges = <0x0 0x1a000 0x1000>;
908 };
910 target-module@1c000 { /* 0x4a21c000, ap 93 38.0 */
911 compatible = "ti,sysc";
912 status = "disabled";
913 #address-cells = <1>;
914 #size-cells = <1>;
915 ranges = <0x0 0x1c000 0x1000>;
916 };
918 target-module@1e000 { /* 0x4a21e000, ap 95 0a.0 */
919 compatible = "ti,sysc";
920 status = "disabled";
921 #address-cells = <1>;
922 #size-cells = <1>;
923 ranges = <0x0 0x1e000 0x1000>;
924 };
926 target-module@20000 { /* 0x4a220000, ap 97 24.0 */
927 compatible = "ti,sysc";
928 status = "disabled";
929 #address-cells = <1>;
930 #size-cells = <1>;
931 ranges = <0x0 0x20000 0x1000>;
932 };
934 target-module@24000 { /* 0x4a224000, ap 99 44.0 */
935 compatible = "ti,sysc";
936 status = "disabled";
937 #address-cells = <1>;
938 #size-cells = <1>;
939 ranges = <0x0 0x24000 0x1000>;
940 };
942 target-module@26000 { /* 0x4a226000, ap 101 2c.0 */
943 compatible = "ti,sysc";
944 status = "disabled";
945 #address-cells = <1>;
946 #size-cells = <1>;
947 ranges = <0x0 0x26000 0x1000>;
948 };
950 target-module@2a000 { /* 0x4a22a000, ap 91 4c.0 */
951 compatible = "ti,sysc";
952 status = "disabled";
953 #address-cells = <1>;
954 #size-cells = <1>;
955 ranges = <0x0 0x2a000 0x1000>;
956 };
958 target-module@2c000 { /* 0x4a22c000, ap 109 6c.0 */
959 compatible = "ti,sysc";
960 status = "disabled";
961 #address-cells = <1>;
962 #size-cells = <1>;
963 ranges = <0x0 0x2c000 0x1000>;
964 };
966 target-module@2e000 { /* 0x4a22e000, ap 111 6e.0 */
967 compatible = "ti,sysc";
968 status = "disabled";
969 #address-cells = <1>;
970 #size-cells = <1>;
971 ranges = <0x0 0x2e000 0x1000>;
972 };
974 target-module@30000 { /* 0x4a230000, ap 113 70.0 */
975 compatible = "ti,sysc";
976 status = "disabled";
977 #address-cells = <1>;
978 #size-cells = <1>;
979 ranges = <0x0 0x30000 0x1000>;
980 };
982 target-module@32000 { /* 0x4a232000, ap 115 5a.0 */
983 compatible = "ti,sysc";
984 status = "disabled";
985 #address-cells = <1>;
986 #size-cells = <1>;
987 ranges = <0x0 0x32000 0x1000>;
988 };
990 target-module@34000 { /* 0x4a234000, ap 117 76.1 */
991 compatible = "ti,sysc";
992 status = "disabled";
993 #address-cells = <1>;
994 #size-cells = <1>;
995 ranges = <0x0 0x34000 0x1000>;
996 };
998 target-module@36000 { /* 0x4a236000, ap 119 62.0 */
999 compatible = "ti,sysc";
1000 status = "disabled";
1001 #address-cells = <1>;
1002 #size-cells = <1>;
1003 ranges = <0x0 0x36000 0x1000>;
1004 };
1005 };
1006 };
1008 &l4_per1 { /* 0x48000000 */
1009 compatible = "ti,dra7-l4-per1", "simple-bus";
1010 reg = <0x48000000 0x800>,
1011 <0x48000800 0x800>,
1012 <0x48001000 0x400>,
1013 <0x48001400 0x400>,
1014 <0x48001800 0x400>,
1015 <0x48001c00 0x400>;
1016 reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
1017 #address-cells = <1>;
1018 #size-cells = <1>;
1019 ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
1020 <0x00200000 0x48200000 0x200000>; /* segment 1 */
1022 segment@0 { /* 0x48000000 */
1023 compatible = "simple-bus";
1024 #address-cells = <1>;
1025 #size-cells = <1>;
1026 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
1027 <0x00001000 0x00001000 0x000400>, /* ap 1 */
1028 <0x00000800 0x00000800 0x000800>, /* ap 2 */
1029 <0x00020000 0x00020000 0x001000>, /* ap 3 */
1030 <0x00021000 0x00021000 0x001000>, /* ap 4 */
1031 <0x00032000 0x00032000 0x001000>, /* ap 5 */
1032 <0x00033000 0x00033000 0x001000>, /* ap 6 */
1033 <0x00034000 0x00034000 0x001000>, /* ap 7 */
1034 <0x00035000 0x00035000 0x001000>, /* ap 8 */
1035 <0x00036000 0x00036000 0x001000>, /* ap 9 */
1036 <0x00037000 0x00037000 0x001000>, /* ap 10 */
1037 <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
1038 <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
1039 <0x00055000 0x00055000 0x001000>, /* ap 13 */
1040 <0x00056000 0x00056000 0x001000>, /* ap 14 */
1041 <0x00057000 0x00057000 0x001000>, /* ap 15 */
1042 <0x00058000 0x00058000 0x001000>, /* ap 16 */
1043 <0x00059000 0x00059000 0x001000>, /* ap 17 */
1044 <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
1045 <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
1046 <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
1047 <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
1048 <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
1049 <0x00060000 0x00060000 0x001000>, /* ap 23 */
1050 <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
1051 <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
1052 <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
1053 <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
1054 <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
1055 <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
1056 <0x00070000 0x00070000 0x001000>, /* ap 30 */
1057 <0x00071000 0x00071000 0x001000>, /* ap 31 */
1058 <0x00072000 0x00072000 0x001000>, /* ap 32 */
1059 <0x00073000 0x00073000 0x001000>, /* ap 33 */
1060 <0x00061000 0x00061000 0x001000>, /* ap 34 */
1061 <0x00053000 0x00053000 0x001000>, /* ap 35 */
1062 <0x00054000 0x00054000 0x001000>, /* ap 36 */
1063 <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
1064 <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
1065 <0x00078000 0x00078000 0x001000>, /* ap 39 */
1066 <0x00079000 0x00079000 0x001000>, /* ap 40 */
1067 <0x00086000 0x00086000 0x001000>, /* ap 41 */
1068 <0x00087000 0x00087000 0x001000>, /* ap 42 */
1069 <0x00088000 0x00088000 0x001000>, /* ap 43 */
1070 <0x00089000 0x00089000 0x001000>, /* ap 44 */
1071 <0x00051000 0x00051000 0x001000>, /* ap 45 */
1072 <0x00052000 0x00052000 0x001000>, /* ap 46 */
1073 <0x00098000 0x00098000 0x001000>, /* ap 47 */
1074 <0x00099000 0x00099000 0x001000>, /* ap 48 */
1075 <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
1076 <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
1077 <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
1078 <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
1079 <0x00068000 0x00068000 0x001000>, /* ap 53 */
1080 <0x00069000 0x00069000 0x001000>, /* ap 54 */
1081 <0x00090000 0x00090000 0x002000>, /* ap 55 */
1082 <0x00092000 0x00092000 0x001000>, /* ap 56 */
1083 <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
1084 <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
1085 <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
1086 <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
1087 <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
1088 <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
1089 <0x00066000 0x00066000 0x001000>, /* ap 63 */
1090 <0x00067000 0x00067000 0x001000>, /* ap 64 */
1091 <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
1092 <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
1093 <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
1094 <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
1095 <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
1096 <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
1097 <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
1098 <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
1099 <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
1100 <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
1101 <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
1102 <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
1103 <0x00001400 0x00001400 0x000400>, /* ap 77 */
1104 <0x00001800 0x00001800 0x000400>, /* ap 78 */
1105 <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
1106 <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
1107 <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
1108 <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
1109 <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
1110 <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
1112 target-module@20000 { /* 0x48020000, ap 3 04.0 */
1113 compatible = "ti,sysc-omap2", "ti,sysc";
1114 reg = <0x20050 0x4>,
1115 <0x20054 0x4>,
1116 <0x20058 0x4>;
1117 reg-names = "rev", "sysc", "syss";
1118 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1119 SYSC_OMAP2_SOFTRESET |
1120 SYSC_OMAP2_AUTOIDLE)>;
1121 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1122 <SYSC_IDLE_NO>,
1123 <SYSC_IDLE_SMART>,
1124 <SYSC_IDLE_SMART_WKUP>;
1125 ti,syss-mask = <1>;
1126 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1127 clocks = <&l4per_clkctrl DRA7_L4PER_UART3_CLKCTRL 0>;
1128 clock-names = "fck";
1129 #address-cells = <1>;
1130 #size-cells = <1>;
1131 ranges = <0x0 0x20000 0x1000>;
1133 uart3: serial@0 {
1134 compatible = "ti,dra742-uart", "ti,omap4-uart";
1135 reg = <0x0 0x100>;
1136 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
1137 clock-frequency = <48000000>;
1138 status = "disabled";
1139 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>;
1140 dma-names = "tx", "rx";
1141 };
1142 };
1144 target-module@32000 { /* 0x48032000, ap 5 3e.0 */
1145 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1146 reg = <0x32000 0x4>,
1147 <0x32010 0x4>;
1148 reg-names = "rev", "sysc";
1149 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1150 SYSC_OMAP4_SOFTRESET)>;
1151 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1152 <SYSC_IDLE_NO>,
1153 <SYSC_IDLE_SMART>,
1154 <SYSC_IDLE_SMART_WKUP>;
1155 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1156 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 0>;
1157 clock-names = "fck";
1158 #address-cells = <1>;
1159 #size-cells = <1>;
1160 ranges = <0x0 0x32000 0x1000>;
1162 timer2: timer@0 {
1163 compatible = "ti,omap5430-timer";
1164 reg = <0x0 0x80>;
1165 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;
1166 clock-names = "fck", "timer_sys_ck";
1167 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1168 };
1169 };
1171 target-module@34000 { /* 0x48034000, ap 7 46.0 */
1172 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1173 reg = <0x34000 0x4>,
1174 <0x34010 0x4>;
1175 reg-names = "rev", "sysc";
1176 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1177 SYSC_OMAP4_SOFTRESET)>;
1178 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1179 <SYSC_IDLE_NO>,
1180 <SYSC_IDLE_SMART>,
1181 <SYSC_IDLE_SMART_WKUP>;
1182 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1183 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 0>;
1184 clock-names = "fck";
1185 #address-cells = <1>;
1186 #size-cells = <1>;
1187 ranges = <0x0 0x34000 0x1000>;
1189 timer3: timer@0 {
1190 compatible = "ti,omap5430-timer";
1191 reg = <0x0 0x80>;
1192 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;
1193 clock-names = "fck", "timer_sys_ck";
1194 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1195 };
1196 };
1198 target-module@36000 { /* 0x48036000, ap 9 4e.0 */
1199 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1200 reg = <0x36000 0x4>,
1201 <0x36010 0x4>;
1202 reg-names = "rev", "sysc";
1203 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1204 SYSC_OMAP4_SOFTRESET)>;
1205 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1206 <SYSC_IDLE_NO>,
1207 <SYSC_IDLE_SMART>,
1208 <SYSC_IDLE_SMART_WKUP>;
1209 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1210 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1211 clock-names = "fck";
1212 #address-cells = <1>;
1213 #size-cells = <1>;
1214 ranges = <0x0 0x36000 0x1000>;
1216 timer4: timer@0 {
1217 compatible = "ti,omap5430-timer";
1218 reg = <0x0 0x80>;
1219 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;
1220 clock-names = "fck", "timer_sys_ck";
1221 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1222 };
1223 };
1225 target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
1226 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1227 reg = <0x3e000 0x4>,
1228 <0x3e010 0x4>;
1229 reg-names = "rev", "sysc";
1230 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1231 SYSC_OMAP4_SOFTRESET)>;
1232 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1233 <SYSC_IDLE_NO>,
1234 <SYSC_IDLE_SMART>,
1235 <SYSC_IDLE_SMART_WKUP>;
1236 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1237 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 0>;
1238 clock-names = "fck";
1239 #address-cells = <1>;
1240 #size-cells = <1>;
1241 ranges = <0x0 0x3e000 0x1000>;
1243 timer9: timer@0 {
1244 compatible = "ti,omap5430-timer";
1245 reg = <0x0 0x80>;
1246 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;
1247 clock-names = "fck", "timer_sys_ck";
1248 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1249 };
1250 };
1252 gpio7_target: target-module@51000 { /* 0x48051000, ap 45 2e.0 */
1253 compatible = "ti,sysc-omap2", "ti,sysc";
1254 reg = <0x51000 0x4>,
1255 <0x51010 0x4>,
1256 <0x51114 0x4>;
1257 reg-names = "rev", "sysc", "syss";
1258 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1259 SYSC_OMAP2_SOFTRESET |
1260 SYSC_OMAP2_AUTOIDLE)>;
1261 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1262 <SYSC_IDLE_NO>,
1263 <SYSC_IDLE_SMART>,
1264 <SYSC_IDLE_SMART_WKUP>;
1265 ti,syss-mask = <1>;
1266 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1267 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 0>,
1268 <&l4per_clkctrl DRA7_L4PER_GPIO7_CLKCTRL 8>;
1269 clock-names = "fck", "dbclk";
1270 #address-cells = <1>;
1271 #size-cells = <1>;
1272 ranges = <0x0 0x51000 0x1000>;
1274 gpio7: gpio@0 {
1275 compatible = "ti,omap4-gpio";
1276 reg = <0x0 0x200>;
1277 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1278 gpio-controller;
1279 #gpio-cells = <2>;
1280 interrupt-controller;
1281 #interrupt-cells = <2>;
1282 };
1283 };
1285 target-module@53000 { /* 0x48053000, ap 35 36.0 */
1286 compatible = "ti,sysc-omap2", "ti,sysc";
1287 reg = <0x53000 0x4>,
1288 <0x53010 0x4>,
1289 <0x53114 0x4>;
1290 reg-names = "rev", "sysc", "syss";
1291 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1292 SYSC_OMAP2_SOFTRESET |
1293 SYSC_OMAP2_AUTOIDLE)>;
1294 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1295 <SYSC_IDLE_NO>,
1296 <SYSC_IDLE_SMART>,
1297 <SYSC_IDLE_SMART_WKUP>;
1298 ti,syss-mask = <1>;
1299 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1300 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 0>,
1301 <&l4per_clkctrl DRA7_L4PER_GPIO8_CLKCTRL 8>;
1302 clock-names = "fck", "dbclk";
1303 #address-cells = <1>;
1304 #size-cells = <1>;
1305 ranges = <0x0 0x53000 0x1000>;
1307 gpio8: gpio@0 {
1308 compatible = "ti,omap4-gpio";
1309 reg = <0x0 0x200>;
1310 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1311 gpio-controller;
1312 #gpio-cells = <2>;
1313 interrupt-controller;
1314 #interrupt-cells = <2>;
1315 };
1316 };
1318 target-module@55000 { /* 0x48055000, ap 13 0e.0 */
1319 compatible = "ti,sysc-omap2", "ti,sysc";
1320 reg = <0x55000 0x4>,
1321 <0x55010 0x4>,
1322 <0x55114 0x4>;
1323 reg-names = "rev", "sysc", "syss";
1324 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1325 SYSC_OMAP2_SOFTRESET |
1326 SYSC_OMAP2_AUTOIDLE)>;
1327 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1328 <SYSC_IDLE_NO>,
1329 <SYSC_IDLE_SMART>,
1330 <SYSC_IDLE_SMART_WKUP>;
1331 ti,syss-mask = <1>;
1332 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1333 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 0>,
1334 <&l4per_clkctrl DRA7_L4PER_GPIO2_CLKCTRL 8>;
1335 clock-names = "fck", "dbclk";
1336 #address-cells = <1>;
1337 #size-cells = <1>;
1338 ranges = <0x0 0x55000 0x1000>;
1340 gpio2: gpio@0 {
1341 compatible = "ti,omap4-gpio";
1342 reg = <0x0 0x200>;
1343 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1344 gpio-controller;
1345 #gpio-cells = <2>;
1346 interrupt-controller;
1347 #interrupt-cells = <2>;
1348 };
1349 };
1351 target-module@57000 { /* 0x48057000, ap 15 06.0 */
1352 compatible = "ti,sysc-omap2", "ti,sysc";
1353 reg = <0x57000 0x4>,
1354 <0x57010 0x4>,
1355 <0x57114 0x4>;
1356 reg-names = "rev", "sysc", "syss";
1357 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1358 SYSC_OMAP2_SOFTRESET |
1359 SYSC_OMAP2_AUTOIDLE)>;
1360 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1361 <SYSC_IDLE_NO>,
1362 <SYSC_IDLE_SMART>,
1363 <SYSC_IDLE_SMART_WKUP>;
1364 ti,syss-mask = <1>;
1365 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1366 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 0>,
1367 <&l4per_clkctrl DRA7_L4PER_GPIO3_CLKCTRL 8>;
1368 clock-names = "fck", "dbclk";
1369 #address-cells = <1>;
1370 #size-cells = <1>;
1371 ranges = <0x0 0x57000 0x1000>;
1373 gpio3: gpio@0 {
1374 compatible = "ti,omap4-gpio";
1375 reg = <0x0 0x200>;
1376 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1377 gpio-controller;
1378 #gpio-cells = <2>;
1379 interrupt-controller;
1380 #interrupt-cells = <2>;
1381 };
1382 };
1384 target-module@59000 { /* 0x48059000, ap 17 16.0 */
1385 compatible = "ti,sysc-omap2", "ti,sysc";
1386 reg = <0x59000 0x4>,
1387 <0x59010 0x4>,
1388 <0x59114 0x4>;
1389 reg-names = "rev", "sysc", "syss";
1390 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1391 SYSC_OMAP2_SOFTRESET |
1392 SYSC_OMAP2_AUTOIDLE)>;
1393 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1394 <SYSC_IDLE_NO>,
1395 <SYSC_IDLE_SMART>,
1396 <SYSC_IDLE_SMART_WKUP>;
1397 ti,syss-mask = <1>;
1398 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1399 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 0>,
1400 <&l4per_clkctrl DRA7_L4PER_GPIO4_CLKCTRL 8>;
1401 clock-names = "fck", "dbclk";
1402 #address-cells = <1>;
1403 #size-cells = <1>;
1404 ranges = <0x0 0x59000 0x1000>;
1406 gpio4: gpio@0 {
1407 compatible = "ti,omap4-gpio";
1408 reg = <0x0 0x200>;
1409 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1410 gpio-controller;
1411 #gpio-cells = <2>;
1412 interrupt-controller;
1413 #interrupt-cells = <2>;
1414 };
1415 };
1417 target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
1418 compatible = "ti,sysc-omap2", "ti,sysc";
1419 reg = <0x5b000 0x4>,
1420 <0x5b010 0x4>,
1421 <0x5b114 0x4>;
1422 reg-names = "rev", "sysc", "syss";
1423 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1424 SYSC_OMAP2_SOFTRESET |
1425 SYSC_OMAP2_AUTOIDLE)>;
1426 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1427 <SYSC_IDLE_NO>,
1428 <SYSC_IDLE_SMART>,
1429 <SYSC_IDLE_SMART_WKUP>;
1430 ti,syss-mask = <1>;
1431 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1432 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 0>,
1433 <&l4per_clkctrl DRA7_L4PER_GPIO5_CLKCTRL 8>;
1434 clock-names = "fck", "dbclk";
1435 #address-cells = <1>;
1436 #size-cells = <1>;
1437 ranges = <0x0 0x5b000 0x1000>;
1439 gpio5: gpio@0 {
1440 compatible = "ti,omap4-gpio";
1441 reg = <0x0 0x200>;
1442 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1443 gpio-controller;
1444 #gpio-cells = <2>;
1445 interrupt-controller;
1446 #interrupt-cells = <2>;
1447 };
1448 };
1450 target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
1451 compatible = "ti,sysc-omap2", "ti,sysc";
1452 reg = <0x5d000 0x4>,
1453 <0x5d010 0x4>,
1454 <0x5d114 0x4>;
1455 reg-names = "rev", "sysc", "syss";
1456 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1457 SYSC_OMAP2_SOFTRESET |
1458 SYSC_OMAP2_AUTOIDLE)>;
1459 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1460 <SYSC_IDLE_NO>,
1461 <SYSC_IDLE_SMART>,
1462 <SYSC_IDLE_SMART_WKUP>;
1463 ti,syss-mask = <1>;
1464 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1465 clocks = <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 0>,
1466 <&l4per_clkctrl DRA7_L4PER_GPIO6_CLKCTRL 8>;
1467 clock-names = "fck", "dbclk";
1468 #address-cells = <1>;
1469 #size-cells = <1>;
1470 ranges = <0x0 0x5d000 0x1000>;
1472 gpio6: gpio@0 {
1473 compatible = "ti,omap4-gpio";
1474 reg = <0x0 0x200>;
1475 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1476 gpio-controller;
1477 #gpio-cells = <2>;
1478 interrupt-controller;
1479 #interrupt-cells = <2>;
1480 };
1481 };
1483 target-module@60000 { /* 0x48060000, ap 23 32.0 */
1484 compatible = "ti,sysc-omap2", "ti,sysc";
1485 reg = <0x60000 0x8>,
1486 <0x60010 0x8>,
1487 <0x60090 0x8>;
1488 reg-names = "rev", "sysc", "syss";
1489 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1490 SYSC_OMAP2_ENAWAKEUP |
1491 SYSC_OMAP2_SOFTRESET |
1492 SYSC_OMAP2_AUTOIDLE)>;
1493 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1494 <SYSC_IDLE_NO>,
1495 <SYSC_IDLE_SMART>,
1496 <SYSC_IDLE_SMART_WKUP>;
1497 ti,syss-mask = <1>;
1498 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1499 clocks = <&l4per_clkctrl DRA7_L4PER_I2C3_CLKCTRL 0>;
1500 clock-names = "fck";
1501 #address-cells = <1>;
1502 #size-cells = <1>;
1503 ranges = <0x0 0x60000 0x1000>;
1505 i2c3: i2c@0 {
1506 compatible = "ti,omap4-i2c";
1507 reg = <0x0 0x100>;
1508 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1509 #address-cells = <1>;
1510 #size-cells = <0>;
1511 status = "disabled";
1512 };
1513 };
1515 target-module@66000 { /* 0x48066000, ap 63 14.0 */
1516 compatible = "ti,sysc-omap2", "ti,sysc";
1517 reg = <0x66050 0x4>,
1518 <0x66054 0x4>,
1519 <0x66058 0x4>;
1520 reg-names = "rev", "sysc", "syss";
1521 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1522 SYSC_OMAP2_SOFTRESET |
1523 SYSC_OMAP2_AUTOIDLE)>;
1524 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1525 <SYSC_IDLE_NO>,
1526 <SYSC_IDLE_SMART>,
1527 <SYSC_IDLE_SMART_WKUP>;
1528 ti,syss-mask = <1>;
1529 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1530 clocks = <&l4per_clkctrl DRA7_L4PER_UART5_CLKCTRL 0>;
1531 clock-names = "fck";
1532 #address-cells = <1>;
1533 #size-cells = <1>;
1534 ranges = <0x0 0x66000 0x1000>;
1536 uart5: serial@0 {
1537 compatible = "ti,dra742-uart", "ti,omap4-uart";
1538 reg = <0x0 0x100>;
1539 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1540 clock-frequency = <48000000>;
1541 status = "disabled";
1542 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>;
1543 dma-names = "tx", "rx";
1544 };
1545 };
1547 target-module@68000 { /* 0x48068000, ap 53 1c.0 */
1548 compatible = "ti,sysc-omap2", "ti,sysc";
1549 reg = <0x68050 0x4>,
1550 <0x68054 0x4>,
1551 <0x68058 0x4>;
1552 reg-names = "rev", "sysc", "syss";
1553 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1554 SYSC_OMAP2_SOFTRESET |
1555 SYSC_OMAP2_AUTOIDLE)>;
1556 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1557 <SYSC_IDLE_NO>,
1558 <SYSC_IDLE_SMART>,
1559 <SYSC_IDLE_SMART_WKUP>;
1560 ti,syss-mask = <1>;
1561 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1562 clocks = <&ipu_clkctrl DRA7_IPU_UART6_CLKCTRL 0>;
1563 clock-names = "fck";
1564 #address-cells = <1>;
1565 #size-cells = <1>;
1566 ranges = <0x0 0x68000 0x1000>;
1568 uart6: serial@0 {
1569 compatible = "ti,dra742-uart", "ti,omap4-uart";
1570 reg = <0x0 0x100>;
1571 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1572 clock-frequency = <48000000>;
1573 status = "disabled";
1574 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>;
1575 dma-names = "tx", "rx";
1576 };
1577 };
1579 target-module@6a000 { /* 0x4806a000, ap 24 24.0 */
1580 compatible = "ti,sysc-omap2", "ti,sysc";
1581 reg = <0x6a050 0x4>,
1582 <0x6a054 0x4>,
1583 <0x6a058 0x4>;
1584 reg-names = "rev", "sysc", "syss";
1585 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1586 SYSC_OMAP2_SOFTRESET |
1587 SYSC_OMAP2_AUTOIDLE)>;
1588 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1589 <SYSC_IDLE_NO>,
1590 <SYSC_IDLE_SMART>,
1591 <SYSC_IDLE_SMART_WKUP>;
1592 ti,syss-mask = <1>;
1593 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1594 clocks = <&l4per_clkctrl DRA7_L4PER_UART1_CLKCTRL 0>;
1595 clock-names = "fck";
1596 #address-cells = <1>;
1597 #size-cells = <1>;
1598 ranges = <0x0 0x6a000 0x1000>;
1600 uart1: serial@0 {
1601 compatible = "ti,dra742-uart", "ti,omap4-uart";
1602 reg = <0x0 0x100>;
1603 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
1604 clock-frequency = <48000000>;
1605 status = "disabled";
1606 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>;
1607 dma-names = "tx", "rx";
1608 };
1609 };
1611 target-module@6c000 { /* 0x4806c000, ap 26 2c.0 */
1612 compatible = "ti,sysc-omap2", "ti,sysc";
1613 reg = <0x6c050 0x4>,
1614 <0x6c054 0x4>,
1615 <0x6c058 0x4>;
1616 reg-names = "rev", "sysc", "syss";
1617 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1618 SYSC_OMAP2_SOFTRESET |
1619 SYSC_OMAP2_AUTOIDLE)>;
1620 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1621 <SYSC_IDLE_NO>,
1622 <SYSC_IDLE_SMART>,
1623 <SYSC_IDLE_SMART_WKUP>;
1624 ti,syss-mask = <1>;
1625 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1626 clocks = <&l4per_clkctrl DRA7_L4PER_UART2_CLKCTRL 0>;
1627 clock-names = "fck";
1628 #address-cells = <1>;
1629 #size-cells = <1>;
1630 ranges = <0x0 0x6c000 0x1000>;
1632 uart2: serial@0 {
1633 compatible = "ti,dra742-uart", "ti,omap4-uart";
1634 reg = <0x0 0x100>;
1635 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1636 clock-frequency = <48000000>;
1637 status = "disabled";
1638 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>;
1639 dma-names = "tx", "rx";
1640 };
1641 };
1643 target-module@6e000 { /* 0x4806e000, ap 28 0c.1 */
1644 compatible = "ti,sysc-omap2", "ti,sysc";
1645 reg = <0x6e050 0x4>,
1646 <0x6e054 0x4>,
1647 <0x6e058 0x4>;
1648 reg-names = "rev", "sysc", "syss";
1649 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
1650 SYSC_OMAP2_SOFTRESET |
1651 SYSC_OMAP2_AUTOIDLE)>;
1652 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1653 <SYSC_IDLE_NO>,
1654 <SYSC_IDLE_SMART>,
1655 <SYSC_IDLE_SMART_WKUP>;
1656 ti,syss-mask = <1>;
1657 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1658 clocks = <&l4per_clkctrl DRA7_L4PER_UART4_CLKCTRL 0>;
1659 clock-names = "fck";
1660 #address-cells = <1>;
1661 #size-cells = <1>;
1662 ranges = <0x0 0x6e000 0x1000>;
1664 uart4: serial@0 {
1665 compatible = "ti,dra742-uart", "ti,omap4-uart";
1666 reg = <0x0 0x100>;
1667 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
1668 clock-frequency = <48000000>;
1669 status = "disabled";
1670 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>;
1671 dma-names = "tx", "rx";
1672 };
1673 };
1675 target-module@70000 { /* 0x48070000, ap 30 22.0 */
1676 compatible = "ti,sysc-omap2", "ti,sysc";
1677 reg = <0x70000 0x8>,
1678 <0x70010 0x8>,
1679 <0x70090 0x8>;
1680 reg-names = "rev", "sysc", "syss";
1681 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1682 SYSC_OMAP2_ENAWAKEUP |
1683 SYSC_OMAP2_SOFTRESET |
1684 SYSC_OMAP2_AUTOIDLE)>;
1685 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1686 <SYSC_IDLE_NO>,
1687 <SYSC_IDLE_SMART>,
1688 <SYSC_IDLE_SMART_WKUP>;
1689 ti,syss-mask = <1>;
1690 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1691 clocks = <&l4per_clkctrl DRA7_L4PER_I2C1_CLKCTRL 0>;
1692 clock-names = "fck";
1693 #address-cells = <1>;
1694 #size-cells = <1>;
1695 ranges = <0x0 0x70000 0x1000>;
1697 i2c1: i2c@0 {
1698 compatible = "ti,omap4-i2c";
1699 reg = <0x0 0x100>;
1700 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1701 #address-cells = <1>;
1702 #size-cells = <0>;
1703 status = "disabled";
1704 };
1705 };
1707 target-module@72000 { /* 0x48072000, ap 32 2a.0 */
1708 compatible = "ti,sysc-omap2", "ti,sysc";
1709 reg = <0x72000 0x8>,
1710 <0x72010 0x8>,
1711 <0x72090 0x8>;
1712 reg-names = "rev", "sysc", "syss";
1713 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1714 SYSC_OMAP2_ENAWAKEUP |
1715 SYSC_OMAP2_SOFTRESET |
1716 SYSC_OMAP2_AUTOIDLE)>;
1717 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1718 <SYSC_IDLE_NO>,
1719 <SYSC_IDLE_SMART>,
1720 <SYSC_IDLE_SMART_WKUP>;
1721 ti,syss-mask = <1>;
1722 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1723 clocks = <&l4per_clkctrl DRA7_L4PER_I2C2_CLKCTRL 0>;
1724 clock-names = "fck";
1725 #address-cells = <1>;
1726 #size-cells = <1>;
1727 ranges = <0x0 0x72000 0x1000>;
1729 i2c2: i2c@0 {
1730 compatible = "ti,omap4-i2c";
1731 reg = <0x0 0x100>;
1732 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1733 #address-cells = <1>;
1734 #size-cells = <0>;
1735 status = "disabled";
1736 };
1737 };
1739 target-module@78000 { /* 0x48078000, ap 39 0a.0 */
1740 compatible = "ti,sysc-omap2", "ti,sysc";
1741 reg = <0x78000 0x4>,
1742 <0x78010 0x4>,
1743 <0x78014 0x4>;
1744 reg-names = "rev", "sysc", "syss";
1745 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1746 SYSC_OMAP2_SOFTRESET |
1747 SYSC_OMAP2_AUTOIDLE)>;
1748 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1749 <SYSC_IDLE_NO>,
1750 <SYSC_IDLE_SMART>,
1751 <SYSC_IDLE_SMART_WKUP>;
1752 ti,syss-mask = <1>;
1753 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1754 clocks = <&l4per_clkctrl DRA7_L4PER_ELM_CLKCTRL 0>;
1755 clock-names = "fck";
1756 #address-cells = <1>;
1757 #size-cells = <1>;
1758 ranges = <0x0 0x78000 0x1000>;
1760 elm: elm@0 {
1761 compatible = "ti,am3352-elm";
1762 reg = <0x0 0xfc0>; /* device IO registers */
1763 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1764 status = "disabled";
1765 };
1766 };
1768 target-module@7a000 { /* 0x4807a000, ap 81 3a.0 */
1769 compatible = "ti,sysc-omap2", "ti,sysc";
1770 reg = <0x7a000 0x8>,
1771 <0x7a010 0x8>,
1772 <0x7a090 0x8>;
1773 reg-names = "rev", "sysc", "syss";
1774 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1775 SYSC_OMAP2_ENAWAKEUP |
1776 SYSC_OMAP2_SOFTRESET |
1777 SYSC_OMAP2_AUTOIDLE)>;
1778 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1779 <SYSC_IDLE_NO>,
1780 <SYSC_IDLE_SMART>,
1781 <SYSC_IDLE_SMART_WKUP>;
1782 ti,syss-mask = <1>;
1783 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1784 clocks = <&l4per_clkctrl DRA7_L4PER_I2C4_CLKCTRL 0>;
1785 clock-names = "fck";
1786 #address-cells = <1>;
1787 #size-cells = <1>;
1788 ranges = <0x0 0x7a000 0x1000>;
1790 i2c4: i2c@0 {
1791 compatible = "ti,omap4-i2c";
1792 reg = <0x0 0x100>;
1793 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1794 #address-cells = <1>;
1795 #size-cells = <0>;
1796 status = "disabled";
1797 };
1798 };
1800 target-module@7c000 { /* 0x4807c000, ap 83 4a.0 */
1801 compatible = "ti,sysc-omap2", "ti,sysc";
1802 reg = <0x7c000 0x8>,
1803 <0x7c010 0x8>,
1804 <0x7c090 0x8>;
1805 reg-names = "rev", "sysc", "syss";
1806 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
1807 SYSC_OMAP2_ENAWAKEUP |
1808 SYSC_OMAP2_SOFTRESET |
1809 SYSC_OMAP2_AUTOIDLE)>;
1810 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1811 <SYSC_IDLE_NO>,
1812 <SYSC_IDLE_SMART>,
1813 <SYSC_IDLE_SMART_WKUP>;
1814 ti,syss-mask = <1>;
1815 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
1816 clocks = <&ipu_clkctrl DRA7_IPU_I2C5_CLKCTRL 0>;
1817 clock-names = "fck";
1818 #address-cells = <1>;
1819 #size-cells = <1>;
1820 ranges = <0x0 0x7c000 0x1000>;
1822 i2c5: i2c@0 {
1823 compatible = "ti,omap4-i2c";
1824 reg = <0x0 0x100>;
1825 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1826 #address-cells = <1>;
1827 #size-cells = <0>;
1828 status = "disabled";
1829 };
1830 };
1832 target-module@86000 { /* 0x48086000, ap 41 5e.0 */
1833 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1834 reg = <0x86000 0x4>,
1835 <0x86010 0x4>;
1836 reg-names = "rev", "sysc";
1837 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1838 SYSC_OMAP4_SOFTRESET)>;
1839 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1840 <SYSC_IDLE_NO>,
1841 <SYSC_IDLE_SMART>,
1842 <SYSC_IDLE_SMART_WKUP>;
1843 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1844 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 0>;
1845 clock-names = "fck";
1846 #address-cells = <1>;
1847 #size-cells = <1>;
1848 ranges = <0x0 0x86000 0x1000>;
1850 timer10: timer@0 {
1851 compatible = "ti,omap5430-timer";
1852 reg = <0x0 0x80>;
1853 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;
1854 clock-names = "fck", "timer_sys_ck";
1855 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1856 };
1857 };
1859 target-module@88000 { /* 0x48088000, ap 43 66.0 */
1860 compatible = "ti,sysc-omap4-timer", "ti,sysc";
1861 reg = <0x88000 0x4>,
1862 <0x88010 0x4>;
1863 reg-names = "rev", "sysc";
1864 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1865 SYSC_OMAP4_SOFTRESET)>;
1866 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1867 <SYSC_IDLE_NO>,
1868 <SYSC_IDLE_SMART>,
1869 <SYSC_IDLE_SMART_WKUP>;
1870 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1871 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 0>;
1872 clock-names = "fck";
1873 #address-cells = <1>;
1874 #size-cells = <1>;
1875 ranges = <0x0 0x88000 0x1000>;
1877 timer11: timer@0 {
1878 compatible = "ti,omap5430-timer";
1879 reg = <0x0 0x80>;
1880 clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;
1881 clock-names = "fck", "timer_sys_ck";
1882 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1883 };
1884 };
1886 target-module@90000 { /* 0x48090000, ap 55 12.0 */
1887 compatible = "ti,sysc-omap2", "ti,sysc";
1888 reg = <0x91fe0 0x4>,
1889 <0x91fe4 0x4>;
1890 reg-names = "rev", "sysc";
1891 ti,sysc-mask = <SYSC_OMAP2_AUTOIDLE>;
1892 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1893 <SYSC_IDLE_NO>;
1894 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1895 clocks = <&l4sec_clkctrl DRA7_L4SEC_RNG_CLKCTRL 0>;
1896 clock-names = "fck";
1897 #address-cells = <1>;
1898 #size-cells = <1>;
1899 ranges = <0x0 0x90000 0x2000>;
1901 rng: rng@0 {
1902 compatible = "ti,omap4-rng";
1903 reg = <0x0 0x2000>;
1904 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1905 clocks = <&l3_iclk_div>;
1906 clock-names = "fck";
1907 };
1908 };
1910 target-module@98000 { /* 0x48098000, ap 47 08.0 */
1911 compatible = "ti,sysc-omap4", "ti,sysc";
1912 reg = <0x98000 0x4>,
1913 <0x98010 0x4>;
1914 reg-names = "rev", "sysc";
1915 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1916 SYSC_OMAP4_SOFTRESET)>;
1917 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1918 <SYSC_IDLE_NO>,
1919 <SYSC_IDLE_SMART>,
1920 <SYSC_IDLE_SMART_WKUP>;
1921 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1922 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI1_CLKCTRL 0>;
1923 clock-names = "fck";
1924 #address-cells = <1>;
1925 #size-cells = <1>;
1926 ranges = <0x0 0x98000 0x1000>;
1928 mcspi1: spi@0 {
1929 compatible = "ti,omap4-mcspi";
1930 reg = <0x0 0x200>;
1931 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1932 #address-cells = <1>;
1933 #size-cells = <0>;
1934 ti,spi-num-cs = <4>;
1935 dmas = <&sdma_xbar 35>,
1936 <&sdma_xbar 36>,
1937 <&sdma_xbar 37>,
1938 <&sdma_xbar 38>,
1939 <&sdma_xbar 39>,
1940 <&sdma_xbar 40>,
1941 <&sdma_xbar 41>,
1942 <&sdma_xbar 42>;
1943 dma-names = "tx0", "rx0", "tx1", "rx1",
1944 "tx2", "rx2", "tx3", "rx3";
1945 status = "disabled";
1946 };
1947 };
1949 target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
1950 compatible = "ti,sysc-omap4", "ti,sysc";
1951 reg = <0x9a000 0x4>,
1952 <0x9a010 0x4>;
1953 reg-names = "rev", "sysc";
1954 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1955 SYSC_OMAP4_SOFTRESET)>;
1956 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1957 <SYSC_IDLE_NO>,
1958 <SYSC_IDLE_SMART>,
1959 <SYSC_IDLE_SMART_WKUP>;
1960 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1961 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI2_CLKCTRL 0>;
1962 clock-names = "fck";
1963 #address-cells = <1>;
1964 #size-cells = <1>;
1965 ranges = <0x0 0x9a000 0x1000>;
1967 mcspi2: spi@0 {
1968 compatible = "ti,omap4-mcspi";
1969 reg = <0x0 0x200>;
1970 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1971 #address-cells = <1>;
1972 #size-cells = <0>;
1973 ti,spi-num-cs = <2>;
1974 dmas = <&sdma_xbar 43>,
1975 <&sdma_xbar 44>,
1976 <&sdma_xbar 45>,
1977 <&sdma_xbar 46>;
1978 dma-names = "tx0", "rx0", "tx1", "rx1";
1979 status = "disabled";
1980 };
1981 };
1983 target-module@9c000 { /* 0x4809c000, ap 51 38.0 */
1984 compatible = "ti,sysc-omap4", "ti,sysc";
1985 reg = <0x9c000 0x4>,
1986 <0x9c010 0x4>;
1987 reg-names = "rev", "sysc";
1988 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
1989 SYSC_OMAP4_SOFTRESET)>;
1990 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1991 <SYSC_IDLE_NO>,
1992 <SYSC_IDLE_SMART>,
1993 <SYSC_IDLE_SMART_WKUP>;
1994 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1995 <SYSC_IDLE_NO>,
1996 <SYSC_IDLE_SMART>,
1997 <SYSC_IDLE_SMART_WKUP>;
1998 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
1999 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC1_CLKCTRL 0>;
2000 clock-names = "fck";
2001 #address-cells = <1>;
2002 #size-cells = <1>;
2003 ranges = <0x0 0x9c000 0x1000>;
2005 mmc1: mmc@0 {
2006 compatible = "ti,dra7-sdhci";
2007 reg = <0x0 0x400>;
2008 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
2009 status = "disabled";
2010 pbias-supply = <&pbias_mmc_reg>;
2011 max-frequency = <192000000>;
2012 mmc-ddr-1_8v;
2013 mmc-ddr-3_3v;
2014 };
2015 };
2017 target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
2018 compatible = "ti,sysc";
2019 status = "disabled";
2020 #address-cells = <1>;
2021 #size-cells = <1>;
2022 ranges = <0x0 0xa2000 0x1000>;
2023 };
2025 target-module@a4000 { /* 0x480a4000, ap 57 42.0 */
2026 compatible = "ti,sysc";
2027 status = "disabled";
2028 #address-cells = <1>;
2029 #size-cells = <1>;
2030 ranges = <0x00000000 0x000a4000 0x00001000>,
2031 <0x00001000 0x000a5000 0x00001000>;
2032 };
2034 des_target: target-module@a5000 { /* 0x480a5000 */
2035 compatible = "ti,sysc-omap2", "ti,sysc";
2036 reg = <0xa5030 0x4>,
2037 <0xa5034 0x4>,
2038 <0xa5038 0x4>;
2039 reg-names = "rev", "sysc", "syss";
2040 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2041 SYSC_OMAP2_AUTOIDLE)>;
2042 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2043 <SYSC_IDLE_NO>,
2044 <SYSC_IDLE_SMART>,
2045 <SYSC_IDLE_SMART_WKUP>;
2046 ti,syss-mask = <1>;
2047 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
2048 clocks = <&l4sec_clkctrl DRA7_L4SEC_DES_CLKCTRL 0>;
2049 clock-names = "fck";
2050 #address-cells = <1>;
2051 #size-cells = <1>;
2052 ranges = <0 0xa5000 0x00001000>;
2054 des: des@0 {
2055 compatible = "ti,omap4-des";
2056 reg = <0 0xa0>;
2057 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2058 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
2059 dma-names = "tx", "rx";
2060 clocks = <&l3_iclk_div>;
2061 clock-names = "fck";
2062 };
2063 };
2065 target-module@a8000 { /* 0x480a8000, ap 59 1a.0 */
2066 compatible = "ti,sysc";
2067 status = "disabled";
2068 #address-cells = <1>;
2069 #size-cells = <1>;
2070 ranges = <0x0 0xa8000 0x4000>;
2071 };
2073 target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
2074 compatible = "ti,sysc-omap4", "ti,sysc";
2075 reg = <0xad000 0x4>,
2076 <0xad010 0x4>;
2077 reg-names = "rev", "sysc";
2078 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2079 SYSC_OMAP4_SOFTRESET)>;
2080 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2081 <SYSC_IDLE_NO>,
2082 <SYSC_IDLE_SMART>,
2083 <SYSC_IDLE_SMART_WKUP>;
2084 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2085 <SYSC_IDLE_NO>,
2086 <SYSC_IDLE_SMART>,
2087 <SYSC_IDLE_SMART_WKUP>;
2088 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2089 clocks = <&l4per_clkctrl DRA7_L4PER_MMC3_CLKCTRL 0>;
2090 clock-names = "fck";
2091 #address-cells = <1>;
2092 #size-cells = <1>;
2093 ranges = <0x0 0xad000 0x1000>;
2095 mmc3: mmc@0 {
2096 compatible = "ti,dra7-sdhci";
2097 reg = <0x0 0x400>;
2098 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
2099 status = "disabled";
2100 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */
2101 max-frequency = <64000000>;
2102 /* SDMA is not supported */
2103 sdhci-caps-mask = <0x0 0x400000>;
2104 };
2105 };
2107 target-module@b2000 { /* 0x480b2000, ap 37 52.0 */
2108 compatible = "ti,sysc-omap2", "ti,sysc";
2109 reg = <0xb2000 0x4>,
2110 <0xb2014 0x4>,
2111 <0xb2018 0x4>;
2112 reg-names = "rev", "sysc", "syss";
2113 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
2114 SYSC_OMAP2_AUTOIDLE)>;
2115 ti,syss-mask = <1>;
2116 ti,no-reset-on-init;
2117 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2118 clocks = <&l4per_clkctrl DRA7_L4PER_HDQ1W_CLKCTRL 0>;
2119 clock-names = "fck";
2120 #address-cells = <1>;
2121 #size-cells = <1>;
2122 ranges = <0x0 0xb2000 0x1000>;
2124 hdqw1w: 1w@0 {
2125 compatible = "ti,omap3-1w";
2126 reg = <0x0 0x1000>;
2127 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2128 };
2129 };
2131 target-module@b4000 { /* 0x480b4000, ap 65 40.0 */
2132 compatible = "ti,sysc-omap4", "ti,sysc";
2133 reg = <0xb4000 0x4>,
2134 <0xb4010 0x4>;
2135 reg-names = "rev", "sysc";
2136 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2137 SYSC_OMAP4_SOFTRESET)>;
2138 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2139 <SYSC_IDLE_NO>,
2140 <SYSC_IDLE_SMART>,
2141 <SYSC_IDLE_SMART_WKUP>;
2142 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2143 <SYSC_IDLE_NO>,
2144 <SYSC_IDLE_SMART>,
2145 <SYSC_IDLE_SMART_WKUP>;
2146 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
2147 clocks = <&l3init_clkctrl DRA7_L3INIT_MMC2_CLKCTRL 0>;
2148 clock-names = "fck";
2149 #address-cells = <1>;
2150 #size-cells = <1>;
2151 ranges = <0x0 0xb4000 0x1000>;
2153 mmc2: mmc@0 {
2154 compatible = "ti,dra7-sdhci";
2155 reg = <0x0 0x400>;
2156 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
2157 status = "disabled";
2158 max-frequency = <192000000>;
2159 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */
2160 sdhci-caps-mask = <0x7 0x0>;
2161 mmc-hs200-1_8v;
2162 mmc-ddr-1_8v;
2163 mmc-ddr-3_3v;
2164 };
2165 };
2167 target-module@b8000 { /* 0x480b8000, ap 67 48.0 */
2168 compatible = "ti,sysc-omap4", "ti,sysc";
2169 reg = <0xb8000 0x4>,
2170 <0xb8010 0x4>;
2171 reg-names = "rev", "sysc";
2172 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2173 SYSC_OMAP4_SOFTRESET)>;
2174 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2175 <SYSC_IDLE_NO>,
2176 <SYSC_IDLE_SMART>,
2177 <SYSC_IDLE_SMART_WKUP>;
2178 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2179 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI3_CLKCTRL 0>;
2180 clock-names = "fck";
2181 #address-cells = <1>;
2182 #size-cells = <1>;
2183 ranges = <0x0 0xb8000 0x1000>;
2185 mcspi3: spi@0 {
2186 compatible = "ti,omap4-mcspi";
2187 reg = <0x0 0x200>;
2188 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
2189 #address-cells = <1>;
2190 #size-cells = <0>;
2191 ti,spi-num-cs = <2>;
2192 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>;
2193 dma-names = "tx0", "rx0";
2194 status = "disabled";
2195 };
2196 };
2198 target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
2199 compatible = "ti,sysc-omap4", "ti,sysc";
2200 reg = <0xba000 0x4>,
2201 <0xba010 0x4>;
2202 reg-names = "rev", "sysc";
2203 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2204 SYSC_OMAP4_SOFTRESET)>;
2205 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2206 <SYSC_IDLE_NO>,
2207 <SYSC_IDLE_SMART>,
2208 <SYSC_IDLE_SMART_WKUP>;
2209 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2210 clocks = <&l4per_clkctrl DRA7_L4PER_MCSPI4_CLKCTRL 0>;
2211 clock-names = "fck";
2212 #address-cells = <1>;
2213 #size-cells = <1>;
2214 ranges = <0x0 0xba000 0x1000>;
2216 mcspi4: spi@0 {
2217 compatible = "ti,omap4-mcspi";
2218 reg = <0x0 0x200>;
2219 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2220 #address-cells = <1>;
2221 #size-cells = <0>;
2222 ti,spi-num-cs = <1>;
2223 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>;
2224 dma-names = "tx0", "rx0";
2225 status = "disabled";
2226 };
2227 };
2229 target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
2230 compatible = "ti,sysc-omap4", "ti,sysc";
2231 reg = <0xd1000 0x4>,
2232 <0xd1010 0x4>;
2233 reg-names = "rev", "sysc";
2234 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
2235 SYSC_OMAP4_SOFTRESET)>;
2236 ti,sysc-midle = <SYSC_IDLE_FORCE>,
2237 <SYSC_IDLE_NO>,
2238 <SYSC_IDLE_SMART>,
2239 <SYSC_IDLE_SMART_WKUP>;
2240 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2241 <SYSC_IDLE_NO>,
2242 <SYSC_IDLE_SMART>,
2243 <SYSC_IDLE_SMART_WKUP>;
2244 /* Domains (P, C): l4per_pwrdm, l4per_clkdm */
2245 clocks = <&l4per_clkctrl DRA7_L4PER_MMC4_CLKCTRL 0>;
2246 clock-names = "fck";
2247 #address-cells = <1>;
2248 #size-cells = <1>;
2249 ranges = <0x0 0xd1000 0x1000>;
2251 mmc4: mmc@0 {
2252 compatible = "ti,dra7-sdhci";
2253 reg = <0x0 0x400>;
2254 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
2255 status = "disabled";
2256 max-frequency = <192000000>;
2257 /* SDMA is not supported */
2258 sdhci-caps-mask = <0x0 0x400000>;
2259 };
2260 };
2262 target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
2263 compatible = "ti,sysc";
2264 status = "disabled";
2265 #address-cells = <1>;
2266 #size-cells = <1>;
2267 ranges = <0x0 0xd5000 0x1000>;
2268 };
2269 };
2271 segment@200000 { /* 0x48200000 */
2272 compatible = "simple-bus";
2273 #address-cells = <1>;
2274 #size-cells = <1>;
2275 };
2276 };
2278 &l4_per2 { /* 0x48400000 */
2279 compatible = "ti,dra7-l4-per2", "simple-bus";
2280 reg = <0x48400000 0x800>,
2281 <0x48400800 0x800>,
2282 <0x48401000 0x400>,
2283 <0x48401400 0x400>,
2284 <0x48401800 0x400>;
2285 reg-names = "ap", "la", "ia0", "ia1", "ia2";
2286 #address-cells = <1>;
2287 #size-cells = <1>;
2288 ranges = <0x00000000 0x48400000 0x400000>, /* segment 0 */
2289 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2290 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2291 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2292 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2293 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2294 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2295 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2296 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2298 segment@0 { /* 0x48400000 */
2299 compatible = "simple-bus";
2300 #address-cells = <1>;
2301 #size-cells = <1>;
2302 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
2303 <0x00001000 0x00001000 0x000400>, /* ap 1 */
2304 <0x00000800 0x00000800 0x000800>, /* ap 2 */
2305 <0x00084000 0x00084000 0x004000>, /* ap 3 */
2306 <0x00001400 0x00001400 0x000400>, /* ap 4 */
2307 <0x00001800 0x00001800 0x000400>, /* ap 5 */
2308 <0x00088000 0x00088000 0x001000>, /* ap 6 */
2309 <0x0002c000 0x0002c000 0x001000>, /* ap 7 */
2310 <0x0002d000 0x0002d000 0x001000>, /* ap 8 */
2311 <0x00060000 0x00060000 0x002000>, /* ap 9 */
2312 <0x00062000 0x00062000 0x001000>, /* ap 10 */
2313 <0x00064000 0x00064000 0x002000>, /* ap 11 */
2314 <0x00066000 0x00066000 0x001000>, /* ap 12 */
2315 <0x00068000 0x00068000 0x002000>, /* ap 13 */
2316 <0x0006a000 0x0006a000 0x001000>, /* ap 14 */
2317 <0x0006c000 0x0006c000 0x002000>, /* ap 15 */
2318 <0x0006e000 0x0006e000 0x001000>, /* ap 16 */
2319 <0x00036000 0x00036000 0x001000>, /* ap 17 */
2320 <0x00037000 0x00037000 0x001000>, /* ap 18 */
2321 <0x00070000 0x00070000 0x002000>, /* ap 19 */
2322 <0x00072000 0x00072000 0x001000>, /* ap 20 */
2323 <0x0003a000 0x0003a000 0x001000>, /* ap 21 */
2324 <0x0003b000 0x0003b000 0x001000>, /* ap 22 */
2325 <0x0003c000 0x0003c000 0x001000>, /* ap 23 */
2326 <0x0003d000 0x0003d000 0x001000>, /* ap 24 */
2327 <0x0003e000 0x0003e000 0x001000>, /* ap 25 */
2328 <0x0003f000 0x0003f000 0x001000>, /* ap 26 */
2329 <0x00040000 0x00040000 0x001000>, /* ap 27 */
2330 <0x00041000 0x00041000 0x001000>, /* ap 28 */
2331 <0x00042000 0x00042000 0x001000>, /* ap 29 */
2332 <0x00043000 0x00043000 0x001000>, /* ap 30 */
2333 <0x00080000 0x00080000 0x002000>, /* ap 31 */
2334 <0x00082000 0x00082000 0x001000>, /* ap 32 */
2335 <0x0004a000 0x0004a000 0x001000>, /* ap 33 */
2336 <0x0004b000 0x0004b000 0x001000>, /* ap 34 */
2337 <0x00074000 0x00074000 0x002000>, /* ap 35 */
2338 <0x00076000 0x00076000 0x001000>, /* ap 36 */
2339 <0x00050000 0x00050000 0x001000>, /* ap 37 */
2340 <0x00051000 0x00051000 0x001000>, /* ap 38 */
2341 <0x00078000 0x00078000 0x002000>, /* ap 39 */
2342 <0x0007a000 0x0007a000 0x001000>, /* ap 40 */
2343 <0x00054000 0x00054000 0x001000>, /* ap 41 */
2344 <0x00055000 0x00055000 0x001000>, /* ap 42 */
2345 <0x0007c000 0x0007c000 0x002000>, /* ap 43 */
2346 <0x0007e000 0x0007e000 0x001000>, /* ap 44 */
2347 <0x0004c000 0x0004c000 0x001000>, /* ap 45 */
2348 <0x0004d000 0x0004d000 0x001000>, /* ap 46 */
2349 <0x00020000 0x00020000 0x001000>, /* ap 47 */
2350 <0x00021000 0x00021000 0x001000>, /* ap 48 */
2351 <0x00022000 0x00022000 0x001000>, /* ap 49 */
2352 <0x00023000 0x00023000 0x001000>, /* ap 50 */
2353 <0x00024000 0x00024000 0x001000>, /* ap 51 */
2354 <0x00025000 0x00025000 0x001000>, /* ap 52 */
2355 <0x00046000 0x00046000 0x001000>, /* ap 53 */
2356 <0x00047000 0x00047000 0x001000>, /* ap 54 */
2357 <0x00048000 0x00048000 0x001000>, /* ap 55 */
2358 <0x00049000 0x00049000 0x001000>, /* ap 56 */
2359 <0x00058000 0x00058000 0x002000>, /* ap 57 */
2360 <0x0005a000 0x0005a000 0x001000>, /* ap 58 */
2361 <0x0005b000 0x0005b000 0x001000>, /* ap 59 */
2362 <0x0005c000 0x0005c000 0x001000>, /* ap 60 */
2363 <0x0005d000 0x0005d000 0x001000>, /* ap 61 */
2364 <0x0005e000 0x0005e000 0x001000>, /* ap 62 */
2365 <0x45800000 0x45800000 0x400000>, /* L3 data port */
2366 <0x45c00000 0x45c00000 0x400000>, /* L3 data port */
2367 <0x46000000 0x46000000 0x400000>, /* L3 data port */
2368 <0x48436000 0x48436000 0x400000>, /* L3 data port */
2369 <0x4843a000 0x4843a000 0x400000>, /* L3 data port */
2370 <0x4844c000 0x4844c000 0x400000>, /* L3 data port */
2371 <0x48450000 0x48450000 0x400000>, /* L3 data port */
2372 <0x48454000 0x48454000 0x400000>; /* L3 data port */
2374 target-module@20000 { /* 0x48420000, ap 47 02.0 */
2375 compatible = "ti,sysc-omap2", "ti,sysc";
2376 reg = <0x20050 0x4>,
2377 <0x20054 0x4>,
2378 <0x20058 0x4>;
2379 reg-names = "rev", "sysc", "syss";
2380 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2381 SYSC_OMAP2_SOFTRESET |
2382 SYSC_OMAP2_AUTOIDLE)>;
2383 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2384 <SYSC_IDLE_NO>,
2385 <SYSC_IDLE_SMART>,
2386 <SYSC_IDLE_SMART_WKUP>;
2387 ti,syss-mask = <1>;
2388 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2389 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART7_CLKCTRL 0>;
2390 clock-names = "fck";
2391 #address-cells = <1>;
2392 #size-cells = <1>;
2393 ranges = <0x0 0x20000 0x1000>;
2395 uart7: serial@0 {
2396 compatible = "ti,dra742-uart", "ti,omap4-uart";
2397 reg = <0x0 0x100>;
2398 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
2399 clock-frequency = <48000000>;
2400 status = "disabled";
2401 };
2402 };
2404 target-module@22000 { /* 0x48422000, ap 49 0a.0 */
2405 compatible = "ti,sysc-omap2", "ti,sysc";
2406 reg = <0x22050 0x4>,
2407 <0x22054 0x4>,
2408 <0x22058 0x4>;
2409 reg-names = "rev", "sysc", "syss";
2410 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2411 SYSC_OMAP2_SOFTRESET |
2412 SYSC_OMAP2_AUTOIDLE)>;
2413 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2414 <SYSC_IDLE_NO>,
2415 <SYSC_IDLE_SMART>,
2416 <SYSC_IDLE_SMART_WKUP>;
2417 ti,syss-mask = <1>;
2418 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2419 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART8_CLKCTRL 0>;
2420 clock-names = "fck";
2421 #address-cells = <1>;
2422 #size-cells = <1>;
2423 ranges = <0x0 0x22000 0x1000>;
2425 uart8: serial@0 {
2426 compatible = "ti,dra742-uart", "ti,omap4-uart";
2427 reg = <0x0 0x100>;
2428 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
2429 clock-frequency = <48000000>;
2430 status = "disabled";
2431 };
2432 };
2434 target-module@24000 { /* 0x48424000, ap 51 12.0 */
2435 compatible = "ti,sysc-omap2", "ti,sysc";
2436 reg = <0x24050 0x4>,
2437 <0x24054 0x4>,
2438 <0x24058 0x4>;
2439 reg-names = "rev", "sysc", "syss";
2440 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
2441 SYSC_OMAP2_SOFTRESET |
2442 SYSC_OMAP2_AUTOIDLE)>;
2443 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2444 <SYSC_IDLE_NO>,
2445 <SYSC_IDLE_SMART>,
2446 <SYSC_IDLE_SMART_WKUP>;
2447 ti,syss-mask = <1>;
2448 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2449 clocks = <&l4per2_clkctrl DRA7_L4PER2_UART9_CLKCTRL 0>;
2450 clock-names = "fck";
2451 #address-cells = <1>;
2452 #size-cells = <1>;
2453 ranges = <0x0 0x24000 0x1000>;
2455 uart9: serial@0 {
2456 compatible = "ti,dra742-uart", "ti,omap4-uart";
2457 reg = <0x0 0x100>;
2458 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
2459 clock-frequency = <48000000>;
2460 status = "disabled";
2461 };
2462 };
2464 target-module@2c000 { /* 0x4842c000, ap 7 18.0 */
2465 compatible = "ti,sysc";
2466 status = "disabled";
2467 #address-cells = <1>;
2468 #size-cells = <1>;
2469 ranges = <0x0 0x2c000 0x1000>;
2470 };
2472 target-module@36000 { /* 0x48436000, ap 17 06.0 */
2473 compatible = "ti,sysc";
2474 status = "disabled";
2475 #address-cells = <1>;
2476 #size-cells = <1>;
2477 ranges = <0x0 0x36000 0x1000>;
2478 };
2480 target-module@3a000 { /* 0x4843a000, ap 21 3e.0 */
2481 compatible = "ti,sysc";
2482 status = "disabled";
2483 #address-cells = <1>;
2484 #size-cells = <1>;
2485 ranges = <0x0 0x3a000 0x1000>;
2486 };
2488 atl_tm: target-module@3c000 { /* 0x4843c000, ap 23 08.0 */
2489 compatible = "ti,sysc-omap4", "ti,sysc";
2490 reg = <0x3c000 0x4>;
2491 reg-names = "rev";
2492 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 0>;
2493 clock-names = "fck";
2494 #address-cells = <1>;
2495 #size-cells = <1>;
2496 ranges = <0x0 0x3c000 0x1000>;
2498 atl: atl@0 {
2499 compatible = "ti,dra7-atl";
2500 reg = <0x0 0x3ff>;
2501 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
2502 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
2503 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
2504 clock-names = "fck";
2505 status = "disabled";
2506 };
2507 };
2509 target-module@3e000 { /* 0x4843e000, ap 25 30.0 */
2510 compatible = "ti,sysc-omap4", "ti,sysc";
2511 reg = <0x3e000 0x4>,
2512 <0x3e004 0x4>;
2513 reg-names = "rev", "sysc";
2514 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2515 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2516 <SYSC_IDLE_NO>,
2517 <SYSC_IDLE_SMART>;
2518 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2519 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS0_CLKCTRL 0>;
2520 clock-names = "fck";
2521 #address-cells = <1>;
2522 #size-cells = <1>;
2523 ranges = <0x0 0x3e000 0x1000>;
2525 epwmss0: epwmss@0 {
2526 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2527 reg = <0x0 0x30>;
2528 #address-cells = <1>;
2529 #size-cells = <1>;
2530 status = "disabled";
2531 ranges = <0 0 0x1000>;
2533 ecap0: ecap@100 {
2534 compatible = "ti,dra746-ecap",
2535 "ti,am3352-ecap";
2536 #pwm-cells = <3>;
2537 reg = <0x100 0x80>;
2538 clocks = <&l4_root_clk_div>;
2539 clock-names = "fck";
2540 status = "disabled";
2541 };
2543 ehrpwm0: pwm@200 {
2544 compatible = "ti,dra746-ehrpwm",
2545 "ti,am3352-ehrpwm";
2546 #pwm-cells = <3>;
2547 reg = <0x200 0x80>;
2548 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>;
2549 clock-names = "tbclk", "fck";
2550 status = "disabled";
2551 };
2552 };
2553 };
2555 target-module@40000 { /* 0x48440000, ap 27 38.0 */
2556 compatible = "ti,sysc-omap4", "ti,sysc";
2557 reg = <0x40000 0x4>,
2558 <0x40004 0x4>;
2559 reg-names = "rev", "sysc";
2560 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2561 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2562 <SYSC_IDLE_NO>,
2563 <SYSC_IDLE_SMART>;
2564 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2565 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS1_CLKCTRL 0>;
2566 clock-names = "fck";
2567 #address-cells = <1>;
2568 #size-cells = <1>;
2569 ranges = <0x0 0x40000 0x1000>;
2571 epwmss1: epwmss@0 {
2572 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2573 reg = <0x0 0x30>;
2574 #address-cells = <1>;
2575 #size-cells = <1>;
2576 status = "disabled";
2577 ranges = <0 0 0x1000>;
2579 ecap1: ecap@100 {
2580 compatible = "ti,dra746-ecap",
2581 "ti,am3352-ecap";
2582 #pwm-cells = <3>;
2583 reg = <0x100 0x80>;
2584 clocks = <&l4_root_clk_div>;
2585 clock-names = "fck";
2586 status = "disabled";
2587 };
2589 ehrpwm1: pwm@200 {
2590 compatible = "ti,dra746-ehrpwm",
2591 "ti,am3352-ehrpwm";
2592 #pwm-cells = <3>;
2593 reg = <0x200 0x80>;
2594 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>;
2595 clock-names = "tbclk", "fck";
2596 status = "disabled";
2597 };
2598 };
2599 };
2601 target-module@42000 { /* 0x48442000, ap 29 20.0 */
2602 compatible = "ti,sysc-omap4", "ti,sysc";
2603 reg = <0x42000 0x4>,
2604 <0x42004 0x4>;
2605 reg-names = "rev", "sysc";
2606 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
2607 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2608 <SYSC_IDLE_NO>,
2609 <SYSC_IDLE_SMART>;
2610 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2611 clocks = <&l4per2_clkctrl DRA7_L4PER2_EPWMSS2_CLKCTRL 0>;
2612 clock-names = "fck";
2613 #address-cells = <1>;
2614 #size-cells = <1>;
2615 ranges = <0x0 0x42000 0x1000>;
2617 epwmss2: epwmss@0 {
2618 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss";
2619 reg = <0x0 0x30>;
2620 #address-cells = <1>;
2621 #size-cells = <1>;
2622 status = "disabled";
2623 ranges = <0 0 0x1000>;
2625 ecap2: ecap@100 {
2626 compatible = "ti,dra746-ecap",
2627 "ti,am3352-ecap";
2628 #pwm-cells = <3>;
2629 reg = <0x100 0x80>;
2630 clocks = <&l4_root_clk_div>;
2631 clock-names = "fck";
2632 status = "disabled";
2633 };
2635 ehrpwm2: pwm@200 {
2636 compatible = "ti,dra746-ehrpwm",
2637 "ti,am3352-ehrpwm";
2638 #pwm-cells = <3>;
2639 reg = <0x200 0x80>;
2640 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>;
2641 clock-names = "tbclk", "fck";
2642 status = "disabled";
2643 };
2644 };
2645 };
2647 target-module@46000 { /* 0x48446000, ap 53 40.0 */
2648 compatible = "ti,sysc";
2649 status = "disabled";
2650 #address-cells = <1>;
2651 #size-cells = <1>;
2652 ranges = <0x0 0x46000 0x1000>;
2653 };
2655 target-module@48000 { /* 0x48448000, ap 55 48.0 */
2656 compatible = "ti,sysc";
2657 status = "disabled";
2658 #address-cells = <1>;
2659 #size-cells = <1>;
2660 ranges = <0x0 0x48000 0x1000>;
2661 };
2663 target-module@4a000 { /* 0x4844a000, ap 33 1a.0 */
2664 compatible = "ti,sysc";
2665 status = "disabled";
2666 #address-cells = <1>;
2667 #size-cells = <1>;
2668 ranges = <0x0 0x4a000 0x1000>;
2669 };
2671 target-module@4c000 { /* 0x4844c000, ap 45 1c.0 */
2672 compatible = "ti,sysc";
2673 status = "disabled";
2674 #address-cells = <1>;
2675 #size-cells = <1>;
2676 ranges = <0x0 0x4c000 0x1000>;
2677 };
2679 target-module@50000 { /* 0x48450000, ap 37 24.0 */
2680 compatible = "ti,sysc";
2681 status = "disabled";
2682 #address-cells = <1>;
2683 #size-cells = <1>;
2684 ranges = <0x0 0x50000 0x1000>;
2685 };
2687 target-module@54000 { /* 0x48454000, ap 41 2c.0 */
2688 compatible = "ti,sysc";
2689 status = "disabled";
2690 #address-cells = <1>;
2691 #size-cells = <1>;
2692 ranges = <0x0 0x54000 0x1000>;
2693 };
2695 target-module@58000 { /* 0x48458000, ap 57 28.0 */
2696 compatible = "ti,sysc";
2697 status = "disabled";
2698 #address-cells = <1>;
2699 #size-cells = <1>;
2700 ranges = <0x0 0x58000 0x2000>;
2701 };
2703 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
2704 compatible = "ti,sysc";
2705 status = "disabled";
2706 #address-cells = <1>;
2707 #size-cells = <1>;
2708 ranges = <0x0 0x5b000 0x1000>;
2709 };
2711 target-module@5d000 { /* 0x4845d000, ap 61 22.0 */
2712 compatible = "ti,sysc";
2713 status = "disabled";
2714 #address-cells = <1>;
2715 #size-cells = <1>;
2716 ranges = <0x0 0x5d000 0x1000>;
2717 };
2719 target-module@60000 { /* 0x48460000, ap 9 0e.0 */
2720 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2721 reg = <0x60000 0x4>,
2722 <0x60004 0x4>;
2723 reg-names = "rev", "sysc";
2724 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2725 <SYSC_IDLE_NO>,
2726 <SYSC_IDLE_SMART>;
2727 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
2728 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2729 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2730 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2731 clock-names = "fck", "ahclkx", "ahclkr";
2732 #address-cells = <1>;
2733 #size-cells = <1>;
2734 ranges = <0x0 0x60000 0x2000>,
2735 <0x45800000 0x45800000 0x400000>;
2737 mcasp1: mcasp@0 {
2738 compatible = "ti,dra7-mcasp-audio";
2739 reg = <0x0 0x2000>,
2740 <0x45800000 0x1000>; /* L3 data port */
2741 reg-names = "mpu","dat";
2742 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2743 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
2744 interrupt-names = "tx", "rx";
2745 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
2746 dma-names = "tx", "rx";
2747 clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
2748 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2749 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
2750 clock-names = "fck", "ahclkx", "ahclkr";
2751 status = "disabled";
2752 };
2753 };
2755 target-module@64000 { /* 0x48464000, ap 11 1e.0 */
2756 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2757 reg = <0x64000 0x4>,
2758 <0x64004 0x4>;
2759 reg-names = "rev", "sysc";
2760 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2761 <SYSC_IDLE_NO>,
2762 <SYSC_IDLE_SMART>;
2763 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2764 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2765 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>,
2766 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2767 clock-names = "fck", "ahclkx", "ahclkr";
2768 #address-cells = <1>;
2769 #size-cells = <1>;
2770 ranges = <0x0 0x64000 0x2000>,
2771 <0x45c00000 0x45c00000 0x400000>;
2773 mcasp2: mcasp@0 {
2774 compatible = "ti,dra7-mcasp-audio";
2775 reg = <0x0 0x2000>,
2776 <0x45c00000 0x1000>; /* L3 data port */
2777 reg-names = "mpu","dat";
2778 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2779 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2780 interrupt-names = "tx", "rx";
2781 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
2782 dma-names = "tx", "rx";
2783 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
2784 <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
2785 <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
2786 clock-names = "fck", "ahclkx", "ahclkr";
2787 status = "disabled";
2788 };
2789 };
2791 target-module@68000 { /* 0x48468000, ap 13 26.0 */
2792 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2793 reg = <0x68000 0x4>,
2794 <0x68004 0x4>;
2795 reg-names = "rev", "sysc";
2796 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2797 <SYSC_IDLE_NO>,
2798 <SYSC_IDLE_SMART>;
2799 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2800 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2801 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2802 clock-names = "fck", "ahclkx";
2803 #address-cells = <1>;
2804 #size-cells = <1>;
2805 ranges = <0x0 0x68000 0x2000>,
2806 <0x46000000 0x46000000 0x400000>;
2808 mcasp3: mcasp@0 {
2809 compatible = "ti,dra7-mcasp-audio";
2810 reg = <0x0 0x2000>,
2811 <0x46000000 0x1000>; /* L3 data port */
2812 reg-names = "mpu","dat";
2813 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
2814 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
2815 interrupt-names = "tx", "rx";
2816 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
2817 dma-names = "tx", "rx";
2818 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
2819 <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2820 clock-names = "fck", "ahclkx";
2821 status = "disabled";
2822 };
2823 };
2825 target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
2826 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2827 reg = <0x6c000 0x4>,
2828 <0x6c004 0x4>;
2829 reg-names = "rev", "sysc";
2830 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2831 <SYSC_IDLE_NO>,
2832 <SYSC_IDLE_SMART>;
2833 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2834 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2835 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2836 clock-names = "fck", "ahclkx";
2837 #address-cells = <1>;
2838 #size-cells = <1>;
2839 ranges = <0x0 0x6c000 0x2000>,
2840 <0x48436000 0x48436000 0x400000>;
2842 mcasp4: mcasp@0 {
2843 compatible = "ti,dra7-mcasp-audio";
2844 reg = <0x0 0x2000>,
2845 <0x48436000 0x1000>; /* L3 data port */
2846 reg-names = "mpu","dat";
2847 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
2848 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
2849 interrupt-names = "tx", "rx";
2850 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
2851 dma-names = "tx", "rx";
2852 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
2853 <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
2854 clock-names = "fck", "ahclkx";
2855 status = "disabled";
2856 };
2857 };
2859 target-module@70000 { /* 0x48470000, ap 19 36.0 */
2860 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2861 reg = <0x70000 0x4>,
2862 <0x70004 0x4>;
2863 reg-names = "rev", "sysc";
2864 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2865 <SYSC_IDLE_NO>,
2866 <SYSC_IDLE_SMART>;
2867 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2868 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2869 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2870 clock-names = "fck", "ahclkx";
2871 #address-cells = <1>;
2872 #size-cells = <1>;
2873 ranges = <0x0 0x70000 0x2000>,
2874 <0x4843a000 0x4843a000 0x400000>;
2876 mcasp5: mcasp@0 {
2877 compatible = "ti,dra7-mcasp-audio";
2878 reg = <0x0 0x2000>,
2879 <0x4843a000 0x1000>; /* L3 data port */
2880 reg-names = "mpu","dat";
2881 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
2882 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
2883 interrupt-names = "tx", "rx";
2884 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
2885 dma-names = "tx", "rx";
2886 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
2887 <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
2888 clock-names = "fck", "ahclkx";
2889 status = "disabled";
2890 };
2891 };
2893 target-module@74000 { /* 0x48474000, ap 35 14.0 */
2894 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2895 reg = <0x74000 0x4>,
2896 <0x74004 0x4>;
2897 reg-names = "rev", "sysc";
2898 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2899 <SYSC_IDLE_NO>,
2900 <SYSC_IDLE_SMART>;
2901 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2902 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2903 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2904 clock-names = "fck", "ahclkx";
2905 #address-cells = <1>;
2906 #size-cells = <1>;
2907 ranges = <0x0 0x74000 0x2000>,
2908 <0x4844c000 0x4844c000 0x400000>;
2910 mcasp6: mcasp@0 {
2911 compatible = "ti,dra7-mcasp-audio";
2912 reg = <0x0 0x2000>,
2913 <0x4844c000 0x1000>; /* L3 data port */
2914 reg-names = "mpu","dat";
2915 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
2916 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
2917 interrupt-names = "tx", "rx";
2918 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
2919 dma-names = "tx", "rx";
2920 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
2921 <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
2922 clock-names = "fck", "ahclkx";
2923 status = "disabled";
2924 };
2925 };
2927 target-module@78000 { /* 0x48478000, ap 39 0c.0 */
2928 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2929 reg = <0x78000 0x4>,
2930 <0x78004 0x4>;
2931 reg-names = "rev", "sysc";
2932 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2933 <SYSC_IDLE_NO>,
2934 <SYSC_IDLE_SMART>;
2935 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2936 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2937 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2938 clock-names = "fck", "ahclkx";
2939 #address-cells = <1>;
2940 #size-cells = <1>;
2941 ranges = <0x0 0x78000 0x2000>,
2942 <0x48450000 0x48450000 0x400000>;
2944 mcasp7: mcasp@0 {
2945 compatible = "ti,dra7-mcasp-audio";
2946 reg = <0x0 0x2000>,
2947 <0x48450000 0x1000>; /* L3 data port */
2948 reg-names = "mpu","dat";
2949 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
2950 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
2951 interrupt-names = "tx", "rx";
2952 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
2953 dma-names = "tx", "rx";
2954 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
2955 <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
2956 clock-names = "fck", "ahclkx";
2957 status = "disabled";
2958 };
2959 };
2961 target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
2962 compatible = "ti,sysc-dra7-mcasp", "ti,sysc";
2963 reg = <0x7c000 0x4>,
2964 <0x7c004 0x4>;
2965 reg-names = "rev", "sysc";
2966 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
2967 <SYSC_IDLE_NO>,
2968 <SYSC_IDLE_SMART>;
2969 /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
2970 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2971 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2972 clock-names = "fck", "ahclkx";
2973 #address-cells = <1>;
2974 #size-cells = <1>;
2975 ranges = <0x0 0x7c000 0x2000>,
2976 <0x48454000 0x48454000 0x400000>;
2978 mcasp8: mcasp@0 {
2979 compatible = "ti,dra7-mcasp-audio";
2980 reg = <0x0 0x2000>,
2981 <0x48454000 0x1000>; /* L3 data port */
2982 reg-names = "mpu","dat";
2983 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
2984 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
2985 interrupt-names = "tx", "rx";
2986 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
2987 dma-names = "tx", "rx";
2988 clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
2989 <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
2990 clock-names = "fck", "ahclkx";
2991 status = "disabled";
2992 };
2993 };
2995 target-module@80000 { /* 0x48480000, ap 31 16.0 */
2996 compatible = "ti,sysc-omap4", "ti,sysc";
2997 reg = <0x80020 0x4>;
2998 reg-names = "rev";
2999 clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
3000 clock-names = "fck";
3001 #address-cells = <1>;
3002 #size-cells = <1>;
3003 ranges = <0x0 0x80000 0x2000>;
3005 dcan2: can@0 {
3006 compatible = "ti,dra7-d_can";
3007 reg = <0x0 0x2000>;
3008 syscon-raminit = <&scm_conf 0x558 1>;
3009 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
3010 clocks = <&sys_clkin1>;
3011 status = "disabled";
3012 };
3013 };
3015 target-module@84000 { /* 0x48484000, ap 3 10.0 */
3016 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3017 reg = <0x85200 0x4>,
3018 <0x85208 0x4>,
3019 <0x85204 0x4>;
3020 reg-names = "rev", "sysc", "syss";
3021 ti,sysc-mask = <0>;
3022 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3023 <SYSC_IDLE_NO>;
3024 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3025 <SYSC_IDLE_NO>;
3026 ti,syss-mask = <1>;
3027 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 0>;
3028 clock-names = "fck";
3029 #address-cells = <1>;
3030 #size-cells = <1>;
3031 ranges = <0x0 0x84000 0x4000>;
3032 /*
3033 * Do not allow gating of cpsw clock as workaround
3034 * for errata i877. Keeping internal clock disabled
3035 * causes the device switching characteristics
3036 * to degrade over time and eventually fail to meet
3037 * the data manual delay time/skew specs.
3038 */
3039 ti,no-idle;
3041 mac_sw: switch@0 {
3042 compatible = "ti,dra7-cpsw-switch","ti,cpsw-switch";
3043 reg = <0x0 0x4000>;
3044 ranges = <0 0 0x4000>;
3045 clocks = <&gmac_main_clk>;
3046 clock-names = "fck";
3047 #address-cells = <1>;
3048 #size-cells = <1>;
3049 syscon = <&scm_conf>;
3050 status = "disabled";
3052 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3053 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3054 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3055 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
3056 interrupt-names = "rx_thresh", "rx", "tx", "misc";
3058 ethernet-ports {
3059 #address-cells = <1>;
3060 #size-cells = <0>;
3062 cpsw_port1: port@1 {
3063 reg = <1>;
3064 label = "port1";
3065 mac-address = [ 00 00 00 00 00 00 ];
3066 phys = <&phy_gmii_sel 1>;
3067 };
3069 cpsw_port2: port@2 {
3070 reg = <2>;
3071 label = "port2";
3072 mac-address = [ 00 00 00 00 00 00 ];
3073 phys = <&phy_gmii_sel 2>;
3074 };
3075 };
3077 davinci_mdio_sw: mdio@1000 {
3078 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
3079 clocks = <&gmac_main_clk>;
3080 clock-names = "fck";
3081 #address-cells = <1>;
3082 #size-cells = <0>;
3083 bus_freq = <1000000>;
3084 reg = <0x1000 0x100>;
3085 };
3087 cpts {
3088 clocks = <&gmac_clkctrl DRA7_GMAC_GMAC_CLKCTRL 25>;
3089 clock-names = "cpts";
3090 };
3091 };
3092 };
3093 };
3094 };
3096 &l4_per3 { /* 0x48800000 */
3097 compatible = "ti,dra7-l4-per3", "simple-bus";
3098 reg = <0x48800000 0x800>,
3099 <0x48800800 0x800>,
3100 <0x48801000 0x400>,
3101 <0x48801400 0x400>,
3102 <0x48801800 0x400>;
3103 reg-names = "ap", "la", "ia0", "ia1", "ia2";
3104 #address-cells = <1>;
3105 #size-cells = <1>;
3106 ranges = <0x00000000 0x48800000 0x200000>; /* segment 0 */
3108 segment@0 { /* 0x48800000 */
3109 compatible = "simple-bus";
3110 #address-cells = <1>;
3111 #size-cells = <1>;
3112 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
3113 <0x00000800 0x00000800 0x000800>, /* ap 1 */
3114 <0x00001000 0x00001000 0x000400>, /* ap 2 */
3115 <0x00001400 0x00001400 0x000400>, /* ap 3 */
3116 <0x00001800 0x00001800 0x000400>, /* ap 4 */
3117 <0x00020000 0x00020000 0x001000>, /* ap 5 */
3118 <0x00021000 0x00021000 0x001000>, /* ap 6 */
3119 <0x00022000 0x00022000 0x001000>, /* ap 7 */
3120 <0x00023000 0x00023000 0x001000>, /* ap 8 */
3121 <0x00024000 0x00024000 0x001000>, /* ap 9 */
3122 <0x00025000 0x00025000 0x001000>, /* ap 10 */
3123 <0x00026000 0x00026000 0x001000>, /* ap 11 */
3124 <0x00027000 0x00027000 0x001000>, /* ap 12 */
3125 <0x00028000 0x00028000 0x001000>, /* ap 13 */
3126 <0x00029000 0x00029000 0x001000>, /* ap 14 */
3127 <0x0002a000 0x0002a000 0x001000>, /* ap 15 */
3128 <0x0002b000 0x0002b000 0x001000>, /* ap 16 */
3129 <0x0002c000 0x0002c000 0x001000>, /* ap 17 */
3130 <0x0002d000 0x0002d000 0x001000>, /* ap 18 */
3131 <0x0002e000 0x0002e000 0x001000>, /* ap 19 */
3132 <0x0002f000 0x0002f000 0x001000>, /* ap 20 */
3133 <0x00170000 0x00170000 0x010000>, /* ap 21 */
3134 <0x00180000 0x00180000 0x001000>, /* ap 22 */
3135 <0x00190000 0x00190000 0x010000>, /* ap 23 */
3136 <0x001a0000 0x001a0000 0x001000>, /* ap 24 */
3137 <0x001b0000 0x001b0000 0x010000>, /* ap 25 */
3138 <0x001c0000 0x001c0000 0x001000>, /* ap 26 */
3139 <0x001d0000 0x001d0000 0x010000>, /* ap 27 */
3140 <0x001e0000 0x001e0000 0x001000>, /* ap 28 */
3141 <0x00038000 0x00038000 0x001000>, /* ap 29 */
3142 <0x00039000 0x00039000 0x001000>, /* ap 30 */
3143 <0x0005c000 0x0005c000 0x001000>, /* ap 31 */
3144 <0x0005d000 0x0005d000 0x001000>, /* ap 32 */
3145 <0x0003a000 0x0003a000 0x001000>, /* ap 33 */
3146 <0x0003b000 0x0003b000 0x001000>, /* ap 34 */
3147 <0x0003c000 0x0003c000 0x001000>, /* ap 35 */
3148 <0x0003d000 0x0003d000 0x001000>, /* ap 36 */
3149 <0x0003e000 0x0003e000 0x001000>, /* ap 37 */
3150 <0x0003f000 0x0003f000 0x001000>, /* ap 38 */
3151 <0x00040000 0x00040000 0x001000>, /* ap 39 */
3152 <0x00041000 0x00041000 0x001000>, /* ap 40 */
3153 <0x00042000 0x00042000 0x001000>, /* ap 41 */
3154 <0x00043000 0x00043000 0x001000>, /* ap 42 */
3155 <0x00044000 0x00044000 0x001000>, /* ap 43 */
3156 <0x00045000 0x00045000 0x001000>, /* ap 44 */
3157 <0x00046000 0x00046000 0x001000>, /* ap 45 */
3158 <0x00047000 0x00047000 0x001000>, /* ap 46 */
3159 <0x00048000 0x00048000 0x001000>, /* ap 47 */
3160 <0x00049000 0x00049000 0x001000>, /* ap 48 */
3161 <0x0004a000 0x0004a000 0x001000>, /* ap 49 */
3162 <0x0004b000 0x0004b000 0x001000>, /* ap 50 */
3163 <0x0004c000 0x0004c000 0x001000>, /* ap 51 */
3164 <0x0004d000 0x0004d000 0x001000>, /* ap 52 */
3165 <0x0004e000 0x0004e000 0x001000>, /* ap 53 */
3166 <0x0004f000 0x0004f000 0x001000>, /* ap 54 */
3167 <0x00050000 0x00050000 0x001000>, /* ap 55 */
3168 <0x00051000 0x00051000 0x001000>, /* ap 56 */
3169 <0x00052000 0x00052000 0x001000>, /* ap 57 */
3170 <0x00053000 0x00053000 0x001000>, /* ap 58 */
3171 <0x00054000 0x00054000 0x001000>, /* ap 59 */
3172 <0x00055000 0x00055000 0x001000>, /* ap 60 */
3173 <0x00056000 0x00056000 0x001000>, /* ap 61 */
3174 <0x00057000 0x00057000 0x001000>, /* ap 62 */
3175 <0x00058000 0x00058000 0x001000>, /* ap 63 */
3176 <0x00059000 0x00059000 0x001000>, /* ap 64 */
3177 <0x0005a000 0x0005a000 0x001000>, /* ap 65 */
3178 <0x0005b000 0x0005b000 0x001000>, /* ap 66 */
3179 <0x00064000 0x00064000 0x001000>, /* ap 67 */
3180 <0x00065000 0x00065000 0x001000>, /* ap 68 */
3181 <0x0005e000 0x0005e000 0x001000>, /* ap 69 */
3182 <0x0005f000 0x0005f000 0x001000>, /* ap 70 */
3183 <0x00060000 0x00060000 0x001000>, /* ap 71 */
3184 <0x00061000 0x00061000 0x001000>, /* ap 72 */
3185 <0x00062000 0x00062000 0x001000>, /* ap 73 */
3186 <0x00063000 0x00063000 0x001000>, /* ap 74 */
3187 <0x00140000 0x00140000 0x020000>, /* ap 75 */
3188 <0x00160000 0x00160000 0x001000>, /* ap 76 */
3189 <0x00016000 0x00016000 0x001000>, /* ap 77 */
3190 <0x00017000 0x00017000 0x001000>, /* ap 78 */
3191 <0x000c0000 0x000c0000 0x020000>, /* ap 79 */
3192 <0x000e0000 0x000e0000 0x001000>, /* ap 80 */
3193 <0x00004000 0x00004000 0x001000>, /* ap 81 */
3194 <0x00005000 0x00005000 0x001000>, /* ap 82 */
3195 <0x00080000 0x00080000 0x020000>, /* ap 83 */
3196 <0x000a0000 0x000a0000 0x001000>, /* ap 84 */
3197 <0x00100000 0x00100000 0x020000>, /* ap 85 */
3198 <0x00120000 0x00120000 0x001000>, /* ap 86 */
3199 <0x00010000 0x00010000 0x001000>, /* ap 87 */
3200 <0x00011000 0x00011000 0x001000>, /* ap 88 */
3201 <0x0000a000 0x0000a000 0x001000>, /* ap 89 */
3202 <0x0000b000 0x0000b000 0x001000>, /* ap 90 */
3203 <0x0001c000 0x0001c000 0x001000>, /* ap 91 */
3204 <0x0001d000 0x0001d000 0x001000>, /* ap 92 */
3205 <0x0001e000 0x0001e000 0x001000>, /* ap 93 */
3206 <0x0001f000 0x0001f000 0x001000>, /* ap 94 */
3207 <0x00002000 0x00002000 0x001000>, /* ap 95 */
3208 <0x00003000 0x00003000 0x001000>; /* ap 96 */
3210 target-module@2000 { /* 0x48802000, ap 95 7c.0 */
3211 compatible = "ti,sysc-omap4", "ti,sysc";
3212 reg = <0x2000 0x4>,
3213 <0x2010 0x4>;
3214 reg-names = "rev", "sysc";
3215 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3216 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3217 <SYSC_IDLE_NO>,
3218 <SYSC_IDLE_SMART>;
3219 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3220 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX13_CLKCTRL 0>;
3221 clock-names = "fck";
3222 #address-cells = <1>;
3223 #size-cells = <1>;
3224 ranges = <0x0 0x2000 0x1000>;
3226 mailbox13: mailbox@0 {
3227 compatible = "ti,omap4-mailbox";
3228 reg = <0x0 0x200>;
3229 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
3230 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
3231 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
3232 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
3233 #mbox-cells = <1>;
3234 ti,mbox-num-users = <4>;
3235 ti,mbox-num-fifos = <12>;
3236 status = "disabled";
3237 };
3238 };
3240 target-module@4000 { /* 0x48804000, ap 81 20.0 */
3241 compatible = "ti,sysc";
3242 status = "disabled";
3243 #address-cells = <1>;
3244 #size-cells = <1>;
3245 ranges = <0x0 0x4000 0x1000>;
3246 };
3248 target-module@a000 { /* 0x4880a000, ap 89 18.0 */
3249 compatible = "ti,sysc";
3250 status = "disabled";
3251 #address-cells = <1>;
3252 #size-cells = <1>;
3253 ranges = <0x0 0xa000 0x1000>;
3254 };
3256 target-module@10000 { /* 0x48810000, ap 87 28.0 */
3257 compatible = "ti,sysc";
3258 status = "disabled";
3259 #address-cells = <1>;
3260 #size-cells = <1>;
3261 ranges = <0x0 0x10000 0x1000>;
3262 };
3264 target-module@16000 { /* 0x48816000, ap 77 1e.0 */
3265 compatible = "ti,sysc";
3266 status = "disabled";
3267 #address-cells = <1>;
3268 #size-cells = <1>;
3269 ranges = <0x0 0x16000 0x1000>;
3270 };
3272 target-module@1c000 { /* 0x4881c000, ap 91 1c.0 */
3273 compatible = "ti,sysc";
3274 status = "disabled";
3275 #address-cells = <1>;
3276 #size-cells = <1>;
3277 ranges = <0x0 0x1c000 0x1000>;
3278 };
3280 target-module@1e000 { /* 0x4881e000, ap 93 2c.0 */
3281 compatible = "ti,sysc";
3282 status = "disabled";
3283 #address-cells = <1>;
3284 #size-cells = <1>;
3285 ranges = <0x0 0x1e000 0x1000>;
3286 };
3288 target-module@20000 { /* 0x48820000, ap 5 08.0 */
3289 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3290 reg = <0x20000 0x4>,
3291 <0x20010 0x4>;
3292 reg-names = "rev", "sysc";
3293 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3294 SYSC_OMAP4_SOFTRESET)>;
3295 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3296 <SYSC_IDLE_NO>,
3297 <SYSC_IDLE_SMART>,
3298 <SYSC_IDLE_SMART_WKUP>;
3299 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3300 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3301 clock-names = "fck";
3302 #address-cells = <1>;
3303 #size-cells = <1>;
3304 ranges = <0x0 0x20000 0x1000>;
3306 timer5: timer@0 {
3307 compatible = "ti,omap5430-timer";
3308 reg = <0x0 0x80>;
3309 clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>;
3310 clock-names = "fck", "timer_sys_ck";
3311 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
3312 };
3313 };
3315 target-module@22000 { /* 0x48822000, ap 7 24.0 */
3316 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3317 reg = <0x22000 0x4>,
3318 <0x22010 0x4>;
3319 reg-names = "rev", "sysc";
3320 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3321 SYSC_OMAP4_SOFTRESET)>;
3322 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3323 <SYSC_IDLE_NO>,
3324 <SYSC_IDLE_SMART>,
3325 <SYSC_IDLE_SMART_WKUP>;
3326 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3327 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3328 clock-names = "fck";
3329 #address-cells = <1>;
3330 #size-cells = <1>;
3331 ranges = <0x0 0x22000 0x1000>;
3333 timer6: timer@0 {
3334 compatible = "ti,omap5430-timer";
3335 reg = <0x0 0x80>;
3336 clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>;
3337 clock-names = "fck", "timer_sys_ck";
3338 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3339 };
3340 };
3342 target-module@24000 { /* 0x48824000, ap 9 26.0 */
3343 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3344 reg = <0x24000 0x4>,
3345 <0x24010 0x4>;
3346 reg-names = "rev", "sysc";
3347 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3348 SYSC_OMAP4_SOFTRESET)>;
3349 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3350 <SYSC_IDLE_NO>,
3351 <SYSC_IDLE_SMART>,
3352 <SYSC_IDLE_SMART_WKUP>;
3353 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3354 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 0>;
3355 clock-names = "fck";
3356 #address-cells = <1>;
3357 #size-cells = <1>;
3358 ranges = <0x0 0x24000 0x1000>;
3360 timer7: timer@0 {
3361 compatible = "ti,omap5430-timer";
3362 reg = <0x0 0x80>;
3363 clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;
3364 clock-names = "fck", "timer_sys_ck";
3365 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3366 };
3367 };
3369 target-module@26000 { /* 0x48826000, ap 11 0c.0 */
3370 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3371 reg = <0x26000 0x4>,
3372 <0x26010 0x4>;
3373 reg-names = "rev", "sysc";
3374 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3375 SYSC_OMAP4_SOFTRESET)>;
3376 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3377 <SYSC_IDLE_NO>,
3378 <SYSC_IDLE_SMART>,
3379 <SYSC_IDLE_SMART_WKUP>;
3380 /* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3381 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 0>;
3382 clock-names = "fck";
3383 #address-cells = <1>;
3384 #size-cells = <1>;
3385 ranges = <0x0 0x26000 0x1000>;
3387 timer8: timer@0 {
3388 compatible = "ti,omap5430-timer";
3389 reg = <0x0 0x80>;
3390 clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;
3391 clock-names = "fck", "timer_sys_ck";
3392 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
3393 };
3394 };
3396 target-module@28000 { /* 0x48828000, ap 13 16.0 */
3397 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3398 reg = <0x28000 0x4>,
3399 <0x28010 0x4>;
3400 reg-names = "rev", "sysc";
3401 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3402 SYSC_OMAP4_SOFTRESET)>;
3403 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3404 <SYSC_IDLE_NO>,
3405 <SYSC_IDLE_SMART>,
3406 <SYSC_IDLE_SMART_WKUP>;
3407 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3408 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 0>;
3409 clock-names = "fck";
3410 #address-cells = <1>;
3411 #size-cells = <1>;
3412 ranges = <0x0 0x28000 0x1000>;
3414 timer13: timer@0 {
3415 compatible = "ti,omap5430-timer";
3416 reg = <0x0 0x80>;
3417 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>;
3418 clock-names = "fck", "timer_sys_ck";
3419 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
3420 ti,timer-pwm;
3421 };
3422 };
3424 target-module@2a000 { /* 0x4882a000, ap 15 10.0 */
3425 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3426 reg = <0x2a000 0x4>,
3427 <0x2a010 0x4>;
3428 reg-names = "rev", "sysc";
3429 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3430 SYSC_OMAP4_SOFTRESET)>;
3431 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3432 <SYSC_IDLE_NO>,
3433 <SYSC_IDLE_SMART>,
3434 <SYSC_IDLE_SMART_WKUP>;
3435 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3436 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 0>;
3437 clock-names = "fck";
3438 #address-cells = <1>;
3439 #size-cells = <1>;
3440 ranges = <0x0 0x2a000 0x1000>;
3442 timer14: timer@0 {
3443 compatible = "ti,omap5430-timer";
3444 reg = <0x0 0x80>;
3445 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>;
3446 clock-names = "fck", "timer_sys_ck";
3447 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
3448 ti,timer-pwm;
3449 };
3450 };
3452 target-module@2c000 { /* 0x4882c000, ap 17 02.0 */
3453 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3454 reg = <0x2c000 0x4>,
3455 <0x2c010 0x4>;
3456 reg-names = "rev", "sysc";
3457 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3458 SYSC_OMAP4_SOFTRESET)>;
3459 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3460 <SYSC_IDLE_NO>,
3461 <SYSC_IDLE_SMART>,
3462 <SYSC_IDLE_SMART_WKUP>;
3463 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3464 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 0>;
3465 clock-names = "fck";
3466 #address-cells = <1>;
3467 #size-cells = <1>;
3468 ranges = <0x0 0x2c000 0x1000>;
3470 timer15: timer@0 {
3471 compatible = "ti,omap5430-timer";
3472 reg = <0x0 0x80>;
3473 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>;
3474 clock-names = "fck", "timer_sys_ck";
3475 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
3476 ti,timer-pwm;
3477 };
3478 };
3480 target-module@2e000 { /* 0x4882e000, ap 19 14.0 */
3481 compatible = "ti,sysc-omap4-timer", "ti,sysc";
3482 reg = <0x2e000 0x4>,
3483 <0x2e010 0x4>;
3484 reg-names = "rev", "sysc";
3485 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
3486 SYSC_OMAP4_SOFTRESET)>;
3487 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3488 <SYSC_IDLE_NO>,
3489 <SYSC_IDLE_SMART>,
3490 <SYSC_IDLE_SMART_WKUP>;
3491 /* Domains (P, C): l4per_pwrdm, l4per3_clkdm */
3492 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 0>;
3493 clock-names = "fck";
3494 #address-cells = <1>;
3495 #size-cells = <1>;
3496 ranges = <0x0 0x2e000 0x1000>;
3498 timer16: timer@0 {
3499 compatible = "ti,omap5430-timer";
3500 reg = <0x0 0x80>;
3501 clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>;
3502 clock-names = "fck", "timer_sys_ck";
3503 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
3504 ti,timer-pwm;
3505 };
3506 };
3508 rtctarget: target-module@38000 { /* 0x48838000, ap 29 12.0 */
3509 compatible = "ti,sysc-omap4-simple", "ti,sysc";
3510 reg = <0x38074 0x4>,
3511 <0x38078 0x4>;
3512 reg-names = "rev", "sysc";
3513 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3514 <SYSC_IDLE_NO>,
3515 <SYSC_IDLE_SMART>,
3516 <SYSC_IDLE_SMART_WKUP>;
3517 /* Domains (P, C): rtc_pwrdm, rtc_clkdm */
3518 clocks = <&rtc_clkctrl DRA7_RTC_RTCSS_CLKCTRL 0>;
3519 clock-names = "fck";
3520 #address-cells = <1>;
3521 #size-cells = <1>;
3522 ranges = <0x0 0x38000 0x1000>;
3524 rtc: rtc@0 {
3525 compatible = "ti,am3352-rtc";
3526 reg = <0x0 0x100>;
3527 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
3528 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
3529 clocks = <&sys_32k_ck>;
3530 };
3531 };
3533 target-module@3a000 { /* 0x4883a000, ap 33 3e.0 */
3534 compatible = "ti,sysc-omap4", "ti,sysc";
3535 reg = <0x3a000 0x4>,
3536 <0x3a010 0x4>;
3537 reg-names = "rev", "sysc";
3538 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3539 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3540 <SYSC_IDLE_NO>,
3541 <SYSC_IDLE_SMART>;
3542 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3543 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX2_CLKCTRL 0>;
3544 clock-names = "fck";
3545 #address-cells = <1>;
3546 #size-cells = <1>;
3547 ranges = <0x0 0x3a000 0x1000>;
3549 mailbox2: mailbox@0 {
3550 compatible = "ti,omap4-mailbox";
3551 reg = <0x0 0x200>;
3552 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
3554 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
3555 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
3556 #mbox-cells = <1>;
3557 ti,mbox-num-users = <4>;
3558 ti,mbox-num-fifos = <12>;
3559 status = "disabled";
3560 };
3561 };
3563 target-module@3c000 { /* 0x4883c000, ap 35 3a.0 */
3564 compatible = "ti,sysc-omap4", "ti,sysc";
3565 reg = <0x3c000 0x4>,
3566 <0x3c010 0x4>;
3567 reg-names = "rev", "sysc";
3568 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3569 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3570 <SYSC_IDLE_NO>,
3571 <SYSC_IDLE_SMART>;
3572 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3573 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX3_CLKCTRL 0>;
3574 clock-names = "fck";
3575 #address-cells = <1>;
3576 #size-cells = <1>;
3577 ranges = <0x0 0x3c000 0x1000>;
3579 mailbox3: mailbox@0 {
3580 compatible = "ti,omap4-mailbox";
3581 reg = <0x0 0x200>;
3582 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
3583 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
3584 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
3585 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
3586 #mbox-cells = <1>;
3587 ti,mbox-num-users = <4>;
3588 ti,mbox-num-fifos = <12>;
3589 status = "disabled";
3590 };
3591 };
3593 target-module@3e000 { /* 0x4883e000, ap 37 46.0 */
3594 compatible = "ti,sysc-omap4", "ti,sysc";
3595 reg = <0x3e000 0x4>,
3596 <0x3e010 0x4>;
3597 reg-names = "rev", "sysc";
3598 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3599 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3600 <SYSC_IDLE_NO>,
3601 <SYSC_IDLE_SMART>;
3602 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3603 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX4_CLKCTRL 0>;
3604 clock-names = "fck";
3605 #address-cells = <1>;
3606 #size-cells = <1>;
3607 ranges = <0x0 0x3e000 0x1000>;
3609 mailbox4: mailbox@0 {
3610 compatible = "ti,omap4-mailbox";
3611 reg = <0x0 0x200>;
3612 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
3613 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
3614 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
3615 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
3616 #mbox-cells = <1>;
3617 ti,mbox-num-users = <4>;
3618 ti,mbox-num-fifos = <12>;
3619 status = "disabled";
3620 };
3621 };
3623 target-module@40000 { /* 0x48840000, ap 39 64.0 */
3624 compatible = "ti,sysc-omap4", "ti,sysc";
3625 reg = <0x40000 0x4>,
3626 <0x40010 0x4>;
3627 reg-names = "rev", "sysc";
3628 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3629 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3630 <SYSC_IDLE_NO>,
3631 <SYSC_IDLE_SMART>;
3632 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3633 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX5_CLKCTRL 0>;
3634 clock-names = "fck";
3635 #address-cells = <1>;
3636 #size-cells = <1>;
3637 ranges = <0x0 0x40000 0x1000>;
3639 mailbox5: mailbox@0 {
3640 compatible = "ti,omap4-mailbox";
3641 reg = <0x0 0x200>;
3642 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
3643 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
3644 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
3645 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
3646 #mbox-cells = <1>;
3647 ti,mbox-num-users = <4>;
3648 ti,mbox-num-fifos = <12>;
3649 status = "disabled";
3650 };
3651 };
3653 target-module@42000 { /* 0x48842000, ap 41 4e.0 */
3654 compatible = "ti,sysc-omap4", "ti,sysc";
3655 reg = <0x42000 0x4>,
3656 <0x42010 0x4>;
3657 reg-names = "rev", "sysc";
3658 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3659 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3660 <SYSC_IDLE_NO>,
3661 <SYSC_IDLE_SMART>;
3662 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3663 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX6_CLKCTRL 0>;
3664 clock-names = "fck";
3665 #address-cells = <1>;
3666 #size-cells = <1>;
3667 ranges = <0x0 0x42000 0x1000>;
3669 mailbox6: mailbox@0 {
3670 compatible = "ti,omap4-mailbox";
3671 reg = <0x0 0x200>;
3672 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
3673 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
3674 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
3675 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
3676 #mbox-cells = <1>;
3677 ti,mbox-num-users = <4>;
3678 ti,mbox-num-fifos = <12>;
3679 status = "disabled";
3680 };
3681 };
3683 target-module@44000 { /* 0x48844000, ap 43 42.0 */
3684 compatible = "ti,sysc-omap4", "ti,sysc";
3685 reg = <0x44000 0x4>,
3686 <0x44010 0x4>;
3687 reg-names = "rev", "sysc";
3688 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3689 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3690 <SYSC_IDLE_NO>,
3691 <SYSC_IDLE_SMART>;
3692 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3693 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX7_CLKCTRL 0>;
3694 clock-names = "fck";
3695 #address-cells = <1>;
3696 #size-cells = <1>;
3697 ranges = <0x0 0x44000 0x1000>;
3699 mailbox7: mailbox@0 {
3700 compatible = "ti,omap4-mailbox";
3701 reg = <0x0 0x200>;
3702 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
3703 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
3704 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
3705 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
3706 #mbox-cells = <1>;
3707 ti,mbox-num-users = <4>;
3708 ti,mbox-num-fifos = <12>;
3709 status = "disabled";
3710 };
3711 };
3713 target-module@46000 { /* 0x48846000, ap 45 48.0 */
3714 compatible = "ti,sysc-omap4", "ti,sysc";
3715 reg = <0x46000 0x4>,
3716 <0x46010 0x4>;
3717 reg-names = "rev", "sysc";
3718 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3719 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3720 <SYSC_IDLE_NO>,
3721 <SYSC_IDLE_SMART>;
3722 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3723 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX8_CLKCTRL 0>;
3724 clock-names = "fck";
3725 #address-cells = <1>;
3726 #size-cells = <1>;
3727 ranges = <0x0 0x46000 0x1000>;
3729 mailbox8: mailbox@0 {
3730 compatible = "ti,omap4-mailbox";
3731 reg = <0x0 0x200>;
3732 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
3733 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
3734 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
3735 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
3736 #mbox-cells = <1>;
3737 ti,mbox-num-users = <4>;
3738 ti,mbox-num-fifos = <12>;
3739 status = "disabled";
3740 };
3741 };
3743 target-module@48000 { /* 0x48848000, ap 47 36.0 */
3744 compatible = "ti,sysc";
3745 status = "disabled";
3746 #address-cells = <1>;
3747 #size-cells = <1>;
3748 ranges = <0x0 0x48000 0x1000>;
3749 };
3751 target-module@4a000 { /* 0x4884a000, ap 49 38.0 */
3752 compatible = "ti,sysc";
3753 status = "disabled";
3754 #address-cells = <1>;
3755 #size-cells = <1>;
3756 ranges = <0x0 0x4a000 0x1000>;
3757 };
3759 target-module@4c000 { /* 0x4884c000, ap 51 44.0 */
3760 compatible = "ti,sysc";
3761 status = "disabled";
3762 #address-cells = <1>;
3763 #size-cells = <1>;
3764 ranges = <0x0 0x4c000 0x1000>;
3765 };
3767 target-module@4e000 { /* 0x4884e000, ap 53 4c.0 */
3768 compatible = "ti,sysc";
3769 status = "disabled";
3770 #address-cells = <1>;
3771 #size-cells = <1>;
3772 ranges = <0x0 0x4e000 0x1000>;
3773 };
3775 target-module@50000 { /* 0x48850000, ap 55 40.0 */
3776 compatible = "ti,sysc";
3777 status = "disabled";
3778 #address-cells = <1>;
3779 #size-cells = <1>;
3780 ranges = <0x0 0x50000 0x1000>;
3781 };
3783 target-module@52000 { /* 0x48852000, ap 57 54.0 */
3784 compatible = "ti,sysc";
3785 status = "disabled";
3786 #address-cells = <1>;
3787 #size-cells = <1>;
3788 ranges = <0x0 0x52000 0x1000>;
3789 };
3791 target-module@54000 { /* 0x48854000, ap 59 1a.0 */
3792 compatible = "ti,sysc";
3793 status = "disabled";
3794 #address-cells = <1>;
3795 #size-cells = <1>;
3796 ranges = <0x0 0x54000 0x1000>;
3797 };
3799 target-module@56000 { /* 0x48856000, ap 61 22.0 */
3800 compatible = "ti,sysc";
3801 status = "disabled";
3802 #address-cells = <1>;
3803 #size-cells = <1>;
3804 ranges = <0x0 0x56000 0x1000>;
3805 };
3807 target-module@58000 { /* 0x48858000, ap 63 2a.0 */
3808 compatible = "ti,sysc";
3809 status = "disabled";
3810 #address-cells = <1>;
3811 #size-cells = <1>;
3812 ranges = <0x0 0x58000 0x1000>;
3813 };
3815 target-module@5a000 { /* 0x4885a000, ap 65 5c.0 */
3816 compatible = "ti,sysc";
3817 status = "disabled";
3818 #address-cells = <1>;
3819 #size-cells = <1>;
3820 ranges = <0x0 0x5a000 0x1000>;
3821 };
3823 target-module@5c000 { /* 0x4885c000, ap 31 32.0 */
3824 compatible = "ti,sysc";
3825 status = "disabled";
3826 #address-cells = <1>;
3827 #size-cells = <1>;
3828 ranges = <0x0 0x5c000 0x1000>;
3829 };
3831 target-module@5e000 { /* 0x4885e000, ap 69 6c.0 */
3832 compatible = "ti,sysc-omap4", "ti,sysc";
3833 reg = <0x5e000 0x4>,
3834 <0x5e010 0x4>;
3835 reg-names = "rev", "sysc";
3836 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3837 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3838 <SYSC_IDLE_NO>,
3839 <SYSC_IDLE_SMART>;
3840 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3841 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX9_CLKCTRL 0>;
3842 clock-names = "fck";
3843 #address-cells = <1>;
3844 #size-cells = <1>;
3845 ranges = <0x0 0x5e000 0x1000>;
3847 mailbox9: mailbox@0 {
3848 compatible = "ti,omap4-mailbox";
3849 reg = <0x0 0x200>;
3850 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
3851 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
3852 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
3853 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3854 #mbox-cells = <1>;
3855 ti,mbox-num-users = <4>;
3856 ti,mbox-num-fifos = <12>;
3857 status = "disabled";
3858 };
3859 };
3861 target-module@60000 { /* 0x48860000, ap 71 4a.0 */
3862 compatible = "ti,sysc-omap4", "ti,sysc";
3863 reg = <0x60000 0x4>,
3864 <0x60010 0x4>;
3865 reg-names = "rev", "sysc";
3866 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3867 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3868 <SYSC_IDLE_NO>,
3869 <SYSC_IDLE_SMART>;
3870 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3871 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX10_CLKCTRL 0>;
3872 clock-names = "fck";
3873 #address-cells = <1>;
3874 #size-cells = <1>;
3875 ranges = <0x0 0x60000 0x1000>;
3877 mailbox10: mailbox@0 {
3878 compatible = "ti,omap4-mailbox";
3879 reg = <0x0 0x200>;
3880 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
3881 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
3882 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
3883 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
3884 #mbox-cells = <1>;
3885 ti,mbox-num-users = <4>;
3886 ti,mbox-num-fifos = <12>;
3887 status = "disabled";
3888 };
3889 };
3891 target-module@62000 { /* 0x48862000, ap 73 74.0 */
3892 compatible = "ti,sysc-omap4", "ti,sysc";
3893 reg = <0x62000 0x4>,
3894 <0x62010 0x4>;
3895 reg-names = "rev", "sysc";
3896 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3897 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3898 <SYSC_IDLE_NO>,
3899 <SYSC_IDLE_SMART>;
3900 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3901 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX11_CLKCTRL 0>;
3902 clock-names = "fck";
3903 #address-cells = <1>;
3904 #size-cells = <1>;
3905 ranges = <0x0 0x62000 0x1000>;
3907 mailbox11: mailbox@0 {
3908 compatible = "ti,omap4-mailbox";
3909 reg = <0x0 0x200>;
3910 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
3911 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
3912 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
3913 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
3914 #mbox-cells = <1>;
3915 ti,mbox-num-users = <4>;
3916 ti,mbox-num-fifos = <12>;
3917 status = "disabled";
3918 };
3919 };
3921 target-module@64000 { /* 0x48864000, ap 67 52.0 */
3922 compatible = "ti,sysc-omap4", "ti,sysc";
3923 reg = <0x64000 0x4>,
3924 <0x64010 0x4>;
3925 reg-names = "rev", "sysc";
3926 ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
3927 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3928 <SYSC_IDLE_NO>,
3929 <SYSC_IDLE_SMART>;
3930 /* Domains (P, C): core_pwrdm, l4cfg_clkdm */
3931 clocks = <&l4cfg_clkctrl DRA7_L4CFG_MAILBOX12_CLKCTRL 0>;
3932 clock-names = "fck";
3933 #address-cells = <1>;
3934 #size-cells = <1>;
3935 ranges = <0x0 0x64000 0x1000>;
3937 mailbox12: mailbox@0 {
3938 compatible = "ti,omap4-mailbox";
3939 reg = <0x0 0x200>;
3940 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
3941 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
3942 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
3943 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
3944 #mbox-cells = <1>;
3945 ti,mbox-num-users = <4>;
3946 ti,mbox-num-fifos = <12>;
3947 status = "disabled";
3948 };
3949 };
3951 target-module@80000 { /* 0x48880000, ap 83 0e.1 */
3952 compatible = "ti,sysc-omap4", "ti,sysc";
3953 reg = <0x80000 0x4>,
3954 <0x80010 0x4>;
3955 reg-names = "rev", "sysc";
3956 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
3957 ti,sysc-midle = <SYSC_IDLE_FORCE>,
3958 <SYSC_IDLE_NO>,
3959 <SYSC_IDLE_SMART>,
3960 <SYSC_IDLE_SMART_WKUP>;
3961 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
3962 <SYSC_IDLE_NO>,
3963 <SYSC_IDLE_SMART>,
3964 <SYSC_IDLE_SMART_WKUP>;
3965 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
3966 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS1_CLKCTRL 0>;
3967 clock-names = "fck";
3968 #address-cells = <1>;
3969 #size-cells = <1>;
3970 ranges = <0x0 0x80000 0x20000>;
3972 omap_dwc3_1: omap_dwc3_1@0 {
3973 compatible = "ti,dwc3";
3974 reg = <0x0 0x10000>;
3975 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3976 #address-cells = <1>;
3977 #size-cells = <1>;
3978 utmi-mode = <2>;
3979 ranges = <0 0 0x20000>;
3981 usb1: usb@10000 {
3982 compatible = "snps,dwc3";
3983 reg = <0x10000 0x17000>;
3984 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3985 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3986 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
3987 interrupt-names = "peripheral",
3988 "host",
3989 "otg";
3990 phys = <&usb2_phy1>, <&usb3_phy1>;
3991 phy-names = "usb2-phy", "usb3-phy";
3992 maximum-speed = "super-speed";
3993 dr_mode = "otg";
3994 snps,dis_u3_susphy_quirk;
3995 snps,dis_u2_susphy_quirk;
3996 };
3997 };
3998 };
4000 target-module@c0000 { /* 0x488c0000, ap 79 06.0 */
4001 compatible = "ti,sysc-omap4", "ti,sysc";
4002 reg = <0xc0000 0x4>,
4003 <0xc0010 0x4>;
4004 reg-names = "rev", "sysc";
4005 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4006 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4007 <SYSC_IDLE_NO>,
4008 <SYSC_IDLE_SMART>,
4009 <SYSC_IDLE_SMART_WKUP>;
4010 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4011 <SYSC_IDLE_NO>,
4012 <SYSC_IDLE_SMART>,
4013 <SYSC_IDLE_SMART_WKUP>;
4014 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4015 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS2_CLKCTRL 0>;
4016 clock-names = "fck";
4017 #address-cells = <1>;
4018 #size-cells = <1>;
4019 ranges = <0x0 0xc0000 0x20000>;
4021 omap_dwc3_2: omap_dwc3_2@0 {
4022 compatible = "ti,dwc3";
4023 reg = <0x0 0x10000>;
4024 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4025 #address-cells = <1>;
4026 #size-cells = <1>;
4027 utmi-mode = <2>;
4028 ranges = <0 0 0x20000>;
4030 usb2: usb@10000 {
4031 compatible = "snps,dwc3";
4032 reg = <0x10000 0x17000>;
4033 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4034 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
4035 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
4036 interrupt-names = "peripheral",
4037 "host",
4038 "otg";
4039 phys = <&usb2_phy2>;
4040 phy-names = "usb2-phy";
4041 maximum-speed = "high-speed";
4042 dr_mode = "otg";
4043 snps,dis_u3_susphy_quirk;
4044 snps,dis_u2_susphy_quirk;
4045 snps,dis_metastability_quirk;
4046 };
4047 };
4048 };
4050 usb3_tm: target-module@100000 { /* 0x48900000, ap 85 04.0 */
4051 compatible = "ti,sysc-omap4", "ti,sysc";
4052 reg = <0x100000 0x4>,
4053 <0x100010 0x4>;
4054 reg-names = "rev", "sysc";
4055 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4056 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4057 <SYSC_IDLE_NO>,
4058 <SYSC_IDLE_SMART>,
4059 <SYSC_IDLE_SMART_WKUP>;
4060 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4061 <SYSC_IDLE_NO>,
4062 <SYSC_IDLE_SMART>,
4063 <SYSC_IDLE_SMART_WKUP>;
4064 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4065 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS3_CLKCTRL 0>;
4066 clock-names = "fck";
4067 #address-cells = <1>;
4068 #size-cells = <1>;
4069 ranges = <0x0 0x100000 0x20000>;
4071 omap_dwc3_3: omap_dwc3_3@0 {
4072 compatible = "ti,dwc3";
4073 reg = <0x0 0x10000>;
4074 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4075 #address-cells = <1>;
4076 #size-cells = <1>;
4077 utmi-mode = <2>;
4078 ranges = <0 0 0x20000>;
4079 status = "disabled";
4081 usb3: usb@10000 {
4082 compatible = "snps,dwc3";
4083 reg = <0x10000 0x17000>;
4084 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4085 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
4086 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
4087 interrupt-names = "peripheral",
4088 "host",
4089 "otg";
4090 maximum-speed = "high-speed";
4091 dr_mode = "otg";
4092 snps,dis_u3_susphy_quirk;
4093 snps,dis_u2_susphy_quirk;
4094 };
4095 };
4096 };
4098 usb4_tm: target-module@140000 { /* 0x48940000, ap 75 3c.0 */
4099 compatible = "ti,sysc-omap4", "ti,sysc";
4100 reg = <0x140000 0x4>,
4101 <0x140010 0x4>;
4102 reg-names = "rev", "sysc";
4103 ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
4104 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4105 <SYSC_IDLE_NO>,
4106 <SYSC_IDLE_SMART>,
4107 <SYSC_IDLE_SMART_WKUP>;
4108 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4109 <SYSC_IDLE_NO>,
4110 <SYSC_IDLE_SMART>,
4111 <SYSC_IDLE_SMART_WKUP>;
4112 /* Domains (P, C): l3init_pwrdm, l3init_clkdm */
4113 clocks = <&l3init_clkctrl DRA7_L3INIT_USB_OTG_SS4_CLKCTRL 0>;
4114 clock-names = "fck";
4115 #address-cells = <1>;
4116 #size-cells = <1>;
4117 ranges = <0x0 0x140000 0x20000>;
4118 };
4120 target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4121 compatible = "ti,sysc-omap4", "ti,sysc";
4122 reg = <0x170010 0x4>;
4123 reg-names = "sysc";
4124 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4125 <SYSC_IDLE_NO>,
4126 <SYSC_IDLE_SMART>;
4127 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4128 <SYSC_IDLE_NO>,
4129 <SYSC_IDLE_SMART>;
4130 clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4131 clock-names = "fck";
4132 #address-cells = <1>;
4133 #size-cells = <1>;
4134 ranges = <0x0 0x170000 0x10000>;
4135 status = "disabled";
4136 };
4138 target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4139 compatible = "ti,sysc-omap4", "ti,sysc";
4140 reg = <0x190010 0x4>;
4141 reg-names = "sysc";
4142 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4143 <SYSC_IDLE_NO>,
4144 <SYSC_IDLE_SMART>;
4145 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4146 <SYSC_IDLE_NO>,
4147 <SYSC_IDLE_SMART>;
4148 clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4149 clock-names = "fck";
4150 #address-cells = <1>;
4151 #size-cells = <1>;
4152 ranges = <0x0 0x190000 0x10000>;
4153 status = "disabled";
4154 };
4156 target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4157 compatible = "ti,sysc-omap4", "ti,sysc";
4158 reg = <0x1b0000 0x4>,
4159 <0x1b0010 0x4>;
4160 reg-names = "rev", "sysc";
4161 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4162 <SYSC_IDLE_NO>,
4163 <SYSC_IDLE_SMART>;
4164 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4165 <SYSC_IDLE_NO>,
4166 <SYSC_IDLE_SMART>;
4167 clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4168 clock-names = "fck";
4169 #address-cells = <1>;
4170 #size-cells = <1>;
4171 ranges = <0x0 0x1b0000 0x10000>;
4172 status = "disabled";
4173 };
4175 target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
4176 compatible = "ti,sysc-omap4", "ti,sysc";
4177 reg = <0x1d0010 0x4>;
4178 reg-names = "sysc";
4179 ti,sysc-midle = <SYSC_IDLE_FORCE>,
4180 <SYSC_IDLE_NO>,
4181 <SYSC_IDLE_SMART>;
4182 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4183 <SYSC_IDLE_NO>,
4184 <SYSC_IDLE_SMART>;
4185 clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4186 clock-names = "fck";
4187 #address-cells = <1>;
4188 #size-cells = <1>;
4189 ranges = <0x0 0x1d0000 0x10000>;
4191 vpe: vpe@0 {
4192 compatible = "ti,dra7-vpe";
4193 reg = <0x0000 0x120>,
4194 <0x0700 0x80>,
4195 <0x5700 0x18>,
4196 <0xd000 0x400>;
4197 reg-names = "vpe_top",
4198 "sc",
4199 "csc",
4200 "vpdma";
4201 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
4202 };
4203 };
4204 };
4205 };
4207 &l4_wkup { /* 0x4ae00000 */
4208 compatible = "ti,dra7-l4-wkup", "simple-bus";
4209 reg = <0x4ae00000 0x800>,
4210 <0x4ae00800 0x800>,
4211 <0x4ae01000 0x1000>;
4212 reg-names = "ap", "la", "ia0";
4213 #address-cells = <1>;
4214 #size-cells = <1>;
4215 ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
4216 <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
4217 <0x00020000 0x4ae20000 0x010000>, /* segment 2 */
4218 <0x00030000 0x4ae30000 0x010000>; /* segment 3 */
4220 segment@0 { /* 0x4ae00000 */
4221 compatible = "simple-bus";
4222 #address-cells = <1>;
4223 #size-cells = <1>;
4224 ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
4225 <0x00001000 0x00001000 0x001000>, /* ap 1 */
4226 <0x00000800 0x00000800 0x000800>, /* ap 2 */
4227 <0x00006000 0x00006000 0x002000>, /* ap 3 */
4228 <0x00008000 0x00008000 0x001000>, /* ap 4 */
4229 <0x00004000 0x00004000 0x001000>, /* ap 15 */
4230 <0x00005000 0x00005000 0x001000>, /* ap 16 */
4231 <0x0000c000 0x0000c000 0x001000>, /* ap 17 */
4232 <0x0000d000 0x0000d000 0x001000>; /* ap 18 */
4234 target-module@4000 { /* 0x4ae04000, ap 15 40.0 */
4235 compatible = "ti,sysc-omap2", "ti,sysc";
4236 reg = <0x4000 0x4>,
4237 <0x4010 0x4>;
4238 reg-names = "rev", "sysc";
4239 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4240 <SYSC_IDLE_NO>,
4241 <SYSC_IDLE_SMART>,
4242 <SYSC_IDLE_SMART_WKUP>;
4243 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4244 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_COUNTER_32K_CLKCTRL 0>;
4245 clock-names = "fck";
4246 #address-cells = <1>;
4247 #size-cells = <1>;
4248 ranges = <0x0 0x4000 0x1000>;
4250 counter32k: counter@0 {
4251 compatible = "ti,omap-counter32k";
4252 reg = <0x0 0x40>;
4253 };
4254 };
4256 target-module@6000 { /* 0x4ae06000, ap 3 10.0 */
4257 compatible = "ti,sysc-omap4", "ti,sysc";
4258 reg = <0x6000 0x4>;
4259 reg-names = "rev";
4260 #address-cells = <1>;
4261 #size-cells = <1>;
4262 ranges = <0x0 0x6000 0x2000>;
4264 prm: prm@0 {
4265 compatible = "ti,dra7-prm", "simple-bus";
4266 reg = <0 0x3000>;
4267 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
4268 #address-cells = <1>;
4269 #size-cells = <1>;
4270 ranges = <0 0 0x3000>;
4272 prm_clocks: clocks {
4273 #address-cells = <1>;
4274 #size-cells = <0>;
4275 };
4277 prm_clockdomains: clockdomains {
4278 };
4279 };
4280 };
4282 target-module@c000 { /* 0x4ae0c000, ap 17 50.0 */
4283 compatible = "ti,sysc-omap4", "ti,sysc";
4284 reg = <0xc000 0x4>;
4285 reg-names = "rev";
4286 #address-cells = <1>;
4287 #size-cells = <1>;
4288 ranges = <0x0 0xc000 0x1000>;
4290 scm_wkup: scm_conf@0 {
4291 compatible = "syscon";
4292 reg = <0 0x1000>;
4293 };
4294 };
4295 };
4297 segment@10000 { /* 0x4ae10000 */
4298 compatible = "simple-bus";
4299 #address-cells = <1>;
4300 #size-cells = <1>;
4301 ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
4302 <0x00001000 0x00011000 0x001000>, /* ap 6 */
4303 <0x00004000 0x00014000 0x001000>, /* ap 7 */
4304 <0x00005000 0x00015000 0x001000>, /* ap 8 */
4305 <0x00008000 0x00018000 0x001000>, /* ap 9 */
4306 <0x00009000 0x00019000 0x001000>, /* ap 10 */
4307 <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
4308 <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
4310 target-module@0 { /* 0x4ae10000, ap 5 20.0 */
4311 compatible = "ti,sysc-omap2", "ti,sysc";
4312 reg = <0x0 0x4>,
4313 <0x10 0x4>,
4314 <0x114 0x4>;
4315 reg-names = "rev", "sysc", "syss";
4316 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4317 SYSC_OMAP2_SOFTRESET |
4318 SYSC_OMAP2_AUTOIDLE)>;
4319 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4320 <SYSC_IDLE_NO>,
4321 <SYSC_IDLE_SMART>,
4322 <SYSC_IDLE_SMART_WKUP>;
4323 ti,syss-mask = <1>;
4324 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4325 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 0>,
4326 <&wkupaon_clkctrl DRA7_WKUPAON_GPIO1_CLKCTRL 8>;
4327 clock-names = "fck", "dbclk";
4328 #address-cells = <1>;
4329 #size-cells = <1>;
4330 ranges = <0x0 0x0 0x1000>;
4332 gpio1: gpio@0 {
4333 compatible = "ti,omap4-gpio";
4334 reg = <0x0 0x200>;
4335 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
4336 gpio-controller;
4337 #gpio-cells = <2>;
4338 interrupt-controller;
4339 #interrupt-cells = <2>;
4340 };
4341 };
4343 target-module@4000 { /* 0x4ae14000, ap 7 28.0 */
4344 compatible = "ti,sysc-omap2", "ti,sysc";
4345 reg = <0x4000 0x4>,
4346 <0x4010 0x4>,
4347 <0x4014 0x4>;
4348 reg-names = "rev", "sysc", "syss";
4349 ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
4350 SYSC_OMAP2_SOFTRESET)>;
4351 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4352 <SYSC_IDLE_NO>,
4353 <SYSC_IDLE_SMART>,
4354 <SYSC_IDLE_SMART_WKUP>;
4355 ti,syss-mask = <1>;
4356 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4357 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_WD_TIMER2_CLKCTRL 0>;
4358 clock-names = "fck";
4359 #address-cells = <1>;
4360 #size-cells = <1>;
4361 ranges = <0x0 0x4000 0x1000>;
4363 wdt2: wdt@0 {
4364 compatible = "ti,omap3-wdt";
4365 reg = <0x0 0x80>;
4366 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
4367 };
4368 };
4370 timer1_target: target-module@8000 { /* 0x4ae18000, ap 9 30.0 */
4371 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4372 reg = <0x8000 0x4>,
4373 <0x8010 0x4>;
4374 reg-names = "rev", "sysc";
4375 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4376 SYSC_OMAP4_SOFTRESET)>;
4377 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4378 <SYSC_IDLE_NO>,
4379 <SYSC_IDLE_SMART>,
4380 <SYSC_IDLE_SMART_WKUP>;
4381 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4382 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 0>;
4383 clock-names = "fck";
4384 #address-cells = <1>;
4385 #size-cells = <1>;
4386 ranges = <0x0 0x8000 0x1000>;
4388 timer1: timer@0 {
4389 compatible = "ti,omap5430-timer";
4390 reg = <0x0 0x80>;
4391 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER1_CLKCTRL 24>;
4392 clock-names = "fck";
4393 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
4394 ti,timer-alwon;
4395 };
4396 };
4398 target-module@c000 { /* 0x4ae1c000, ap 11 38.0 */
4399 compatible = "ti,sysc";
4400 status = "disabled";
4401 #address-cells = <1>;
4402 #size-cells = <1>;
4403 ranges = <0x0 0xc000 0x1000>;
4404 };
4405 };
4407 segment@20000 { /* 0x4ae20000 */
4408 compatible = "simple-bus";
4409 #address-cells = <1>;
4410 #size-cells = <1>;
4411 ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
4412 <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
4413 <0x00000000 0x00020000 0x001000>, /* ap 19 */
4414 <0x00001000 0x00021000 0x001000>, /* ap 20 */
4415 <0x00002000 0x00022000 0x001000>, /* ap 21 */
4416 <0x00003000 0x00023000 0x001000>, /* ap 22 */
4417 <0x00007000 0x00027000 0x000400>, /* ap 23 */
4418 <0x00008000 0x00028000 0x000800>, /* ap 24 */
4419 <0x00009000 0x00029000 0x000100>, /* ap 25 */
4420 <0x00008800 0x00028800 0x000200>, /* ap 26 */
4421 <0x00008a00 0x00028a00 0x000100>, /* ap 27 */
4422 <0x0000b000 0x0002b000 0x001000>, /* ap 28 */
4423 <0x0000c000 0x0002c000 0x001000>, /* ap 29 */
4424 <0x0000f000 0x0002f000 0x001000>; /* ap 32 */
4426 target-module@0 { /* 0x4ae20000, ap 19 08.0 */
4427 compatible = "ti,sysc-omap4-timer", "ti,sysc";
4428 reg = <0x0 0x4>,
4429 <0x10 0x4>;
4430 reg-names = "rev", "sysc";
4431 ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
4432 SYSC_OMAP4_SOFTRESET)>;
4433 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4434 <SYSC_IDLE_NO>,
4435 <SYSC_IDLE_SMART>,
4436 <SYSC_IDLE_SMART_WKUP>;
4437 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4438 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_TIMER12_CLKCTRL 0>;
4439 clock-names = "fck";
4440 #address-cells = <1>;
4441 #size-cells = <1>;
4442 ranges = <0x0 0x0 0x1000>;
4444 timer12: timer@0 {
4445 compatible = "ti,omap5430-timer";
4446 reg = <0x0 0x80>;
4447 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
4448 ti,timer-alwon;
4449 ti,timer-secure;
4450 };
4451 };
4453 target-module@2000 { /* 0x4ae22000, ap 21 18.0 */
4454 compatible = "ti,sysc";
4455 status = "disabled";
4456 #address-cells = <1>;
4457 #size-cells = <1>;
4458 ranges = <0x0 0x2000 0x1000>;
4459 };
4461 target-module@6000 { /* 0x4ae26000, ap 13 48.0 */
4462 compatible = "ti,sysc";
4463 status = "disabled";
4464 #address-cells = <1>;
4465 #size-cells = <1>;
4466 ranges = <0x00000000 0x00006000 0x00001000>,
4467 <0x00001000 0x00007000 0x00000400>,
4468 <0x00002000 0x00008000 0x00000800>,
4469 <0x00002800 0x00008800 0x00000200>,
4470 <0x00002a00 0x00008a00 0x00000100>,
4471 <0x00003000 0x00009000 0x00000100>;
4472 };
4474 target-module@b000 { /* 0x4ae2b000, ap 28 02.0 */
4475 compatible = "ti,sysc-omap2", "ti,sysc";
4476 reg = <0xb050 0x4>,
4477 <0xb054 0x4>,
4478 <0xb058 0x4>;
4479 reg-names = "rev", "sysc", "syss";
4480 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
4481 SYSC_OMAP2_SOFTRESET |
4482 SYSC_OMAP2_AUTOIDLE)>;
4483 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4484 <SYSC_IDLE_NO>,
4485 <SYSC_IDLE_SMART>,
4486 <SYSC_IDLE_SMART_WKUP>;
4487 ti,syss-mask = <1>;
4488 /* Domains (P, C): wkupaon_pwrdm, wkupaon_clkdm */
4489 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_UART10_CLKCTRL 0>;
4490 clock-names = "fck";
4491 #address-cells = <1>;
4492 #size-cells = <1>;
4493 ranges = <0x0 0xb000 0x1000>;
4495 uart10: serial@0 {
4496 compatible = "ti,dra742-uart", "ti,omap4-uart";
4497 reg = <0x0 0x100>;
4498 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
4499 clock-frequency = <48000000>;
4500 status = "disabled";
4501 };
4502 };
4504 target-module@f000 { /* 0x4ae2f000, ap 32 58.0 */
4505 compatible = "ti,sysc";
4506 status = "disabled";
4507 #address-cells = <1>;
4508 #size-cells = <1>;
4509 ranges = <0x0 0xf000 0x1000>;
4510 };
4511 };
4513 segment@30000 { /* 0x4ae30000 */
4514 compatible = "simple-bus";
4515 #address-cells = <1>;
4516 #size-cells = <1>;
4517 ranges = <0x0000c000 0x0003c000 0x002000>, /* ap 30 */
4518 <0x0000e000 0x0003e000 0x001000>, /* ap 31 */
4519 <0x00000000 0x00030000 0x001000>, /* ap 33 */
4520 <0x00001000 0x00031000 0x001000>, /* ap 34 */
4521 <0x00002000 0x00032000 0x001000>, /* ap 35 */
4522 <0x00003000 0x00033000 0x001000>, /* ap 36 */
4523 <0x00004000 0x00034000 0x001000>, /* ap 37 */
4524 <0x00005000 0x00035000 0x001000>, /* ap 38 */
4525 <0x00006000 0x00036000 0x001000>, /* ap 39 */
4526 <0x00007000 0x00037000 0x001000>, /* ap 40 */
4527 <0x00008000 0x00038000 0x001000>, /* ap 41 */
4528 <0x00009000 0x00039000 0x001000>, /* ap 42 */
4529 <0x0000a000 0x0003a000 0x001000>; /* ap 43 */
4531 target-module@1000 { /* 0x4ae31000, ap 34 60.0 */
4532 compatible = "ti,sysc";
4533 status = "disabled";
4534 #address-cells = <1>;
4535 #size-cells = <1>;
4536 ranges = <0x0 0x1000 0x1000>;
4537 };
4539 target-module@3000 { /* 0x4ae33000, ap 36 0a.0 */
4540 compatible = "ti,sysc";
4541 status = "disabled";
4542 #address-cells = <1>;
4543 #size-cells = <1>;
4544 ranges = <0x0 0x3000 0x1000>;
4545 };
4547 target-module@5000 { /* 0x4ae35000, ap 38 0c.0 */
4548 compatible = "ti,sysc";
4549 status = "disabled";
4550 #address-cells = <1>;
4551 #size-cells = <1>;
4552 ranges = <0x0 0x5000 0x1000>;
4553 };
4555 target-module@7000 { /* 0x4ae37000, ap 40 68.0 */
4556 compatible = "ti,sysc";
4557 status = "disabled";
4558 #address-cells = <1>;
4559 #size-cells = <1>;
4560 ranges = <0x0 0x7000 0x1000>;
4561 };
4563 target-module@9000 { /* 0x4ae39000, ap 42 70.0 */
4564 compatible = "ti,sysc";
4565 status = "disabled";
4566 #address-cells = <1>;
4567 #size-cells = <1>;
4568 ranges = <0x0 0x9000 0x1000>;
4569 };
4571 target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
4572 compatible = "ti,sysc-omap4", "ti,sysc";
4573 reg = <0xc020 0x4>;
4574 reg-names = "rev";
4575 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
4576 clock-names = "fck";
4577 #address-cells = <1>;
4578 #size-cells = <1>;
4579 ranges = <0x0 0xc000 0x2000>;
4581 dcan1: can@0 {
4582 compatible = "ti,dra7-d_can";
4583 reg = <0x0 0x2000>;
4584 syscon-raminit = <&scm_conf 0x558 0>;
4585 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
4586 clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 24>;
4587 status = "disabled";
4588 };
4589 };
4590 };
4591 };