| blob | ce1194744f84025210f5c706e412e10b1267abd0 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
12 #include <dt-bindings/clock/dra7.h>
14 #define MAX_SOURCES 400
16 / {
17 #address-cells = <2>;
18 #size-cells = <2>;
20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>;
22 chosen { };
24 aliases {
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
40 ethernet0 = &cpsw_port1;
41 ethernet1 = &cpsw_port2;
42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
44 spi0 = &qspi;
45 };
47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 interrupt-parent = <&gic>;
54 };
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 interrupt-parent = <&gic>;
66 };
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
73 interrupt-parent = <&gic>;
74 };
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
80 cpu0: cpu@0 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a15";
83 reg = <0>;
85 operating-points-v2 = <&cpu0_opp_table>;
87 clocks = <&dpll_mpu_ck>;
88 clock-names = "cpu";
90 clock-latency = <300000>; /* From omap-cpufreq driver */
92 /* cooling options */
93 #cooling-cells = <2>; /* min followed by max */
95 vbb-supply = <&abb_mpu>;
96 };
97 };
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
101 syscon = <&scm_wkup>;
103 opp_nom-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <1060000 850000 1150000>,
106 <1060000 850000 1150000>;
107 opp-supported-hw = <0xFF 0x01>;
108 opp-suspend;
109 };
111 opp_od-1176000000 {
112 opp-hz = /bits/ 64 <1176000000>;
113 opp-microvolt = <1160000 885000 1160000>,
114 <1160000 885000 1160000>;
116 opp-supported-hw = <0xFF 0x02>;
117 };
119 opp_high@1500000000 {
120 opp-hz = /bits/ 64 <1500000000>;
121 opp-microvolt = <1210000 950000 1250000>,
122 <1210000 950000 1250000>;
123 opp-supported-hw = <0xFF 0x04>;
124 };
125 };
127 /*
128 * The soc node represents the soc top level view. It is used for IPs
129 * that are not memory mapped in the MPU view or for the MPU itself.
130 */
131 soc {
132 compatible = "ti,omap-infra";
133 mpu {
134 compatible = "ti,omap5-mpu";
135 ti,hwmods = "mpu";
136 };
137 };
139 /*
140 * XXX: Use a flat representation of the SOC interconnect.
141 * The real OMAP interconnect network is quite complex.
142 * Since it will not bring real advantage to represent that in DT for
143 * the moment, just use a fake OCP bus entry to represent the whole bus
144 * hierarchy.
145 */
146 ocp: ocp {
147 compatible = "ti,dra7-l3-noc", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x0 0x0 0xc0000000>;
151 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
152 ti,hwmods = "l3_main_1", "l3_main_2";
153 reg = <0x0 0x44000000 0x0 0x1000000>,
154 <0x0 0x45000000 0x0 0x1000>;
155 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
156 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
158 l4_cfg: interconnect@4a000000 {
159 };
160 l4_wkup: interconnect@4ae00000 {
161 };
162 l4_per1: interconnect@48000000 {
163 };
164 l4_per2: interconnect@48400000 {
165 };
166 l4_per3: interconnect@48800000 {
167 };
169 axi@0 {
170 compatible = "simple-bus";
171 #size-cells = <1>;
172 #address-cells = <1>;
173 ranges = <0x51000000 0x51000000 0x3000
174 0x0 0x20000000 0x10000000>;
175 dma-ranges;
176 /**
177 * To enable PCI endpoint mode, disable the pcie1_rc
178 * node and enable pcie1_ep mode.
179 */
180 pcie1_rc: pcie@51000000 {
181 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
182 reg-names = "rc_dbics", "ti_conf", "config";
183 interrupts = <0 232 0x4>, <0 233 0x4>;
184 #address-cells = <3>;
185 #size-cells = <2>;
186 device_type = "pci";
187 ranges = <0x81000000 0 0 0x03000 0 0x00010000
188 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
189 bus-range = <0x00 0xff>;
190 #interrupt-cells = <1>;
191 num-lanes = <1>;
192 linux,pci-domain = <0>;
193 ti,hwmods = "pcie1";
194 phys = <&pcie1_phy>;
195 phy-names = "pcie-phy0";
196 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
197 interrupt-map-mask = <0 0 0 7>;
198 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
199 <0 0 0 2 &pcie1_intc 2>,
200 <0 0 0 3 &pcie1_intc 3>,
201 <0 0 0 4 &pcie1_intc 4>;
202 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
203 status = "disabled";
204 pcie1_intc: interrupt-controller {
205 interrupt-controller;
206 #address-cells = <0>;
207 #interrupt-cells = <1>;
208 };
209 };
211 pcie1_ep: pcie_ep@51000000 {
212 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
213 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
214 interrupts = <0 232 0x4>;
215 num-lanes = <1>;
216 num-ib-windows = <4>;
217 num-ob-windows = <16>;
218 ti,hwmods = "pcie1";
219 phys = <&pcie1_phy>;
220 phy-names = "pcie-phy0";
221 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
222 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
223 status = "disabled";
224 };
225 };
227 axi@1 {
228 compatible = "simple-bus";
229 #size-cells = <1>;
230 #address-cells = <1>;
231 ranges = <0x51800000 0x51800000 0x3000
232 0x0 0x30000000 0x10000000>;
233 dma-ranges;
234 status = "disabled";
235 pcie2_rc: pcie@51800000 {
236 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
237 reg-names = "rc_dbics", "ti_conf", "config";
238 interrupts = <0 355 0x4>, <0 356 0x4>;
239 #address-cells = <3>;
240 #size-cells = <2>;
241 device_type = "pci";
242 ranges = <0x81000000 0 0 0x03000 0 0x00010000
243 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
244 bus-range = <0x00 0xff>;
245 #interrupt-cells = <1>;
246 num-lanes = <1>;
247 linux,pci-domain = <1>;
248 ti,hwmods = "pcie2";
249 phys = <&pcie2_phy>;
250 phy-names = "pcie-phy0";
251 interrupt-map-mask = <0 0 0 7>;
252 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
253 <0 0 0 2 &pcie2_intc 2>,
254 <0 0 0 3 &pcie2_intc 3>,
255 <0 0 0 4 &pcie2_intc 4>;
256 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
257 pcie2_intc: interrupt-controller {
258 interrupt-controller;
259 #address-cells = <0>;
260 #interrupt-cells = <1>;
261 };
262 };
263 };
265 ocmcram1: ocmcram@40300000 {
266 compatible = "mmio-sram";
267 reg = <0x40300000 0x80000>;
268 ranges = <0x0 0x40300000 0x80000>;
269 #address-cells = <1>;
270 #size-cells = <1>;
271 /*
272 * This is a placeholder for an optional reserved
273 * region for use by secure software. The size
274 * of this region is not known until runtime so it
275 * is set as zero to either be updated to reserve
276 * space or left unchanged to leave all SRAM for use.
277 * On HS parts that that require the reserved region
278 * either the bootloader can update the size to
279 * the required amount or the node can be overridden
280 * from the board dts file for the secure platform.
281 */
282 sram-hs@0 {
283 compatible = "ti,secure-ram";
284 reg = <0x0 0x0>;
285 };
286 };
288 /*
289 * NOTE: ocmcram2 and ocmcram3 are not available on all
290 * DRA7xx and AM57xx variants. Confirm availability in
291 * the data manual for the exact part number in use
292 * before enabling these nodes in the board dts file.
293 */
294 ocmcram2: ocmcram@40400000 {
295 status = "disabled";
296 compatible = "mmio-sram";
297 reg = <0x40400000 0x100000>;
298 ranges = <0x0 0x40400000 0x100000>;
299 #address-cells = <1>;
300 #size-cells = <1>;
301 };
303 ocmcram3: ocmcram@40500000 {
304 status = "disabled";
305 compatible = "mmio-sram";
306 reg = <0x40500000 0x100000>;
307 ranges = <0x0 0x40500000 0x100000>;
308 #address-cells = <1>;
309 #size-cells = <1>;
310 };
312 bandgap: bandgap@4a0021e0 {
313 reg = <0x4a0021e0 0xc
314 0x4a00232c 0xc
315 0x4a002380 0x2c
316 0x4a0023C0 0x3c
317 0x4a002564 0x8
318 0x4a002574 0x50>;
319 compatible = "ti,dra752-bandgap";
320 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
321 #thermal-sensor-cells = <1>;
322 };
324 dsp1_system: dsp_system@40d00000 {
325 compatible = "syscon";
326 reg = <0x40d00000 0x100>;
327 };
329 dra7_iodelay_core: padconf@4844a000 {
330 compatible = "ti,dra7-iodelay";
331 reg = <0x4844a000 0x0d1c>;
332 #address-cells = <1>;
333 #size-cells = <0>;
334 #pinctrl-cells = <2>;
335 };
337 target-module@43300000 {
338 compatible = "ti,sysc-omap4", "ti,sysc";
339 reg = <0x43300000 0x4>;
340 reg-names = "rev";
341 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
342 clock-names = "fck";
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges = <0x0 0x43300000 0x100000>;
347 edma: dma@0 {
348 compatible = "ti,edma3-tpcc";
349 reg = <0 0x100000>;
350 reg-names = "edma3_cc";
351 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
354 interrupt-names = "edma3_ccint", "edma3_mperr",
355 "edma3_ccerrint";
356 dma-requests = <64>;
357 #dma-cells = <2>;
359 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
361 /*
362 * memcpy is disabled, can be enabled with:
363 * ti,edma-memcpy-channels = <20 21>;
364 * for example. Note that these channels need to be
365 * masked in the xbar as well.
366 */
367 };
368 };
370 target-module@43400000 {
371 compatible = "ti,sysc-omap4", "ti,sysc";
372 reg = <0x43400000 0x4>;
373 reg-names = "rev";
374 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
375 clock-names = "fck";
376 #address-cells = <1>;
377 #size-cells = <1>;
378 ranges = <0x0 0x43400000 0x100000>;
380 edma_tptc0: dma@0 {
381 compatible = "ti,edma3-tptc";
382 reg = <0 0x100000>;
383 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
384 interrupt-names = "edma3_tcerrint";
385 };
386 };
388 target-module@43500000 {
389 compatible = "ti,sysc-omap4", "ti,sysc";
390 reg = <0x43500000 0x4>;
391 reg-names = "rev";
392 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
393 clock-names = "fck";
394 #address-cells = <1>;
395 #size-cells = <1>;
396 ranges = <0x0 0x43500000 0x100000>;
398 edma_tptc1: dma@0 {
399 compatible = "ti,edma3-tptc";
400 reg = <0 0x100000>;
401 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
402 interrupt-names = "edma3_tcerrint";
403 };
404 };
406 dmm@4e000000 {
407 compatible = "ti,omap5-dmm";
408 reg = <0x4e000000 0x800>;
409 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
410 ti,hwmods = "dmm";
411 };
413 ipu1: ipu@58820000 {
414 compatible = "ti,dra7-ipu";
415 reg = <0x58820000 0x10000>;
416 reg-names = "l2ram";
417 iommus = <&mmu_ipu1>;
418 status = "disabled";
419 resets = <&prm_ipu 0>, <&prm_ipu 1>;
420 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
421 firmware-name = "dra7-ipu1-fw.xem4";
422 };
424 ipu2: ipu@55020000 {
425 compatible = "ti,dra7-ipu";
426 reg = <0x55020000 0x10000>;
427 reg-names = "l2ram";
428 iommus = <&mmu_ipu2>;
429 status = "disabled";
430 resets = <&prm_core 0>, <&prm_core 1>;
431 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
432 firmware-name = "dra7-ipu2-fw.xem4";
433 };
435 dsp1: dsp@40800000 {
436 compatible = "ti,dra7-dsp";
437 reg = <0x40800000 0x48000>,
438 <0x40e00000 0x8000>,
439 <0x40f00000 0x8000>;
440 reg-names = "l2ram", "l1pram", "l1dram";
441 ti,bootreg = <&scm_conf 0x55c 10>;
442 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
443 status = "disabled";
444 resets = <&prm_dsp1 0>;
445 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
446 firmware-name = "dra7-dsp1-fw.xe66";
447 };
449 target-module@40d01000 {
450 compatible = "ti,sysc-omap2", "ti,sysc";
451 reg = <0x40d01000 0x4>,
452 <0x40d01010 0x4>,
453 <0x40d01014 0x4>;
454 reg-names = "rev", "sysc", "syss";
455 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
456 <SYSC_IDLE_NO>,
457 <SYSC_IDLE_SMART>;
458 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
459 SYSC_OMAP2_SOFTRESET |
460 SYSC_OMAP2_AUTOIDLE)>;
461 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
462 clock-names = "fck";
463 resets = <&prm_dsp1 1>;
464 reset-names = "rstctrl";
465 ranges = <0x0 0x40d01000 0x1000>;
466 #size-cells = <1>;
467 #address-cells = <1>;
469 mmu0_dsp1: mmu@0 {
470 compatible = "ti,dra7-dsp-iommu";
471 reg = <0x0 0x100>;
472 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
473 #iommu-cells = <0>;
474 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
475 };
476 };
478 target-module@40d02000 {
479 compatible = "ti,sysc-omap2", "ti,sysc";
480 reg = <0x40d02000 0x4>,
481 <0x40d02010 0x4>,
482 <0x40d02014 0x4>;
483 reg-names = "rev", "sysc", "syss";
484 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
485 <SYSC_IDLE_NO>,
486 <SYSC_IDLE_SMART>;
487 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
488 SYSC_OMAP2_SOFTRESET |
489 SYSC_OMAP2_AUTOIDLE)>;
490 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
491 clock-names = "fck";
492 resets = <&prm_dsp1 1>;
493 reset-names = "rstctrl";
494 ranges = <0x0 0x40d02000 0x1000>;
495 #size-cells = <1>;
496 #address-cells = <1>;
498 mmu1_dsp1: mmu@0 {
499 compatible = "ti,dra7-dsp-iommu";
500 reg = <0x0 0x100>;
501 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
502 #iommu-cells = <0>;
503 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
504 };
505 };
507 target-module@58882000 {
508 compatible = "ti,sysc-omap2", "ti,sysc";
509 reg = <0x58882000 0x4>,
510 <0x58882010 0x4>,
511 <0x58882014 0x4>;
512 reg-names = "rev", "sysc", "syss";
513 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
514 <SYSC_IDLE_NO>,
515 <SYSC_IDLE_SMART>;
516 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
517 SYSC_OMAP2_SOFTRESET |
518 SYSC_OMAP2_AUTOIDLE)>;
519 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
520 clock-names = "fck";
521 resets = <&prm_ipu 2>;
522 reset-names = "rstctrl";
523 #address-cells = <1>;
524 #size-cells = <1>;
525 ranges = <0x0 0x58882000 0x100>;
527 mmu_ipu1: mmu@0 {
528 compatible = "ti,dra7-iommu";
529 reg = <0x0 0x100>;
530 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
531 #iommu-cells = <0>;
532 ti,iommu-bus-err-back;
533 };
534 };
536 target-module@55082000 {
537 compatible = "ti,sysc-omap2", "ti,sysc";
538 reg = <0x55082000 0x4>,
539 <0x55082010 0x4>,
540 <0x55082014 0x4>;
541 reg-names = "rev", "sysc", "syss";
542 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
543 <SYSC_IDLE_NO>,
544 <SYSC_IDLE_SMART>;
545 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
546 SYSC_OMAP2_SOFTRESET |
547 SYSC_OMAP2_AUTOIDLE)>;
548 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
549 clock-names = "fck";
550 resets = <&prm_core 2>;
551 reset-names = "rstctrl";
552 #address-cells = <1>;
553 #size-cells = <1>;
554 ranges = <0x0 0x55082000 0x100>;
556 mmu_ipu2: mmu@0 {
557 compatible = "ti,dra7-iommu";
558 reg = <0x0 0x100>;
559 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
560 #iommu-cells = <0>;
561 ti,iommu-bus-err-back;
562 };
563 };
565 abb_mpu: regulator-abb-mpu {
566 compatible = "ti,abb-v3";
567 regulator-name = "abb_mpu";
568 #address-cells = <0>;
569 #size-cells = <0>;
570 clocks = <&sys_clkin1>;
571 ti,settling-time = <50>;
572 ti,clock-cycles = <16>;
574 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
575 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
576 <0x4ae0c158 0x4>;
577 reg-names = "setup-address", "control-address",
578 "int-address", "efuse-address",
579 "ldo-address";
580 ti,tranxdone-status-mask = <0x80>;
581 /* LDOVBBMPU_FBB_MUX_CTRL */
582 ti,ldovbb-override-mask = <0x400>;
583 /* LDOVBBMPU_FBB_VSET_OUT */
584 ti,ldovbb-vset-mask = <0x1F>;
586 /*
587 * NOTE: only FBB mode used but actual vset will
588 * determine final biasing
589 */
590 ti,abb_info = <
591 /*uV ABB efuse rbb_m fbb_m vset_m*/
592 1060000 0 0x0 0 0x02000000 0x01F00000
593 1160000 0 0x4 0 0x02000000 0x01F00000
594 1210000 0 0x8 0 0x02000000 0x01F00000
595 >;
596 };
598 abb_ivahd: regulator-abb-ivahd {
599 compatible = "ti,abb-v3";
600 regulator-name = "abb_ivahd";
601 #address-cells = <0>;
602 #size-cells = <0>;
603 clocks = <&sys_clkin1>;
604 ti,settling-time = <50>;
605 ti,clock-cycles = <16>;
607 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
608 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
609 <0x4a002470 0x4>;
610 reg-names = "setup-address", "control-address",
611 "int-address", "efuse-address",
612 "ldo-address";
613 ti,tranxdone-status-mask = <0x40000000>;
614 /* LDOVBBIVA_FBB_MUX_CTRL */
615 ti,ldovbb-override-mask = <0x400>;
616 /* LDOVBBIVA_FBB_VSET_OUT */
617 ti,ldovbb-vset-mask = <0x1F>;
619 /*
620 * NOTE: only FBB mode used but actual vset will
621 * determine final biasing
622 */
623 ti,abb_info = <
624 /*uV ABB efuse rbb_m fbb_m vset_m*/
625 1055000 0 0x0 0 0x02000000 0x01F00000
626 1150000 0 0x4 0 0x02000000 0x01F00000
627 1250000 0 0x8 0 0x02000000 0x01F00000
628 >;
629 };
631 abb_dspeve: regulator-abb-dspeve {
632 compatible = "ti,abb-v3";
633 regulator-name = "abb_dspeve";
634 #address-cells = <0>;
635 #size-cells = <0>;
636 clocks = <&sys_clkin1>;
637 ti,settling-time = <50>;
638 ti,clock-cycles = <16>;
640 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
641 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
642 <0x4a00246c 0x4>;
643 reg-names = "setup-address", "control-address",
644 "int-address", "efuse-address",
645 "ldo-address";
646 ti,tranxdone-status-mask = <0x20000000>;
647 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
648 ti,ldovbb-override-mask = <0x400>;
649 /* LDOVBBDSPEVE_FBB_VSET_OUT */
650 ti,ldovbb-vset-mask = <0x1F>;
652 /*
653 * NOTE: only FBB mode used but actual vset will
654 * determine final biasing
655 */
656 ti,abb_info = <
657 /*uV ABB efuse rbb_m fbb_m vset_m*/
658 1055000 0 0x0 0 0x02000000 0x01F00000
659 1150000 0 0x4 0 0x02000000 0x01F00000
660 1250000 0 0x8 0 0x02000000 0x01F00000
661 >;
662 };
664 abb_gpu: regulator-abb-gpu {
665 compatible = "ti,abb-v3";
666 regulator-name = "abb_gpu";
667 #address-cells = <0>;
668 #size-cells = <0>;
669 clocks = <&sys_clkin1>;
670 ti,settling-time = <50>;
671 ti,clock-cycles = <16>;
673 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
674 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
675 <0x4ae0c154 0x4>;
676 reg-names = "setup-address", "control-address",
677 "int-address", "efuse-address",
678 "ldo-address";
679 ti,tranxdone-status-mask = <0x10000000>;
680 /* LDOVBBGPU_FBB_MUX_CTRL */
681 ti,ldovbb-override-mask = <0x400>;
682 /* LDOVBBGPU_FBB_VSET_OUT */
683 ti,ldovbb-vset-mask = <0x1F>;
685 /*
686 * NOTE: only FBB mode used but actual vset will
687 * determine final biasing
688 */
689 ti,abb_info = <
690 /*uV ABB efuse rbb_m fbb_m vset_m*/
691 1090000 0 0x0 0 0x02000000 0x01F00000
692 1210000 0 0x4 0 0x02000000 0x01F00000
693 1280000 0 0x8 0 0x02000000 0x01F00000
694 >;
695 };
697 qspi: spi@4b300000 {
698 compatible = "ti,dra7xxx-qspi";
699 reg = <0x4b300000 0x100>,
700 <0x5c000000 0x4000000>;
701 reg-names = "qspi_base", "qspi_mmap";
702 syscon-chipselects = <&scm_conf 0x558>;
703 #address-cells = <1>;
704 #size-cells = <0>;
705 ti,hwmods = "qspi";
706 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
707 clock-names = "fck";
708 num-cs = <4>;
709 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
710 status = "disabled";
711 };
713 /* OCP2SCP3 */
714 sata: sata@4a141100 {
715 compatible = "snps,dwc-ahci";
716 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
717 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
718 phys = <&sata_phy>;
719 phy-names = "sata-phy";
720 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
721 ti,hwmods = "sata";
722 ports-implemented = <0x1>;
723 };
725 /* OCP2SCP1 */
726 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
728 target-module@50000000 {
729 compatible = "ti,sysc-omap2", "ti,sysc";
730 reg = <0x50000000 4>,
731 <0x50000010 4>,
732 <0x50000014 4>;
733 reg-names = "rev", "sysc", "syss";
734 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
735 <SYSC_IDLE_NO>,
736 <SYSC_IDLE_SMART>;
737 ti,syss-mask = <1>;
738 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
739 clock-names = "fck";
740 #address-cells = <1>;
741 #size-cells = <1>;
742 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
743 <0x00000000 0x00000000 0x40000000>; /* data */
745 gpmc: gpmc@50000000 {
746 compatible = "ti,am3352-gpmc";
747 reg = <0x50000000 0x37c>; /* device IO registers */
748 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
749 dmas = <&edma_xbar 4 0>;
750 dma-names = "rxtx";
751 gpmc,num-cs = <8>;
752 gpmc,num-waitpins = <2>;
753 #address-cells = <2>;
754 #size-cells = <1>;
755 interrupt-controller;
756 #interrupt-cells = <2>;
757 gpio-controller;
758 #gpio-cells = <2>;
759 status = "disabled";
760 };
761 };
763 target-module@56000000 {
764 compatible = "ti,sysc-omap4", "ti,sysc";
765 reg = <0x5600fe00 0x4>,
766 <0x5600fe10 0x4>;
767 reg-names = "rev", "sysc";
768 ti,sysc-midle = <SYSC_IDLE_FORCE>,
769 <SYSC_IDLE_NO>,
770 <SYSC_IDLE_SMART>;
771 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
772 <SYSC_IDLE_NO>,
773 <SYSC_IDLE_SMART>;
774 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
775 clock-names = "fck";
776 #address-cells = <1>;
777 #size-cells = <1>;
778 ranges = <0 0x56000000 0x2000000>;
779 };
781 crossbar_mpu: crossbar@4a002a48 {
782 compatible = "ti,irq-crossbar";
783 reg = <0x4a002a48 0x130>;
784 interrupt-controller;
785 interrupt-parent = <&wakeupgen>;
786 #interrupt-cells = <3>;
787 ti,max-irqs = <160>;
788 ti,max-crossbar-sources = <MAX_SOURCES>;
789 ti,reg-size = <2>;
790 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
791 ti,irqs-skip = <10 133 139 140>;
792 ti,irqs-safe-map = <0>;
793 };
795 target-module@58000000 {
796 compatible = "ti,sysc-omap2", "ti,sysc";
797 reg = <0x58000000 4>,
798 <0x58000014 4>;
799 reg-names = "rev", "syss";
800 ti,syss-mask = <1>;
801 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
802 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
803 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
804 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
805 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
806 #address-cells = <1>;
807 #size-cells = <1>;
808 ranges = <0 0x58000000 0x800000>;
810 dss: dss@0 {
811 compatible = "ti,dra7-dss";
812 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
813 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
814 status = "disabled";
815 /* CTRL_CORE_DSS_PLL_CONTROL */
816 syscon-pll-ctrl = <&scm_conf 0x538>;
817 #address-cells = <1>;
818 #size-cells = <1>;
819 ranges = <0 0 0x800000>;
821 target-module@1000 {
822 compatible = "ti,sysc-omap2", "ti,sysc";
823 reg = <0x1000 0x4>,
824 <0x1010 0x4>,
825 <0x1014 0x4>;
826 reg-names = "rev", "sysc", "syss";
827 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
828 <SYSC_IDLE_NO>,
829 <SYSC_IDLE_SMART>;
830 ti,sysc-midle = <SYSC_IDLE_FORCE>,
831 <SYSC_IDLE_NO>,
832 <SYSC_IDLE_SMART>;
833 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
834 SYSC_OMAP2_ENAWAKEUP |
835 SYSC_OMAP2_SOFTRESET |
836 SYSC_OMAP2_AUTOIDLE)>;
837 ti,syss-mask = <1>;
838 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
839 clock-names = "fck";
840 #address-cells = <1>;
841 #size-cells = <1>;
842 ranges = <0 0x1000 0x1000>;
844 dispc@0 {
845 compatible = "ti,dra7-dispc";
846 reg = <0 0x1000>;
847 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
849 clock-names = "fck";
850 /* CTRL_CORE_SMA_SW_1 */
851 syscon-pol = <&scm_conf 0x534>;
852 };
853 };
855 target-module@40000 {
856 compatible = "ti,sysc-omap4", "ti,sysc";
857 reg = <0x40000 0x4>,
858 <0x40010 0x4>;
859 reg-names = "rev", "sysc";
860 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
861 <SYSC_IDLE_NO>,
862 <SYSC_IDLE_SMART>,
863 <SYSC_IDLE_SMART_WKUP>;
864 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
865 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
866 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
867 clock-names = "fck", "dss_clk";
868 #address-cells = <1>;
869 #size-cells = <1>;
870 ranges = <0 0x40000 0x40000>;
872 hdmi: encoder@0 {
873 compatible = "ti,dra7-hdmi";
874 reg = <0 0x200>,
875 <0x200 0x80>,
876 <0x300 0x80>,
877 <0x20000 0x19000>;
878 reg-names = "wp", "pll", "phy", "core";
879 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
880 status = "disabled";
881 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
882 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
883 clock-names = "fck", "sys_clk";
884 dmas = <&sdma_xbar 76>;
885 dma-names = "audio_tx";
886 };
887 };
888 };
889 };
891 aes1_target: target-module@4b500000 {
892 compatible = "ti,sysc-omap2", "ti,sysc";
893 reg = <0x4b500080 0x4>,
894 <0x4b500084 0x4>,
895 <0x4b500088 0x4>;
896 reg-names = "rev", "sysc", "syss";
897 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
898 SYSC_OMAP2_AUTOIDLE)>;
899 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
900 <SYSC_IDLE_NO>,
901 <SYSC_IDLE_SMART>,
902 <SYSC_IDLE_SMART_WKUP>;
903 ti,syss-mask = <1>;
904 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
905 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
906 clock-names = "fck";
907 #address-cells = <1>;
908 #size-cells = <1>;
909 ranges = <0x0 0x4b500000 0x1000>;
911 aes1: aes@0 {
912 compatible = "ti,omap4-aes";
913 reg = <0 0xa0>;
914 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
915 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
916 dma-names = "tx", "rx";
917 clocks = <&l3_iclk_div>;
918 clock-names = "fck";
919 };
920 };
922 aes2_target: target-module@4b700000 {
923 compatible = "ti,sysc-omap2", "ti,sysc";
924 reg = <0x4b700080 0x4>,
925 <0x4b700084 0x4>,
926 <0x4b700088 0x4>;
927 reg-names = "rev", "sysc", "syss";
928 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
929 SYSC_OMAP2_AUTOIDLE)>;
930 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
931 <SYSC_IDLE_NO>,
932 <SYSC_IDLE_SMART>,
933 <SYSC_IDLE_SMART_WKUP>;
934 ti,syss-mask = <1>;
935 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
936 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
937 clock-names = "fck";
938 #address-cells = <1>;
939 #size-cells = <1>;
940 ranges = <0x0 0x4b700000 0x1000>;
942 aes2: aes@0 {
943 compatible = "ti,omap4-aes";
944 reg = <0 0xa0>;
945 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
946 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
947 dma-names = "tx", "rx";
948 clocks = <&l3_iclk_div>;
949 clock-names = "fck";
950 };
951 };
953 sham1_target: target-module@4b101000 {
954 compatible = "ti,sysc-omap3-sham", "ti,sysc";
955 reg = <0x4b101100 0x4>,
956 <0x4b101110 0x4>,
957 <0x4b101114 0x4>;
958 reg-names = "rev", "sysc", "syss";
959 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
960 SYSC_OMAP2_AUTOIDLE)>;
961 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
962 <SYSC_IDLE_NO>,
963 <SYSC_IDLE_SMART>;
964 ti,syss-mask = <1>;
965 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
966 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
967 clock-names = "fck";
968 #address-cells = <1>;
969 #size-cells = <1>;
970 ranges = <0x0 0x4b101000 0x1000>;
972 sham1: sham@0 {
973 compatible = "ti,omap5-sham";
974 reg = <0 0x300>;
975 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
976 dmas = <&edma_xbar 119 0>;
977 dma-names = "rx";
978 clocks = <&l3_iclk_div>;
979 clock-names = "fck";
980 };
981 };
983 sham2_target: target-module@42701000 {
984 compatible = "ti,sysc-omap3-sham", "ti,sysc";
985 reg = <0x42701100 0x4>,
986 <0x42701110 0x4>,
987 <0x42701114 0x4>;
988 reg-names = "rev", "sysc", "syss";
989 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
990 SYSC_OMAP2_AUTOIDLE)>;
991 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
992 <SYSC_IDLE_NO>,
993 <SYSC_IDLE_SMART>;
994 ti,syss-mask = <1>;
995 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
996 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
997 clock-names = "fck";
998 #address-cells = <1>;
999 #size-cells = <1>;
1000 ranges = <0x0 0x42701000 0x1000>;
1002 sham2: sham@0 {
1003 compatible = "ti,omap5-sham";
1004 reg = <0 0x300>;
1005 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
1006 dmas = <&edma_xbar 165 0>;
1007 dma-names = "rx";
1008 clocks = <&l3_iclk_div>;
1009 clock-names = "fck";
1010 };
1011 };
1013 iva_hd_target: target-module@5a000000 {
1014 compatible = "ti,sysc-omap4", "ti,sysc";
1015 reg = <0x5a05a400 0x4>,
1016 <0x5a05a410 0x4>;
1017 reg-names = "rev", "sysc";
1018 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1019 <SYSC_IDLE_NO>,
1020 <SYSC_IDLE_SMART>;
1021 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1022 <SYSC_IDLE_NO>,
1023 <SYSC_IDLE_SMART>;
1024 power-domains = <&prm_iva>;
1025 resets = <&prm_iva 2>;
1026 reset-names = "rstctrl";
1027 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
1028 clock-names = "fck";
1029 #address-cells = <1>;
1030 #size-cells = <1>;
1031 ranges = <0x5a000000 0x5a000000 0x1000000>,
1032 <0x5b000000 0x5b000000 0x1000000>;
1034 iva {
1035 compatible = "ti,ivahd";
1036 };
1037 };
1039 opp_supply_mpu: opp-supply@4a003b20 {
1040 compatible = "ti,omap5-opp-supply";
1041 reg = <0x4a003b20 0xc>;
1042 ti,efuse-settings = <
1043 /* uV offset */
1044 1060000 0x0
1045 1160000 0x4
1046 1210000 0x8
1047 >;
1048 ti,absolute-max-voltage-uv = <1500000>;
1049 };
1051 };
1053 thermal_zones: thermal-zones {
1054 #include "omap4-cpu-thermal.dtsi"
1055 #include "omap5-gpu-thermal.dtsi"
1056 #include "omap5-core-thermal.dtsi"
1057 #include "dra7-dspeve-thermal.dtsi"
1058 #include "dra7-iva-thermal.dtsi"
1059 };
1061 };
1063 &cpu_thermal {
1064 polling-delay = <500>; /* milliseconds */
1065 coefficients = <0 2000>;
1066 };
1068 &gpu_thermal {
1069 coefficients = <0 2000>;
1070 };
1072 &core_thermal {
1073 coefficients = <0 2000>;
1074 };
1076 &dspeve_thermal {
1077 coefficients = <0 2000>;
1078 };
1080 &iva_thermal {
1081 coefficients = <0 2000>;
1082 };
1084 &cpu_crit {
1085 temperature = <120000>; /* milli Celsius */
1086 };
1088 &core_crit {
1089 temperature = <120000>; /* milli Celsius */
1090 };
1092 &gpu_crit {
1093 temperature = <120000>; /* milli Celsius */
1094 };
1096 &dspeve_crit {
1097 temperature = <120000>; /* milli Celsius */
1098 };
1100 &iva_crit {
1101 temperature = <120000>; /* milli Celsius */
1102 };
1104 #include "dra7-l4.dtsi"
1105 #include "dra7xx-clocks.dtsi"
1107 &prm {
1108 prm_mpu: prm@300 {
1109 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1110 reg = <0x300 0x100>;
1111 #power-domain-cells = <0>;
1112 };
1114 prm_dsp1: prm@400 {
1115 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1116 reg = <0x400 0x100>;
1117 #reset-cells = <1>;
1118 #power-domain-cells = <0>;
1119 };
1121 prm_ipu: prm@500 {
1122 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1123 reg = <0x500 0x100>;
1124 #reset-cells = <1>;
1125 #power-domain-cells = <0>;
1126 };
1128 prm_coreaon: prm@628 {
1129 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1130 reg = <0x628 0xd8>;
1131 #power-domain-cells = <0>;
1132 };
1134 prm_core: prm@700 {
1135 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1136 reg = <0x700 0x100>;
1137 #reset-cells = <1>;
1138 #power-domain-cells = <0>;
1139 };
1141 prm_iva: prm@f00 {
1142 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1143 reg = <0xf00 0x100>;
1144 #reset-cells = <1>;
1145 #power-domain-cells = <0>;
1146 };
1148 prm_cam: prm@1000 {
1149 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1150 reg = <0x1000 0x100>;
1151 #power-domain-cells = <0>;
1152 };
1154 prm_dss: prm@1100 {
1155 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1156 reg = <0x1100 0x100>;
1157 #power-domain-cells = <0>;
1158 };
1160 prm_gpu: prm@1200 {
1161 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1162 reg = <0x1200 0x100>;
1163 #power-domain-cells = <0>;
1164 };
1166 prm_l3init: prm@1300 {
1167 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1168 reg = <0x1300 0x100>;
1169 #reset-cells = <1>;
1170 #power-domain-cells = <0>;
1171 };
1173 prm_l4per: prm@1400 {
1174 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1175 reg = <0x1400 0x100>;
1176 #power-domain-cells = <0>;
1177 };
1179 prm_custefuse: prm@1600 {
1180 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1181 reg = <0x1600 0x100>;
1182 #power-domain-cells = <0>;
1183 };
1185 prm_wkupaon: prm@1724 {
1186 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1187 reg = <0x1724 0x100>;
1188 #power-domain-cells = <0>;
1189 };
1191 prm_dsp2: prm@1b00 {
1192 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1193 reg = <0x1b00 0x40>;
1194 #reset-cells = <1>;
1195 #power-domain-cells = <0>;
1196 };
1198 prm_eve1: prm@1b40 {
1199 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1200 reg = <0x1b40 0x40>;
1201 #power-domain-cells = <0>;
1202 };
1204 prm_eve2: prm@1b80 {
1205 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1206 reg = <0x1b80 0x40>;
1207 #power-domain-cells = <0>;
1208 };
1210 prm_eve3: prm@1bc0 {
1211 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1212 reg = <0x1bc0 0x40>;
1213 #power-domain-cells = <0>;
1214 };
1216 prm_eve4: prm@1c00 {
1217 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1218 reg = <0x1c00 0x60>;
1219 #power-domain-cells = <0>;
1220 };
1222 prm_rtc: prm@1c60 {
1223 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1224 reg = <0x1c60 0x20>;
1225 #power-domain-cells = <0>;
1226 };
1228 prm_vpe: prm@1c80 {
1229 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1230 reg = <0x1c80 0x80>;
1231 #power-domain-cells = <0>;
1232 };
1233 };
1235 /* Preferred always-on timer for clockevent */
1236 &timer1_target {
1237 ti,no-reset-on-init;
1238 ti,no-idle;
1239 timer@0 {
1240 assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
1241 assigned-clock-parents = <&sys_32k_ck>;
1242 };
1243 };