arch/arm/boot/dts/hip04.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Hisilicon Ltd. HiP04 SoC
   4  *
   5  * Copyright (C) 2013-2014 Hisilicon Ltd.
   6  * Copyright (C) 2013-2014 Linaro Ltd.
   7  *
   8  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
   9  */
  10
  11 / {
  12         /* memory bus is 64-bit */
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         aliases {
  17                 serial0 = &uart0;
  18         };
  19
  20         bootwrapper {
  21                 compatible = "hisilicon,hip04-bootwrapper";
  22                 boot-method = <0x10c00000 0x10000>, <0xe0000100 0x1000>;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu-map {
  30                         cluster0 {
  31                                 core0 {
  32                                         cpu = <&CPU0>;
  33                                 };
  34                                 core1 {
  35                                         cpu = <&CPU1>;
  36                                 };
  37                                 core2 {
  38                                         cpu = <&CPU2>;
  39                                 };
  40                                 core3 {
  41                                         cpu = <&CPU3>;
  42                                 };
  43                         };
  44                         cluster1 {
  45                                 core0 {
  46                                         cpu = <&CPU4>;
  47                                 };
  48                                 core1 {
  49                                         cpu = <&CPU5>;
  50                                 };
  51                                 core2 {
  52                                         cpu = <&CPU6>;
  53                                 };
  54                                 core3 {
  55                                         cpu = <&CPU7>;
  56                                 };
  57                         };
  58                         cluster2 {
  59                                 core0 {
  60                                         cpu = <&CPU8>;
  61                                 };
  62                                 core1 {
  63                                         cpu = <&CPU9>;
  64                                 };
  65                                 core2 {
  66                                         cpu = <&CPU10>;
  67                                 };
  68                                 core3 {
  69                                         cpu = <&CPU11>;
  70                                 };
  71                         };
  72                         cluster3 {
  73                                 core0 {
  74                                         cpu = <&CPU12>;
  75                                 };
  76                                 core1 {
  77                                         cpu = <&CPU13>;
  78                                 };
  79                                 core2 {
  80                                         cpu = <&CPU14>;
  81                                 };
  82                                 core3 {
  83                                         cpu = <&CPU15>;
  84                                 };
  85                         };
  86                 };
  87                 CPU0: cpu@0 {
  88                         device_type = "cpu";
  89                         compatible = "arm,cortex-a15";
  90                         reg = <0>;
  91                 };
  92                 CPU1: cpu@1 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a15";
  95                         reg = <1>;
  96                 };
  97                 CPU2: cpu@2 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a15";
 100                         reg = <2>;
 101                 };
 102                 CPU3: cpu@3 {
 103                         device_type = "cpu";
 104                         compatible = "arm,cortex-a15";
 105                         reg = <3>;
 106                 };
 107                 CPU4: cpu@100 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a15";
 110                         reg = <0x100>;
 111                 };
 112                 CPU5: cpu@101 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a15";
 115                         reg = <0x101>;
 116                 };
 117                 CPU6: cpu@102 {
 118                         device_type = "cpu";
 119                         compatible = "arm,cortex-a15";
 120                         reg = <0x102>;
 121                 };
 122                 CPU7: cpu@103 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a15";
 125                         reg = <0x103>;
 126                 };
 127                 CPU8: cpu@200 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a15";
 130                         reg = <0x200>;
 131                 };
 132                 CPU9: cpu@201 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a15";
 135                         reg = <0x201>;
 136                 };
 137                 CPU10: cpu@202 {
 138                         device_type = "cpu";
 139                         compatible = "arm,cortex-a15";
 140                         reg = <0x202>;
 141                 };
 142                 CPU11: cpu@203 {
 143                         device_type = "cpu";
 144                         compatible = "arm,cortex-a15";
 145                         reg = <0x203>;
 146                 };
 147                 CPU12: cpu@300 {
 148                         device_type = "cpu";
 149                         compatible = "arm,cortex-a15";
 150                         reg = <0x300>;
 151                 };
 152                 CPU13: cpu@301 {
 153                         device_type = "cpu";
 154                         compatible = "arm,cortex-a15";
 155                         reg = <0x301>;
 156                 };
 157                 CPU14: cpu@302 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a15";
 160                         reg = <0x302>;
 161                 };
 162                 CPU15: cpu@303 {
 163                         device_type = "cpu";
 164                         compatible = "arm,cortex-a15";
 165                         reg = <0x303>;
 166                 };
 167         };
 168
 169         timer {
 170                 compatible = "arm,armv7-timer";
 171                 interrupt-parent = <&gic>;
 172                 interrupts = <1 13 0xf08>,
 173                              <1 14 0xf08>,
 174                              <1 11 0xf08>,
 175                              <1 10 0xf08>;
 176         };
 177
 178         clk_50m: clk_50m {
 179                 #clock-cells = <0>;
 180                 compatible = "fixed-clock";
 181                 clock-frequency = <50000000>;
 182         };
 183
 184         clk_168m: clk_168m {
 185                 #clock-cells = <0>;
 186                 compatible = "fixed-clock";
 187                 clock-frequency = <168000000>;
 188         };
 189
 190         clk_375m: clk_375m {
 191                 #clock-cells = <0>;
 192                 compatible = "fixed-clock";
 193                 clock-frequency = <375000000>;
 194         };
 195
 196         soc {
 197                 /* It's a 32-bit SoC. */
 198                 #address-cells = <1>;
 199                 #size-cells = <1>;
 200                 compatible = "simple-bus";
 201                 interrupt-parent = <&gic>;
 202                 ranges = <0 0 0xe0000000 0x10000000>;
 203
 204                 gic: interrupt-controller@c01000 {
 205                         compatible = "hisilicon,hip04-intc";
 206                         #interrupt-cells = <3>;
 207                         #address-cells = <0>;
 208                         interrupt-controller;
 209                         interrupts = <1 9 0xf04>;
 210
 211                         reg = <0xc01000 0x1000>, <0xc02000 0x1000>,
 212                               <0xc04000 0x2000>, <0xc06000 0x2000>;
 213                 };
 214
 215                 sysctrl: sysctrl {
 216                         compatible = "hisilicon,sysctrl", "syscon";
 217                         reg = <0x3e00000 0x00100000>;
 218                 };
 219
 220                 fabric: fabric {
 221                         compatible = "hisilicon,hip04-fabric";
 222                         reg = <0x302a000 0x1000>;
 223                 };
 224
 225                 dual_timer0: dual_timer@3000000 {
 226                         compatible = "arm,sp804", "arm,primecell";
 227                         reg = <0x3000000 0x1000>;
 228                         interrupts = <0 224 4>;
 229                         clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>;
 230                         clock-names = "timer0clk", "timer1clk", "apb_pclk";
 231                 };
 232
 233                 arm-pmu {
 234                         compatible = "arm,cortex-a15-pmu";
 235                         interrupts = <0 64 4>,
 236                                      <0 65 4>,
 237                                      <0 66 4>,
 238                                      <0 67 4>,
 239                                      <0 68 4>,
 240                                      <0 69 4>,
 241                                      <0 70 4>,
 242                                      <0 71 4>,
 243                                      <0 72 4>,
 244                                      <0 73 4>,
 245                                      <0 74 4>,
 246                                      <0 75 4>,
 247                                      <0 76 4>,
 248                                      <0 77 4>,
 249                                      <0 78 4>,
 250                                      <0 79 4>;
 251                 };
 252
 253                 uart0: serial@4007000 {
 254                         compatible = "snps,dw-apb-uart";
 255                         reg = <0x4007000 0x1000>;
 256                         interrupts = <0 381 4>;
 257                         clocks = <&clk_168m>, <&clk_168m>;
 258                         clock-names = "baudclk", "apb_pclk";
 259                         reg-shift = <2>;
 260                         status = "disabled";
 261                 };
 262
 263                 sata0: sata@a000000 {
 264                         compatible = "hisilicon,hisi-ahci";
 265                         reg = <0xa000000 0x1000000>;
 266                         interrupts = <0 372 4>;
 267                 };
 268
 269         };
 270
 271         etb@0,e3c42000 {
 272                 compatible = "arm,coresight-etb10", "arm,primecell";
 273                 reg = <0 0xe3c42000 0 0x1000>;
 274
 275                 clocks = <&clk_375m>;
 276                 clock-names = "apb_pclk";
 277                 in-ports {
 278                         port {
 279                                 etb0_in_port: endpoint@0 {
 280                                         remote-endpoint = <&replicator0_out_port0>;
 281                                 };
 282                         };
 283                 };
 284         };
 285
 286         etb@0,e3c82000 {
 287                 compatible = "arm,coresight-etb10", "arm,primecell";
 288                 reg = <0 0xe3c82000 0 0x1000>;
 289
 290                 clocks = <&clk_375m>;
 291                 clock-names = "apb_pclk";
 292                 in-ports {
 293                         port {
 294                                 etb1_in_port: endpoint@0 {
 295                                         remote-endpoint = <&replicator1_out_port0>;
 296                                 };
 297                         };
 298                 };
 299         };
 300
 301         etb@0,e3cc2000 {
 302                 compatible = "arm,coresight-etb10", "arm,primecell";
 303                 reg = <0 0xe3cc2000 0 0x1000>;
 304
 305                 clocks = <&clk_375m>;
 306                 clock-names = "apb_pclk";
 307                 in-ports {
 308                         port {
 309                                 etb2_in_port: endpoint@0 {
 310                                         remote-endpoint = <&replicator2_out_port0>;
 311                                 };
 312                         };
 313                 };
 314         };
 315
 316         etb@0,e3d02000 {
 317                 compatible = "arm,coresight-etb10", "arm,primecell";
 318                 reg = <0 0xe3d02000 0 0x1000>;
 319
 320                 clocks = <&clk_375m>;
 321                 clock-names = "apb_pclk";
 322                 in-ports {
 323                         port {
 324                                 etb3_in_port: endpoint@0 {
 325                                         remote-endpoint = <&replicator3_out_port0>;
 326                                 };
 327                         };
 328                 };
 329         };
 330
 331         tpiu@0,e3c05000 {
 332                 compatible = "arm,coresight-tpiu", "arm,primecell";
 333                 reg = <0 0xe3c05000 0 0x1000>;
 334
 335                 clocks = <&clk_375m>;
 336                 clock-names = "apb_pclk";
 337                 in-ports {
 338                         port {
 339                                 tpiu_in_port: endpoint@0 {
 340                                         remote-endpoint = <&funnel4_out_port0>;
 341                                 };
 342                         };
 343                 };
 344         };
 345
 346         replicator0 {
 347                 /* non-configurable replicators don't show up on the
 348                  * AMBA bus.  As such no need to add "arm,primecell".
 349                  */
 350                 compatible = "arm,coresight-static-replicator";
 351
 352                 out-ports {
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355
 356                         /* replicator output ports */
 357                         port@0 {
 358                                 reg = <0>;
 359                                 replicator0_out_port0: endpoint {
 360                                         remote-endpoint = <&etb0_in_port>;
 361                                 };
 362                         };
 363
 364                         port@1 {
 365                                 reg = <1>;
 366                                 replicator0_out_port1: endpoint {
 367                                         remote-endpoint = <&funnel4_in_port0>;
 368                                 };
 369                         };
 370                 };
 371
 372                 in-ports {
 373                         port {
 374                                 replicator0_in_port0: endpoint {
 375                                         remote-endpoint = <&funnel0_out_port0>;
 376                                 };
 377                         };
 378                 };
 379         };
 380
 381         replicator1 {
 382                 /* non-configurable replicators don't show up on the
 383                  * AMBA bus.  As such no need to add "arm,primecell".
 384                  */
 385                 compatible = "arm,coresight-static-replicator";
 386
 387                 out-ports {
 388                         #address-cells = <1>;
 389                         #size-cells = <0>;
 390
 391                         /* replicator output ports */
 392                         port@0 {
 393                                 reg = <0>;
 394                                 replicator1_out_port0: endpoint {
 395                                         remote-endpoint = <&etb1_in_port>;
 396                                 };
 397                         };
 398
 399                         port@1 {
 400                                 reg = <1>;
 401                                 replicator1_out_port1: endpoint {
 402                                         remote-endpoint = <&funnel4_in_port1>;
 403                                 };
 404                         };
 405                 };
 406
 407                 in-ports {
 408                         port {
 409                                 replicator1_in_port0: endpoint {
 410                                         remote-endpoint = <&funnel1_out_port0>;
 411                                 };
 412                         };
 413                 };
 414         };
 415
 416         replicator2 {
 417                 /* non-configurable replicators don't show up on the
 418                  * AMBA bus.  As such no need to add "arm,primecell".
 419                  */
 420                 compatible = "arm,coresight-static-replicator";
 421
 422                 out-ports {
 423                         #address-cells = <1>;
 424                         #size-cells = <0>;
 425
 426                         port@0 {
 427                                 reg = <0>;
 428                                 replicator2_out_port0: endpoint {
 429                                         remote-endpoint = <&etb2_in_port>;
 430                                 };
 431                         };
 432
 433                         port@1 {
 434                                 reg = <1>;
 435                                         replicator2_out_port1: endpoint {
 436                                         remote-endpoint = <&funnel4_in_port2>;
 437                                 };
 438                         };
 439                 };
 440
 441                 in-ports {
 442                         port {
 443                                 replicator2_in_port0: endpoint {
 444                                         remote-endpoint = <&funnel2_out_port0>;
 445                                 };
 446                         };
 447                 };
 448         };
 449
 450         replicator3 {
 451                 /* non-configurable replicators don't show up on the
 452                  * AMBA bus.  As such no need to add "arm,primecell".
 453                  */
 454                 compatible = "arm,coresight-static-replicator";
 455
 456                 out-ports {
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459
 460                         port@0 {
 461                                 reg = <0>;
 462                                 replicator3_out_port0: endpoint {
 463                                         remote-endpoint = <&etb3_in_port>;
 464                                 };
 465                         };
 466
 467                         port@1 {
 468                                 reg = <1>;
 469                                 replicator3_out_port1: endpoint {
 470                                         remote-endpoint = <&funnel4_in_port3>;
 471                                 };
 472                         };
 473                 };
 474
 475                 in-ports {
 476                         port {
 477                                 replicator3_in_port0: endpoint {
 478                                         remote-endpoint = <&funnel3_out_port0>;
 479                                 };
 480                         };
 481                 };
 482         };
 483
 484         funnel@0,e3c41000 {
 485                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 486                 reg = <0 0xe3c41000 0 0x1000>;
 487
 488                 clocks = <&clk_375m>;
 489                 clock-names = "apb_pclk";
 490                 out-ports {
 491                         port {
 492                                 funnel0_out_port0: endpoint {
 493                                         remote-endpoint =
 494                                                 <&replicator0_in_port0>;
 495                                 };
 496                         };
 497                 };
 498
 499                 in-ports {
 500                         #address-cells = <1>;
 501                         #size-cells = <0>;
 502
 503                         port@0 {
 504                                 reg = <0>;
 505                                 funnel0_in_port0: endpoint {
 506                                         remote-endpoint = <&ptm0_out_port>;
 507                                 };
 508                         };
 509
 510                         port@1 {
 511                                 reg = <1>;
 512                                 funnel0_in_port1: endpoint {
 513                                         remote-endpoint = <&ptm1_out_port>;
 514                                 };
 515                         };
 516
 517                         port@2 {
 518                                 reg = <2>;
 519                                 funnel0_in_port2: endpoint {
 520                                         remote-endpoint = <&ptm2_out_port>;
 521                                 };
 522                         };
 523
 524                         port@3 {
 525                                 reg = <3>;
 526                                 funnel0_in_port3: endpoint {
 527                                         remote-endpoint = <&ptm3_out_port>;
 528                                 };
 529                         };
 530                 };
 531         };
 532
 533         funnel@0,e3c81000 {
 534                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 535                 reg = <0 0xe3c81000 0 0x1000>;
 536
 537                 clocks = <&clk_375m>;
 538                 clock-names = "apb_pclk";
 539                 out-ports {
 540                         port {
 541                                 funnel1_out_port0: endpoint {
 542                                         remote-endpoint =
 543                                                 <&replicator1_in_port0>;
 544                                 };
 545                         };
 546                 };
 547
 548                 in-ports {
 549                         #address-cells = <1>;
 550                         #size-cells = <0>;
 551
 552                         port@0 {
 553                                 reg = <0>;
 554                                 funnel1_in_port0: endpoint {
 555                                         remote-endpoint = <&ptm4_out_port>;
 556                                 };
 557                         };
 558
 559                         port@1 {
 560                                 reg = <1>;
 561                                 funnel1_in_port1: endpoint {
 562                                         remote-endpoint = <&ptm5_out_port>;
 563                                 };
 564                         };
 565
 566                         port@2 {
 567                                 reg = <2>;
 568                                 funnel1_in_port2: endpoint {
 569                                         remote-endpoint = <&ptm6_out_port>;
 570                                 };
 571                         };
 572
 573                         port@3 {
 574                                 reg = <3>;
 575                                 funnel1_in_port3: endpoint {
 576                                         remote-endpoint = <&ptm7_out_port>;
 577                                 };
 578                         };
 579                 };
 580         };
 581
 582         funnel@0,e3cc1000 {
 583                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 584                 reg = <0 0xe3cc1000 0 0x1000>;
 585
 586                 clocks = <&clk_375m>;
 587                 clock-names = "apb_pclk";
 588                 out-ports {
 589                         port {
 590                                 funnel2_out_port0: endpoint {
 591                                         remote-endpoint =
 592                                                 <&replicator2_in_port0>;
 593                                 };
 594                         };
 595                 };
 596
 597                 in-ports {
 598                         #address-cells = <1>;
 599                         #size-cells = <0>;
 600
 601                         port@0 {
 602                                 reg = <0>;
 603                                 funnel2_in_port0: endpoint {
 604                                         remote-endpoint = <&ptm8_out_port>;
 605                                 };
 606                         };
 607
 608                         port@1 {
 609                                 reg = <1>;
 610                                 funnel2_in_port1: endpoint {
 611                                         remote-endpoint = <&ptm9_out_port>;
 612                                 };
 613                         };
 614
 615                         port@2 {
 616                                 reg = <2>;
 617                                 funnel2_in_port2: endpoint {
 618                                         remote-endpoint = <&ptm10_out_port>;
 619                                 };
 620                         };
 621
 622                         port@3 {
 623                                 reg = <3>;
 624                                 funnel2_in_port3: endpoint {
 625                                         remote-endpoint = <&ptm11_out_port>;
 626                                 };
 627                         };
 628                 };
 629         };
 630
 631         funnel@0,e3d01000 {
 632                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 633                 reg = <0 0xe3d01000 0 0x1000>;
 634
 635                 clocks = <&clk_375m>;
 636                 clock-names = "apb_pclk";
 637                 out-ports {
 638                         port {
 639                                 funnel3_out_port0: endpoint {
 640                                         remote-endpoint =
 641                                                 <&replicator3_in_port0>;
 642                                 };
 643                         };
 644                 };
 645
 646                 in-ports {
 647                         #address-cells = <1>;
 648                         #size-cells = <0>;
 649
 650                         port@0 {
 651                                 reg = <0>;
 652                                 funnel3_in_port0: endpoint {
 653                                         remote-endpoint = <&ptm12_out_port>;
 654                                 };
 655                         };
 656
 657                         port@1 {
 658                                 reg = <1>;
 659                                 funnel3_in_port1: endpoint {
 660                                         remote-endpoint = <&ptm13_out_port>;
 661                                 };
 662                         };
 663
 664                         port@2 {
 665                                 reg = <2>;
 666                                 funnel3_in_port2: endpoint {
 667                                         remote-endpoint = <&ptm14_out_port>;
 668                                 };
 669                         };
 670
 671                         port@3 {
 672                                 reg = <3>;
 673                                 funnel3_in_port3: endpoint {
 674                                         remote-endpoint = <&ptm15_out_port>;
 675                                 };
 676                         };
 677                 };
 678         };
 679
 680         funnel@0,e3c04000 {
 681                 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
 682                 reg = <0 0xe3c04000 0 0x1000>;
 683
 684                 clocks = <&clk_375m>;
 685                 clock-names = "apb_pclk";
 686                 out-ports {
 687                         port {
 688                                 funnel4_out_port0: endpoint {
 689                                         remote-endpoint = <&tpiu_in_port>;
 690                                 };
 691                         };
 692                 };
 693
 694                 in-ports {
 695                         #address-cells = <1>;
 696                         #size-cells = <0>;
 697
 698                         port@0 {
 699                                 reg = <0>;
 700                                 funnel4_in_port0: endpoint {
 701                                         remote-endpoint =
 702                                                 <&replicator0_out_port1>;
 703                                 };
 704                         };
 705
 706                         port@1 {
 707                                 reg = <1>;
 708                                 funnel4_in_port1: endpoint {
 709                                         remote-endpoint =
 710                                                 <&replicator1_out_port1>;
 711                                 };
 712                         };
 713
 714                         port@2 {
 715                                 reg = <2>;
 716                                 funnel4_in_port2: endpoint {
 717                                         remote-endpoint =
 718                                                 <&replicator2_out_port1>;
 719                                 };
 720                         };
 721
 722                         port@3 {
 723                                 reg = <3>;
 724                                 funnel4_in_port3: endpoint {
 725                                         remote-endpoint =
 726                                                 <&replicator3_out_port1>;
 727                                 };
 728                         };
 729                 };
 730         };
 731
 732         ptm@0,e3c7c000 {
 733                 compatible = "arm,coresight-etm3x", "arm,primecell";
 734                 reg = <0 0xe3c7c000 0 0x1000>;
 735
 736                 clocks = <&clk_375m>;
 737                 clock-names = "apb_pclk";
 738                 cpu = <&CPU0>;
 739                 out-ports {
 740                         port {
 741                                 ptm0_out_port: endpoint {
 742                                         remote-endpoint = <&funnel0_in_port0>;
 743                                 };
 744                         };
 745                 };
 746         };
 747
 748         ptm@0,e3c7d000 {
 749                 compatible = "arm,coresight-etm3x", "arm,primecell";
 750                 reg = <0 0xe3c7d000 0 0x1000>;
 751
 752                 clocks = <&clk_375m>;
 753                 clock-names = "apb_pclk";
 754                 cpu = <&CPU1>;
 755                 out-ports {
 756                         port {
 757                                 ptm1_out_port: endpoint {
 758                                         remote-endpoint = <&funnel0_in_port1>;
 759                                 };
 760                         };
 761                 };
 762         };
 763
 764         ptm@0,e3c7e000 {
 765                 compatible = "arm,coresight-etm3x", "arm,primecell";
 766                 reg = <0 0xe3c7e000 0 0x1000>;
 767
 768                 clocks = <&clk_375m>;
 769                 clock-names = "apb_pclk";
 770                 cpu = <&CPU2>;
 771                 out-ports {
 772                         port {
 773                                 ptm2_out_port: endpoint {
 774                                         remote-endpoint = <&funnel0_in_port2>;
 775                                 };
 776                         };
 777                 };
 778         };
 779
 780         ptm@0,e3c7f000 {
 781                 compatible = "arm,coresight-etm3x", "arm,primecell";
 782                 reg = <0 0xe3c7f000 0 0x1000>;
 783
 784                 clocks = <&clk_375m>;
 785                 clock-names = "apb_pclk";
 786                 cpu = <&CPU3>;
 787                 out-ports {
 788                         port {
 789                                 ptm3_out_port: endpoint {
 790                                         remote-endpoint = <&funnel0_in_port3>;
 791                                 };
 792                         };
 793                 };
 794         };
 795
 796         ptm@0,e3cbc000 {
 797                 compatible = "arm,coresight-etm3x", "arm,primecell";
 798                 reg = <0 0xe3cbc000 0 0x1000>;
 799
 800                 clocks = <&clk_375m>;
 801                 clock-names = "apb_pclk";
 802                 cpu = <&CPU4>;
 803                 out-ports {
 804                         port {
 805                                 ptm4_out_port: endpoint {
 806                                         remote-endpoint = <&funnel1_in_port0>;
 807                                 };
 808                         };
 809                 };
 810         };
 811
 812         ptm@0,e3cbd000 {
 813                 compatible = "arm,coresight-etm3x", "arm,primecell";
 814                 reg = <0 0xe3cbd000 0 0x1000>;
 815
 816                 clocks = <&clk_375m>;
 817                 clock-names = "apb_pclk";
 818                 cpu = <&CPU5>;
 819                 out-ports {
 820                         port {
 821                                 ptm5_out_port: endpoint {
 822                                         remote-endpoint = <&funnel1_in_port1>;
 823                                 };
 824                         };
 825                 };
 826         };
 827
 828         ptm@0,e3cbe000 {
 829                 compatible = "arm,coresight-etm3x", "arm,primecell";
 830                 reg = <0 0xe3cbe000 0 0x1000>;
 831
 832                 clocks = <&clk_375m>;
 833                 clock-names = "apb_pclk";
 834                 cpu = <&CPU6>;
 835                 out-ports {
 836                         port {
 837                                 ptm6_out_port: endpoint {
 838                                         remote-endpoint = <&funnel1_in_port2>;
 839                                 };
 840                         };
 841                 };
 842         };
 843
 844         ptm@0,e3cbf000 {
 845                 compatible = "arm,coresight-etm3x", "arm,primecell";
 846                 reg = <0 0xe3cbf000 0 0x1000>;
 847
 848                 clocks = <&clk_375m>;
 849                 clock-names = "apb_pclk";
 850                 cpu = <&CPU7>;
 851                 out-ports {
 852                         port {
 853                                 ptm7_out_port: endpoint {
 854                                         remote-endpoint = <&funnel1_in_port3>;
 855                                 };
 856                         };
 857                 };
 858         };
 859
 860         ptm@0,e3cfc000 {
 861                 compatible = "arm,coresight-etm3x", "arm,primecell";
 862                 reg = <0 0xe3cfc000 0 0x1000>;
 863
 864                 clocks = <&clk_375m>;
 865                 clock-names = "apb_pclk";
 866                 cpu = <&CPU8>;
 867                 out-ports {
 868                         port {
 869                                 ptm8_out_port: endpoint {
 870                                         remote-endpoint = <&funnel2_in_port0>;
 871                                 };
 872                         };
 873                 };
 874         };
 875
 876         ptm@0,e3cfd000 {
 877                 compatible = "arm,coresight-etm3x", "arm,primecell";
 878                 reg = <0 0xe3cfd000 0 0x1000>;
 879                 clocks = <&clk_375m>;
 880                 clock-names = "apb_pclk";
 881                 cpu = <&CPU9>;
 882                 out-ports {
 883                         port {
 884                                 ptm9_out_port: endpoint {
 885                                         remote-endpoint = <&funnel2_in_port1>;
 886                                 };
 887                         };
 888                 };
 889         };
 890
 891         ptm@0,e3cfe000 {
 892                 compatible = "arm,coresight-etm3x", "arm,primecell";
 893                 reg = <0 0xe3cfe000 0 0x1000>;
 894
 895                 clocks = <&clk_375m>;
 896                 clock-names = "apb_pclk";
 897                 cpu = <&CPU10>;
 898                 out-ports {
 899                         port {
 900                                 ptm10_out_port: endpoint {
 901                                         remote-endpoint = <&funnel2_in_port2>;
 902                                 };
 903                         };
 904                 };
 905         };
 906
 907         ptm@0,e3cff000 {
 908                 compatible = "arm,coresight-etm3x", "arm,primecell";
 909                 reg = <0 0xe3cff000 0 0x1000>;
 910
 911                 clocks = <&clk_375m>;
 912                 clock-names = "apb_pclk";
 913                 cpu = <&CPU11>;
 914                 out-ports {
 915                         port {
 916                                 ptm11_out_port: endpoint {
 917                                         remote-endpoint = <&funnel2_in_port3>;
 918                                 };
 919                         };
 920                 };
 921         };
 922
 923         ptm@0,e3d3c000 {
 924                 compatible = "arm,coresight-etm3x", "arm,primecell";
 925                 reg = <0 0xe3d3c000 0 0x1000>;
 926
 927                 clocks = <&clk_375m>;
 928                 clock-names = "apb_pclk";
 929                 cpu = <&CPU12>;
 930                 out-ports {
 931                         port {
 932                                 ptm12_out_port: endpoint {
 933                                         remote-endpoint = <&funnel3_in_port0>;
 934                                 };
 935                         };
 936                 };
 937         };
 938
 939         ptm@0,e3d3d000 {
 940                 compatible = "arm,coresight-etm3x", "arm,primecell";
 941                 reg = <0 0xe3d3d000 0 0x1000>;
 942
 943                 clocks = <&clk_375m>;
 944                 clock-names = "apb_pclk";
 945                 cpu = <&CPU13>;
 946                 out-ports {
 947                         port {
 948                                 ptm13_out_port: endpoint {
 949                                         remote-endpoint = <&funnel3_in_port1>;
 950                                 };
 951                         };
 952                 };
 953         };
 954
 955         ptm@0,e3d3e000 {
 956                 compatible = "arm,coresight-etm3x", "arm,primecell";
 957                 reg = <0 0xe3d3e000 0 0x1000>;
 958
 959                 clocks = <&clk_375m>;
 960                 clock-names = "apb_pclk";
 961                 cpu = <&CPU14>;
 962                 out-ports {
 963                         port {
 964                                 ptm14_out_port: endpoint {
 965                                         remote-endpoint = <&funnel3_in_port2>;
 966                                 };
 967                         };
 968                 };
 969         };
 970
 971         ptm@0,e3d3f000 {
 972                 compatible = "arm,coresight-etm3x", "arm,primecell";
 973                 reg = <0 0xe3d3f000 0 0x1000>;
 974
 975                 clocks = <&clk_375m>;
 976                 clock-names = "apb_pclk";
 977                 cpu = <&CPU15>;
 978                 out-ports {
 979                         port {
 980                                 ptm15_out_port: endpoint {
 981                                         remote-endpoint = <&funnel3_in_port3>;
 982                                 };
 983                         };
 984                 };
 985         };
 986 };