arch/arm/boot/dts/imx51-babbage.dts

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright 2011 Freescale Semiconductor, Inc.
   4 // Copyright 2011 Linaro Ltd.
   5
   6 /dts-v1/;
   7 #include "imx51.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX51 Babbage Board";
  11         compatible = "fsl,imx51-babbage", "fsl,imx51";
  12
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         memory@90000000 {
  18                 device_type = "memory";
  19                 reg = <0x90000000 0x20000000>;
  20         };
  21
  22         ckih1 {
  23                 clock-frequency = <22579200>;
  24         };
  25
  26         clk_osc: clk-osc {
  27                 compatible = "fixed-clock";
  28                 #clock-cells = <0>;
  29                 clock-frequency = <26000000>;
  30         };
  31
  32         clk_osc_gate: clk-osc-gate {
  33                 compatible = "gpio-gate-clock";
  34                 pinctrl-names = "default";
  35                 pinctrl-0 = <&pinctrl_clk26mhz_osc>;
  36                 clocks = <&clk_osc>;
  37                 #clock-cells = <0>;
  38                 enable-gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
  39         };
  40
  41         clk_audio: clk-audio {
  42                 compatible = "gpio-gate-clock";
  43                 pinctrl-names = "default";
  44                 pinctrl-0 = <&pinctrl_clk26mhz_audio>;
  45                 clocks = <&clk_osc_gate>;
  46                 #clock-cells = <0>;
  47                 enable-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
  48         };
  49
  50         clk_usb: clk-usb {
  51                 compatible = "gpio-gate-clock";
  52                 pinctrl-names = "default";
  53                 pinctrl-0 = <&pinctrl_clk26mhz_usb>;
  54                 clocks = <&clk_osc_gate>;
  55                 #clock-cells = <0>;
  56                 enable-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
  57         };
  58
  59         display1: disp1 {
  60                 compatible = "fsl,imx-parallel-display";
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 interface-pix-fmt = "rgb24";
  64                 pinctrl-names = "default";
  65                 pinctrl-0 = <&pinctrl_ipu_disp1>;
  66
  67                 port@0 {
  68                 reg = <0>;
  69
  70                         display0_in: endpoint {
  71                                 remote-endpoint = <&ipu_di0_disp1>;
  72                         };
  73                 };
  74
  75                 port@1 {
  76                         reg = <1>;
  77
  78                         parallel_display_out: endpoint {
  79                                 remote-endpoint = <&tfp410_in>;
  80                         };
  81                 };
  82         };
  83
  84         display2: disp2 {
  85                 compatible = "fsl,imx-parallel-display";
  86                 interface-pix-fmt = "rgb565";
  87                 pinctrl-names = "default";
  88                 pinctrl-0 = <&pinctrl_ipu_disp2>;
  89                 status = "disabled";
  90                 display-timings {
  91                         native-mode = <&timing1>;
  92                         timing1: claawvga {
  93                                 clock-frequency = <27000000>;
  94                                 hactive = <800>;
  95                                 vactive = <480>;
  96                                 hback-porch = <40>;
  97                                 hfront-porch = <60>;
  98                                 vback-porch = <10>;
  99                                 vfront-porch = <10>;
 100                                 hsync-len = <20>;
 101                                 vsync-len = <10>;
 102                                 hsync-active = <0>;
 103                                 vsync-active = <0>;
 104                                 de-active = <1>;
 105                                 pixelclk-active = <0>;
 106                         };
 107                 };
 108
 109                 port {
 110                         display1_in: endpoint {
 111                                 remote-endpoint = <&ipu_di1_disp2>;
 112                         };
 113                 };
 114         };
 115
 116         dvi-connector {
 117                 compatible = "dvi-connector";
 118                 digital;
 119
 120                 port {
 121                         dvi_connector_in: endpoint {
 122                                 remote-endpoint = <&tfp410_out>;
 123                         };
 124                 };
 125         };
 126
 127         dvi-encoder {
 128                 compatible = "ti,tfp410";
 129
 130                 ports {
 131                         #address-cells = <1>;
 132                         #size-cells = <0>;
 133
 134                         port@0 {
 135                                 reg = <0>;
 136
 137                                 tfp410_in: endpoint {
 138                                         remote-endpoint = <&parallel_display_out>;
 139                                 };
 140                         };
 141
 142                         port@1 {
 143                                 reg = <1>;
 144
 145                                 tfp410_out: endpoint {
 146                                         remote-endpoint = <&dvi_connector_in>;
 147                                 };
 148                         };
 149                 };
 150         };
 151
 152         gpio-keys {
 153                 compatible = "gpio-keys";
 154                 pinctrl-names = "default";
 155                 pinctrl-0 = <&pinctrl_gpio_keys>;
 156
 157                 power {
 158                         label = "Power Button";
 159                         gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
 160                         linux,code = <KEY_POWER>;
 161                         wakeup-source;
 162                 };
 163         };
 164
 165         leds {
 166                 compatible = "gpio-leds";
 167                 pinctrl-names = "default";
 168                 pinctrl-0 = <&pinctrl_gpio_leds>;
 169
 170                 led-diagnostic {
 171                         label = "diagnostic";
 172                         gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
 173                 };
 174         };
 175
 176         regulators {
 177                 compatible = "simple-bus";
 178                 #address-cells = <1>;
 179                 #size-cells = <0>;
 180
 181                 reg_hub_reset: regulator@0 {
 182                         compatible = "regulator-fixed";
 183                         pinctrl-names = "default";
 184                         pinctrl-0 = <&pinctrl_usbotgreg>;
 185                         reg = <0>;
 186                         regulator-name = "hub_reset";
 187                         regulator-min-microvolt = <5000000>;
 188                         regulator-max-microvolt = <5000000>;
 189                         gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 190                         enable-active-high;
 191                 };
 192         };
 193
 194         sound {
 195                 compatible = "fsl,imx51-babbage-sgtl5000",
 196                              "fsl,imx-audio-sgtl5000";
 197                 model = "imx51-babbage-sgtl5000";
 198                 ssi-controller = <&ssi2>;
 199                 audio-codec = <&sgtl5000>;
 200                 audio-routing =
 201                         "MIC_IN", "Mic Jack",
 202                         "Mic Jack", "Mic Bias",
 203                         "Headphone Jack", "HP_OUT";
 204                 mux-int-port = <2>;
 205                 mux-ext-port = <3>;
 206         };
 207
 208         usbphy1: usbphy1 {
 209                 compatible = "usb-nop-xceiv";
 210                 pinctrl-names = "default";
 211                 pinctrl-0 = <&pinctrl_usbh1reg>;
 212                 clocks = <&clk_usb>;
 213                 clock-names = "main_clk";
 214                 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
 215                 vcc-supply = <&vusb_reg>;
 216                 #phy-cells = <0>;
 217         };
 218 };
 219
 220 &audmux {
 221         pinctrl-names = "default";
 222         pinctrl-0 = <&pinctrl_audmux>;
 223         status = "okay";
 224 };
 225
 226 &ecspi1 {
 227         pinctrl-names = "default";
 228         pinctrl-0 = <&pinctrl_ecspi1>;
 229         cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
 230                    <&gpio4 25 GPIO_ACTIVE_LOW>;
 231         status = "okay";
 232
 233         pmic: mc13892@0 {
 234                 compatible = "fsl,mc13892";
 235                 pinctrl-names = "default";
 236                 pinctrl-0 = <&pinctrl_pmic>;
 237                 spi-max-frequency = <6000000>;
 238                 spi-cs-high;
 239                 reg = <0>;
 240                 interrupt-parent = <&gpio1>;
 241                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
 242                 fsl,mc13xxx-uses-adc;
 243                 fsl,mc13xxx-uses-rtc;
 244
 245                 regulators {
 246                         sw1_reg: sw1 {
 247                                 regulator-min-microvolt = <600000>;
 248                                 regulator-max-microvolt = <1375000>;
 249                                 regulator-boot-on;
 250                                 regulator-always-on;
 251                         };
 252
 253                         sw2_reg: sw2 {
 254                                 regulator-min-microvolt = <900000>;
 255                                 regulator-max-microvolt = <1850000>;
 256                                 regulator-boot-on;
 257                                 regulator-always-on;
 258                         };
 259
 260                         sw3_reg: sw3 {
 261                                 regulator-min-microvolt = <1100000>;
 262                                 regulator-max-microvolt = <1850000>;
 263                                 regulator-boot-on;
 264                                 regulator-always-on;
 265                         };
 266
 267                         sw4_reg: sw4 {
 268                                 regulator-min-microvolt = <1100000>;
 269                                 regulator-max-microvolt = <1850000>;
 270                                 regulator-boot-on;
 271                                 regulator-always-on;
 272                         };
 273
 274                         vpll_reg: vpll {
 275                                 regulator-min-microvolt = <1050000>;
 276                                 regulator-max-microvolt = <1800000>;
 277                                 regulator-boot-on;
 278                                 regulator-always-on;
 279                         };
 280
 281                         vdig_reg: vdig {
 282                                 regulator-min-microvolt = <1650000>;
 283                                 regulator-max-microvolt = <1650000>;
 284                                 regulator-boot-on;
 285                         };
 286
 287                         vsd_reg: vsd {
 288                                 regulator-min-microvolt = <1800000>;
 289                                 regulator-max-microvolt = <3150000>;
 290                         };
 291
 292                         vusb_reg: vusb {
 293                                 regulator-boot-on;
 294                         };
 295
 296                         vusb2_reg: vusb2 {
 297                                 regulator-min-microvolt = <2400000>;
 298                                 regulator-max-microvolt = <2775000>;
 299                                 regulator-boot-on;
 300                                 regulator-always-on;
 301                         };
 302
 303                         vvideo_reg: vvideo {
 304                                 regulator-min-microvolt = <2775000>;
 305                                 regulator-max-microvolt = <2775000>;
 306                         };
 307
 308                         vaudio_reg: vaudio {
 309                                 regulator-min-microvolt = <2300000>;
 310                                 regulator-max-microvolt = <3000000>;
 311                         };
 312
 313                         vcam_reg: vcam {
 314                                 regulator-min-microvolt = <2500000>;
 315                                 regulator-max-microvolt = <3000000>;
 316                         };
 317
 318                         vgen1_reg: vgen1 {
 319                                 regulator-min-microvolt = <1200000>;
 320                                 regulator-max-microvolt = <1200000>;
 321                         };
 322
 323                         vgen2_reg: vgen2 {
 324                                 regulator-min-microvolt = <1200000>;
 325                                 regulator-max-microvolt = <3150000>;
 326                                 regulator-always-on;
 327                         };
 328
 329                         vgen3_reg: vgen3 {
 330                                 regulator-min-microvolt = <1800000>;
 331                                 regulator-max-microvolt = <2900000>;
 332                                 regulator-always-on;
 333                         };
 334                 };
 335         };
 336
 337         flash: at45db321d@1 {
 338                 #address-cells = <1>;
 339                 #size-cells = <1>;
 340                 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
 341                 spi-max-frequency = <25000000>;
 342                 reg = <1>;
 343
 344                 partition@0 {
 345                         label = "U-Boot";
 346                         reg = <0x0 0x40000>;
 347                         read-only;
 348                 };
 349
 350                 partition@40000 {
 351                         label = "Kernel";
 352                         reg = <0x40000 0x3c0000>;
 353                 };
 354         };
 355 };
 356
 357 &esdhc1 {
 358         pinctrl-names = "default";
 359         pinctrl-0 = <&pinctrl_esdhc1>;
 360         cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 361         wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 362         status = "okay";
 363 };
 364
 365 &esdhc2 {
 366         pinctrl-names = "default";
 367         pinctrl-0 = <&pinctrl_esdhc2>;
 368         cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
 369         wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 370         status = "okay";
 371 };
 372
 373 &fec {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_fec>;
 376         phy-mode = "mii";
 377         phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
 378         phy-reset-duration = <1>;
 379         status = "okay";
 380 };
 381
 382 &i2c1 {
 383         pinctrl-names = "default";
 384         pinctrl-0 = <&pinctrl_i2c1>;
 385         status = "okay";
 386 };
 387
 388 &i2c2 {
 389         pinctrl-names = "default";
 390         pinctrl-0 = <&pinctrl_i2c2>;
 391         status = "okay";
 392
 393         sgtl5000: codec@a {
 394                 compatible = "fsl,sgtl5000";
 395                 reg = <0x0a>;
 396                 #sound-dai-cells = <0>;
 397                 clocks = <&clk_audio>;
 398                 VDDA-supply = <&vdig_reg>;
 399                 VDDIO-supply = <&vvideo_reg>;
 400         };
 401 };
 402
 403 &ipu_di0_disp1 {
 404         remote-endpoint = <&display0_in>;
 405 };
 406
 407 &ipu_di1_disp2 {
 408         remote-endpoint = <&display1_in>;
 409 };
 410
 411 &kpp {
 412         pinctrl-names = "default";
 413         pinctrl-0 = <&pinctrl_kpp>;
 414         linux,keymap = <
 415                 MATRIX_KEY(0, 0, KEY_UP)
 416                 MATRIX_KEY(0, 1, KEY_DOWN)
 417                 MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
 418                 MATRIX_KEY(0, 3, KEY_HOME)
 419                 MATRIX_KEY(1, 0, KEY_RIGHT)
 420                 MATRIX_KEY(1, 1, KEY_LEFT)
 421                 MATRIX_KEY(1, 2, KEY_ENTER)
 422                 MATRIX_KEY(1, 3, KEY_VOLUMEUP)
 423                 MATRIX_KEY(2, 0, KEY_F6)
 424                 MATRIX_KEY(2, 1, KEY_F8)
 425                 MATRIX_KEY(2, 2, KEY_F9)
 426                 MATRIX_KEY(2, 3, KEY_F10)
 427                 MATRIX_KEY(3, 0, KEY_F1)
 428                 MATRIX_KEY(3, 1, KEY_F2)
 429                 MATRIX_KEY(3, 2, KEY_F3)
 430                 MATRIX_KEY(3, 3, KEY_POWER)
 431         >;
 432         status = "okay";
 433 };
 434
 435 &pmu {
 436         secure-reg-access;
 437 };
 438
 439 &ssi2 {
 440         status = "okay";
 441 };
 442
 443 &uart1 {
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&pinctrl_uart1>;
 446         uart-has-rtscts;
 447         status = "okay";
 448 };
 449
 450 &uart2 {
 451         pinctrl-names = "default";
 452         pinctrl-0 = <&pinctrl_uart2>;
 453         status = "okay";
 454 };
 455
 456 &uart3 {
 457         pinctrl-names = "default";
 458         pinctrl-0 = <&pinctrl_uart3>;
 459         uart-has-rtscts;
 460         status = "okay";
 461 };
 462
 463 &usbh1 {
 464         pinctrl-names = "default";
 465         pinctrl-0 = <&pinctrl_usbh1>;
 466         vbus-supply = <&reg_hub_reset>;
 467         fsl,usbphy = <&usbphy1>;
 468         phy_type = "ulpi";
 469         status = "okay";
 470 };
 471
 472 &usbphy0 {
 473         vcc-supply = <&vusb_reg>;
 474 };
 475
 476 &usbotg {
 477         dr_mode = "otg";
 478         disable-over-current;
 479         phy_type = "utmi_wide";
 480         status = "okay";
 481 };
 482
 483 &iomuxc {
 484         imx51-babbage {
 485                 pinctrl_audmux: audmuxgrp {
 486                         fsl,pins = <
 487                                 MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
 488                                 MX51_PAD_AUD3_BB_RXD__AUD3_RXD          0x80000000
 489                                 MX51_PAD_AUD3_BB_CK__AUD3_TXC           0x80000000
 490                                 MX51_PAD_AUD3_BB_FS__AUD3_TXFS          0x80000000
 491                         >;
 492                 };
 493
 494                 pinctrl_clk26mhz_audio: clk26mhzaudiocgrp {
 495                         fsl,pins = <
 496                                 MX51_PAD_CSPI1_RDY__GPIO4_26            0x85
 497                         >;
 498                 };
 499
 500                 pinctrl_clk26mhz_osc: clk26mhzoscgrp {
 501                         fsl,pins = <
 502                                 MX51_PAD_DI1_PIN12__GPIO3_1             0x85
 503                         >;
 504                 };
 505
 506                 pinctrl_clk26mhz_usb: clk26mhzusbgrp {
 507                         fsl,pins = <
 508                                 MX51_PAD_EIM_D17__GPIO2_1               0x85
 509                         >;
 510                 };
 511
 512                 pinctrl_ecspi1: ecspi1grp {
 513                         fsl,pins = <
 514                                 MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
 515                                 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
 516                                 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
 517                                 MX51_PAD_CSPI1_SS0__GPIO4_24            0x85 /* CS0 */
 518                                 MX51_PAD_CSPI1_SS1__GPIO4_25            0x85 /* CS1 */
 519                         >;
 520                 };
 521
 522                 pinctrl_esdhc1: esdhc1grp {
 523                         fsl,pins = <
 524                                 MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
 525                                 MX51_PAD_SD1_CLK__SD1_CLK               0x20d5
 526                                 MX51_PAD_SD1_DATA0__SD1_DATA0           0x20d5
 527                                 MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
 528                                 MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
 529                                 MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
 530                                 MX51_PAD_GPIO1_0__GPIO1_0               0x100
 531                                 MX51_PAD_GPIO1_1__GPIO1_1               0x100
 532                         >;
 533                 };
 534
 535                 pinctrl_esdhc2: esdhc2grp {
 536                         fsl,pins = <
 537                                 MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
 538                                 MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
 539                                 MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
 540                                 MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
 541                                 MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
 542                                 MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
 543                                 MX51_PAD_GPIO1_5__GPIO1_5               0x100 /* WP */
 544                                 MX51_PAD_GPIO1_6__GPIO1_6               0x100 /* CD */
 545                         >;
 546                 };
 547
 548                 pinctrl_fec: fecgrp {
 549                         fsl,pins = <
 550                                 MX51_PAD_EIM_EB2__FEC_MDIO              0x000001f5
 551                                 MX51_PAD_EIM_EB3__FEC_RDATA1            0x00000085
 552                                 MX51_PAD_EIM_CS2__FEC_RDATA2            0x00000085
 553                                 MX51_PAD_EIM_CS3__FEC_RDATA3            0x00000085
 554                                 MX51_PAD_EIM_CS4__FEC_RX_ER             0x00000180
 555                                 MX51_PAD_EIM_CS5__FEC_CRS               0x00000180
 556                                 MX51_PAD_NANDF_RB2__FEC_COL             0x00000180
 557                                 MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x00000180
 558                                 MX51_PAD_NANDF_D9__FEC_RDATA0           0x00002180
 559                                 MX51_PAD_NANDF_D8__FEC_TDATA0           0x00002004
 560                                 MX51_PAD_NANDF_CS2__FEC_TX_ER           0x00002004
 561                                 MX51_PAD_NANDF_CS3__FEC_MDC             0x00002004
 562                                 MX51_PAD_NANDF_CS4__FEC_TDATA1          0x00002004
 563                                 MX51_PAD_NANDF_CS5__FEC_TDATA2          0x00002004
 564                                 MX51_PAD_NANDF_CS6__FEC_TDATA3          0x00002004
 565                                 MX51_PAD_NANDF_CS7__FEC_TX_EN           0x00002004
 566                                 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x00002180
 567                                 MX51_PAD_NANDF_D11__FEC_RX_DV           0x000020a4
 568                                 MX51_PAD_EIM_A20__GPIO2_14              0x00000085 /* Phy Reset */
 569                         >;
 570                 };
 571
 572                 pinctrl_gpio_keys: gpiokeysgrp {
 573                         fsl,pins = <
 574                                 MX51_PAD_EIM_A27__GPIO2_21              0x5
 575                         >;
 576                 };
 577
 578                 pinctrl_gpio_leds: gpioledsgrp {
 579                         fsl,pins = <
 580                                 MX51_PAD_EIM_D22__GPIO2_6               0x80000000
 581                         >;
 582                 };
 583
 584                 pinctrl_i2c1: i2c1grp {
 585                         fsl,pins = <
 586                                 MX51_PAD_EIM_D19__I2C1_SCL              0x400001ed
 587                                 MX51_PAD_EIM_D16__I2C1_SDA              0x400001ed
 588                         >;
 589                 };
 590
 591                 pinctrl_i2c2: i2c2grp {
 592                         fsl,pins = <
 593                                 MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
 594                                 MX51_PAD_KEY_COL5__I2C2_SDA             0x400001ed
 595                         >;
 596                 };
 597
 598                 pinctrl_ipu_disp1: ipudisp1grp {
 599                         fsl,pins = <
 600                                 MX51_PAD_DISP1_DAT0__DISP1_DAT0         0x5
 601                                 MX51_PAD_DISP1_DAT1__DISP1_DAT1         0x5
 602                                 MX51_PAD_DISP1_DAT2__DISP1_DAT2         0x5
 603                                 MX51_PAD_DISP1_DAT3__DISP1_DAT3         0x5
 604                                 MX51_PAD_DISP1_DAT4__DISP1_DAT4         0x5
 605                                 MX51_PAD_DISP1_DAT5__DISP1_DAT5         0x5
 606                                 MX51_PAD_DISP1_DAT6__DISP1_DAT6         0x5
 607                                 MX51_PAD_DISP1_DAT7__DISP1_DAT7         0x5
 608                                 MX51_PAD_DISP1_DAT8__DISP1_DAT8         0x5
 609                                 MX51_PAD_DISP1_DAT9__DISP1_DAT9         0x5
 610                                 MX51_PAD_DISP1_DAT10__DISP1_DAT10       0x5
 611                                 MX51_PAD_DISP1_DAT11__DISP1_DAT11       0x5
 612                                 MX51_PAD_DISP1_DAT12__DISP1_DAT12       0x5
 613                                 MX51_PAD_DISP1_DAT13__DISP1_DAT13       0x5
 614                                 MX51_PAD_DISP1_DAT14__DISP1_DAT14       0x5
 615                                 MX51_PAD_DISP1_DAT15__DISP1_DAT15       0x5
 616                                 MX51_PAD_DISP1_DAT16__DISP1_DAT16       0x5
 617                                 MX51_PAD_DISP1_DAT17__DISP1_DAT17       0x5
 618                                 MX51_PAD_DISP1_DAT18__DISP1_DAT18       0x5
 619                                 MX51_PAD_DISP1_DAT19__DISP1_DAT19       0x5
 620                                 MX51_PAD_DISP1_DAT20__DISP1_DAT20       0x5
 621                                 MX51_PAD_DISP1_DAT21__DISP1_DAT21       0x5
 622                                 MX51_PAD_DISP1_DAT22__DISP1_DAT22       0x5
 623                                 MX51_PAD_DISP1_DAT23__DISP1_DAT23       0x5
 624                                 MX51_PAD_DI1_PIN2__DI1_PIN2             0x5
 625                                 MX51_PAD_DI1_PIN3__DI1_PIN3             0x5
 626                         >;
 627                 };
 628
 629                 pinctrl_ipu_disp2: ipudisp2grp {
 630                         fsl,pins = <
 631                                 MX51_PAD_DISP2_DAT0__DISP2_DAT0         0x5
 632                                 MX51_PAD_DISP2_DAT1__DISP2_DAT1         0x5
 633                                 MX51_PAD_DISP2_DAT2__DISP2_DAT2         0x5
 634                                 MX51_PAD_DISP2_DAT3__DISP2_DAT3         0x5
 635                                 MX51_PAD_DISP2_DAT4__DISP2_DAT4         0x5
 636                                 MX51_PAD_DISP2_DAT5__DISP2_DAT5         0x5
 637                                 MX51_PAD_DISP2_DAT6__DISP2_DAT6         0x5
 638                                 MX51_PAD_DISP2_DAT7__DISP2_DAT7         0x5
 639                                 MX51_PAD_DISP2_DAT8__DISP2_DAT8         0x5
 640                                 MX51_PAD_DISP2_DAT9__DISP2_DAT9         0x5
 641                                 MX51_PAD_DISP2_DAT10__DISP2_DAT10       0x5
 642                                 MX51_PAD_DISP2_DAT11__DISP2_DAT11       0x5
 643                                 MX51_PAD_DISP2_DAT12__DISP2_DAT12       0x5
 644                                 MX51_PAD_DISP2_DAT13__DISP2_DAT13       0x5
 645                                 MX51_PAD_DISP2_DAT14__DISP2_DAT14       0x5
 646                                 MX51_PAD_DISP2_DAT15__DISP2_DAT15       0x5
 647                                 MX51_PAD_DI2_PIN2__DI2_PIN2             0x5
 648                                 MX51_PAD_DI2_PIN3__DI2_PIN3             0x5
 649                                 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     0x5
 650                                 MX51_PAD_DI_GP4__DI2_PIN15              0x5
 651                         >;
 652                 };
 653
 654                 pinctrl_kpp: kppgrp {
 655                         fsl,pins = <
 656                                 MX51_PAD_KEY_ROW0__KEY_ROW0             0xe0
 657                                 MX51_PAD_KEY_ROW1__KEY_ROW1             0xe0
 658                                 MX51_PAD_KEY_ROW2__KEY_ROW2             0xe0
 659                                 MX51_PAD_KEY_ROW3__KEY_ROW3             0xe0
 660                                 MX51_PAD_KEY_COL0__KEY_COL0             0xe8
 661                                 MX51_PAD_KEY_COL1__KEY_COL1             0xe8
 662                                 MX51_PAD_KEY_COL2__KEY_COL2             0xe8
 663                                 MX51_PAD_KEY_COL3__KEY_COL3             0xe8
 664                         >;
 665                 };
 666
 667                 pinctrl_pmic: pmicgrp {
 668                         fsl,pins = <
 669                                 MX51_PAD_GPIO1_8__GPIO1_8               0xe5 /* IRQ */
 670                         >;
 671                 };
 672
 673                 pinctrl_uart1: uart1grp {
 674                         fsl,pins = <
 675                                 MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
 676                                 MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
 677                                 MX51_PAD_UART1_RTS__UART1_RTS           0x1c5
 678                                 MX51_PAD_UART1_CTS__UART1_CTS           0x1c5
 679                         >;
 680                 };
 681
 682                 pinctrl_uart2: uart2grp {
 683                         fsl,pins = <
 684                                 MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
 685                                 MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
 686                         >;
 687                 };
 688
 689                 pinctrl_uart3: uart3grp {
 690                         fsl,pins = <
 691                                 MX51_PAD_EIM_D25__UART3_RXD             0x1c5
 692                                 MX51_PAD_EIM_D26__UART3_TXD             0x1c5
 693                                 MX51_PAD_EIM_D27__UART3_RTS             0x1c5
 694                                 MX51_PAD_EIM_D24__UART3_CTS             0x1c5
 695                         >;
 696                 };
 697
 698                 pinctrl_usbh1: usbh1grp {
 699                         fsl,pins = <
 700                                 MX51_PAD_USBH1_CLK__USBH1_CLK           0x80000000
 701                                 MX51_PAD_USBH1_DIR__USBH1_DIR           0x80000000
 702                                 MX51_PAD_USBH1_NXT__USBH1_NXT           0x80000000
 703                                 MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x80000000
 704                                 MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x80000000
 705                                 MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x80000000
 706                                 MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x80000000
 707                                 MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x80000000
 708                                 MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x80000000
 709                                 MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x80000000
 710                                 MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x80000000
 711                         >;
 712                 };
 713
 714                 pinctrl_usbh1reg: usbh1reggrp {
 715                         fsl,pins = <
 716                                 MX51_PAD_EIM_D21__GPIO2_5               0x85
 717                         >;
 718                 };
 719
 720                 pinctrl_usbotgreg: usbotgreggrp {
 721                         fsl,pins = <
 722                                 MX51_PAD_GPIO1_7__GPIO1_7               0x85
 723                         >;
 724                 };
 725         };
 726 };