WIP FPC-III support
[linux/fpc-iii.git] / arch / arm / boot / dts / imx6q-dhcom-pdk2.dts
bloba685b1c3208f31d1318fa945301dd9b8c8b289ad
1 // SPDX-License-Identifier: (GPL-2.0+)
2 /*
3  * Copyright (C) 2015 DH electronics GmbH
4  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
5  */
7 /dts-v1/;
9 #include "imx6q-dhcom-som.dtsi"
11 / {
12         model = "Freescale i.MX6 Quad DHCOM Premium Developer Kit (2)";
13         compatible = "dh,imx6q-dhcom-pdk2", "dh,imx6q-dhcom-som", "fsl,imx6q";
15         chosen {
16                 stdout-path = &uart1;
17         };
19         clk_ext_audio_codec: clock-codec {
20                 compatible = "fixed-clock";
21                 #clock-cells = <0>;
22                 clock-frequency = <24000000>;
23         };
25         display_bl: display-bl {
26                 compatible = "pwm-backlight";
27                 pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>;
28                 brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>;
29                 default-brightness-level = <8>;
30                 enable-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
31                 status = "okay";
32         };
34         lcd_display: disp0 {
35                 compatible = "fsl,imx-parallel-display";
36                 #address-cells = <1>;
37                 #size-cells = <0>;
38                 interface-pix-fmt = "rgb24";
39                 pinctrl-names = "default";
40                 pinctrl-0 = <&pinctrl_ipu1_lcdif>;
41                 status = "okay";
43                 port@0 {
44                         reg = <0>;
46                         lcd_display_in: endpoint {
47                                 remote-endpoint = <&ipu1_di0_disp0>;
48                         };
49                 };
51                 port@1 {
52                         reg = <1>;
54                         lcd_display_out: endpoint {
55                                 remote-endpoint = <&lcd_panel_in>;
56                         };
57                 };
58         };
60         panel {
61                 compatible = "edt,etm0700g0edh6";
62                 ddc-i2c-bus = <&i2c2>;
63                 backlight = <&display_bl>;
65                 port {
66                         lcd_panel_in: endpoint {
67                                 remote-endpoint = <&lcd_display_out>;
68                         };
69                 };
70         };
72         sound {
73                 compatible = "fsl,imx-audio-sgtl5000";
74                 model = "imx-sgtl5000";
75                 ssi-controller = <&ssi1>;
76                 audio-codec = <&sgtl5000>;
77                 audio-routing =
78                         "MIC_IN", "Mic Jack",
79                         "Mic Jack", "Mic Bias",
80                         "LINE_IN", "Line In Jack",
81                         "Headphone Jack", "HP_OUT";
82                 mux-int-port = <1>;
83                 mux-ext-port = <3>;
84         };
87 &audmux {
88         pinctrl-names = "default";
89         pinctrl-0 = <&pinctrl_audmux_ext>;
90         status = "okay";
93 &can1 {
94         status = "okay";
97 &can2 {
98         status = "disabled";
101 &hdmi {
102         ddc-i2c-bus = <&i2c2>;
103         status = "okay";
106 &i2c2 {
107         sgtl5000: codec@a {
108                 compatible = "fsl,sgtl5000";
109                 reg = <0x0a>;
110                 #sound-dai-cells = <0>;
111                 clocks = <&clk_ext_audio_codec>;
112                 VDDA-supply = <&reg_3p3v>;
113                 VDDIO-supply = <&sw2_reg>;
114         };
116         touchscreen@38 {
117                 pinctrl-names = "default";
118                 pinctrl-0 = <&pinctrl_touchscreen>;
119                 compatible = "edt,edt-ft5406";
120                 reg = <0x38>;
121                 interrupt-parent = <&gpio4>;
122                 interrupts = <5 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */
123         };
126 &iomuxc {
127         pinctrl-names = "default";
128         pinctrl-0 = <&pinctrl_hog_base &pinctrl_hog>;
130         pinctrl_hog: hog-grp {
131                 fsl,pins = <
132                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x400120b0
133                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x400120b0
134                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x400120b0
135                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x400120b0
136                         MX6QDL_PAD_DI0_PIN4__GPIO4_IO20         0x400120b0
137                         MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x120b0
138                         MX6QDL_PAD_KEY_COL1__GPIO4_IO08         0x400120b0
139                         MX6QDL_PAD_NANDF_CS1__GPIO6_IO14        0x400120b0
140                         MX6QDL_PAD_NANDF_CS2__GPIO6_IO15        0x400120b0
141                         MX6QDL_PAD_KEY_ROW1__GPIO4_IO09         0x400120b0
142                         MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x400120b0
143                         MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x400120b0
144                         MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21       0x400120b0
145                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x400120b0
146                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x400120b0
147                         MX6QDL_PAD_SD1_DAT0__GPIO1_IO16         0x400120b0
148                         MX6QDL_PAD_SD1_DAT1__GPIO1_IO17         0x400120b0
149                         MX6QDL_PAD_SD1_DAT2__GPIO1_IO19         0x400120b0
150                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x400120b0
151                         MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18      0x400120b0
152                         MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19        0x400120b0
153                         MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x400120b0
154                 >;
155         };
157         pinctrl_audmux_ext: audmux-ext-grp {
158                 fsl,pins = <
159                         MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x130b0
160                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
161                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x110b0
162                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
163                 >;
164         };
166         pinctrl_enet_1G: enet-1G-grp {
167                 fsl,pins = <
168                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b0
169                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x100b0
170                         MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x100b0
171                         MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x100b0
172                         MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x100b0
173                         MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x100b0
174                         MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x100b0
175                         MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x100b0
176                         MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x100b0
177                         MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
178                         MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
179                         MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
180                         MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
181                         MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
182                         MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
183                         MX6QDL_PAD_EIM_D29__GPIO3_IO29          0x000b0
184                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x000b1
185                         MX6QDL_PAD_EIM_D26__GPIO3_IO26          0x000b1
186                 >;
187         };
189         pinctrl_ipu1_lcdif: ipu1-lcdif-grp {
190                 fsl,pins = <
191                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x38
192                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0x38
193                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x38
194                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x38
195                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x38
196                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x38
197                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x38
198                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x38
199                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x38
200                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x38
201                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x38
202                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x38
203                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x38
204                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x38
205                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x38
206                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x38
207                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x38
208                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x38
209                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x38
210                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x38
211                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x38
212                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x38
213                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x38
214                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x38
215                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x38
216                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x38
217                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x38
218                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x38
219                         MX6QDL_PAD_EIM_D27__GPIO3_IO27                  0x120b0
220                 >;
221         };
223         pinctrl_pwm1: pwm1-grp {
224                 fsl,pins = <
225                         MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
226                 >;
227         };
229         pinctrl_touchscreen: touchscreen-grp {
230                 fsl,pins = <
231                         MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b1
232                 >;
233         };
235         pinctrl_pcie: pcie-grp {
236                 fsl,pins = <
237                         MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20     0x1b0b1
238                 >;
239         };
242 &ipu1_di0_disp0 {
243         remote-endpoint = <&lcd_display_in>;
246 &pcie {
247         pinctrl-names = "default";
248         pinctrl-0 = <&pinctrl_pcie>;
249         reset-gpio = <&gpio6 14 GPIO_ACTIVE_LOW>;
250         status = "okay";
253 &pwm1 {
254         pinctrl-names = "default";
255         pinctrl-0 = <&pinctrl_pwm1>;
256         status = "okay";
259 &ssi1 {
260         status = "okay";
263 &sata {
264         status = "okay";
267 &usdhc3 {
268         status = "okay";