| blob | 5277e390329126313549b2021fd1d1f447d995bc |
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2013 Freescale Semiconductor, Inc.
5 #include <dt-bindings/interrupt-controller/irq.h>
6 #include "imx6q-pinfunc.h"
7 #include "imx6qdl.dtsi"
9 / {
10 aliases {
11 ipu1 = &ipu2;
12 spi4 = &ecspi5;
13 };
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu0: cpu@0 {
20 compatible = "arm,cortex-a9";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 operating-points = <
25 /* kHz uV */
26 1200000 1275000
27 996000 1250000
28 852000 1250000
29 792000 1175000
30 396000 975000
31 >;
32 fsl,soc-operating-points = <
33 /* ARM kHz SOC-PU uV */
34 1200000 1275000
35 996000 1250000
36 852000 1250000
37 792000 1175000
38 396000 1175000
39 >;
40 clock-latency = <61036>; /* two CLK32 periods */
41 #cooling-cells = <2>;
42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
47 clock-names = "arm", "pll2_pfd2_396m", "step",
48 "pll1_sw", "pll1_sys";
49 arm-supply = <®_arm>;
50 pu-supply = <®_pu>;
51 soc-supply = <®_soc>;
52 nvmem-cells = <&cpu_speed_grade>;
53 nvmem-cell-names = "speed_grade";
54 };
56 cpu1: cpu@1 {
57 compatible = "arm,cortex-a9";
58 device_type = "cpu";
59 reg = <1>;
60 next-level-cache = <&L2>;
61 operating-points = <
62 /* kHz uV */
63 1200000 1275000
64 996000 1250000
65 852000 1250000
66 792000 1175000
67 396000 975000
68 >;
69 fsl,soc-operating-points = <
70 /* ARM kHz SOC-PU uV */
71 1200000 1275000
72 996000 1250000
73 852000 1250000
74 792000 1175000
75 396000 1175000
76 >;
77 clock-latency = <61036>; /* two CLK32 periods */
78 #cooling-cells = <2>;
79 clocks = <&clks IMX6QDL_CLK_ARM>,
80 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
81 <&clks IMX6QDL_CLK_STEP>,
82 <&clks IMX6QDL_CLK_PLL1_SW>,
83 <&clks IMX6QDL_CLK_PLL1_SYS>;
84 clock-names = "arm", "pll2_pfd2_396m", "step",
85 "pll1_sw", "pll1_sys";
86 arm-supply = <®_arm>;
87 pu-supply = <®_pu>;
88 soc-supply = <®_soc>;
89 };
91 cpu2: cpu@2 {
92 compatible = "arm,cortex-a9";
93 device_type = "cpu";
94 reg = <2>;
95 next-level-cache = <&L2>;
96 operating-points = <
97 /* kHz uV */
98 1200000 1275000
99 996000 1250000
100 852000 1250000
101 792000 1175000
102 396000 975000
103 >;
104 fsl,soc-operating-points = <
105 /* ARM kHz SOC-PU uV */
106 1200000 1275000
107 996000 1250000
108 852000 1250000
109 792000 1175000
110 396000 1175000
111 >;
112 clock-latency = <61036>; /* two CLK32 periods */
113 #cooling-cells = <2>;
114 clocks = <&clks IMX6QDL_CLK_ARM>,
115 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
116 <&clks IMX6QDL_CLK_STEP>,
117 <&clks IMX6QDL_CLK_PLL1_SW>,
118 <&clks IMX6QDL_CLK_PLL1_SYS>;
119 clock-names = "arm", "pll2_pfd2_396m", "step",
120 "pll1_sw", "pll1_sys";
121 arm-supply = <®_arm>;
122 pu-supply = <®_pu>;
123 soc-supply = <®_soc>;
124 };
126 cpu3: cpu@3 {
127 compatible = "arm,cortex-a9";
128 device_type = "cpu";
129 reg = <3>;
130 next-level-cache = <&L2>;
131 operating-points = <
132 /* kHz uV */
133 1200000 1275000
134 996000 1250000
135 852000 1250000
136 792000 1175000
137 396000 975000
138 >;
139 fsl,soc-operating-points = <
140 /* ARM kHz SOC-PU uV */
141 1200000 1275000
142 996000 1250000
143 852000 1250000
144 792000 1175000
145 396000 1175000
146 >;
147 clock-latency = <61036>; /* two CLK32 periods */
148 #cooling-cells = <2>;
149 clocks = <&clks IMX6QDL_CLK_ARM>,
150 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
151 <&clks IMX6QDL_CLK_STEP>,
152 <&clks IMX6QDL_CLK_PLL1_SW>,
153 <&clks IMX6QDL_CLK_PLL1_SYS>;
154 clock-names = "arm", "pll2_pfd2_396m", "step",
155 "pll1_sw", "pll1_sys";
156 arm-supply = <®_arm>;
157 pu-supply = <®_pu>;
158 soc-supply = <®_soc>;
159 };
160 };
162 soc {
163 ocram: sram@900000 {
164 compatible = "mmio-sram";
165 reg = <0x00900000 0x40000>;
166 clocks = <&clks IMX6QDL_CLK_OCRAM>;
167 };
169 bus@2000000 { /* AIPS1 */
170 spba-bus@2000000 {
171 ecspi5: spi@2018000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x02018000 0x4000>;
176 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&clks IMX6Q_CLK_ECSPI5>,
178 <&clks IMX6Q_CLK_ECSPI5>;
179 clock-names = "ipg", "per";
180 dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
181 dma-names = "rx", "tx";
182 status = "disabled";
183 };
184 };
185 };
187 sata: sata@2200000 {
188 compatible = "fsl,imx6q-ahci";
189 reg = <0x02200000 0x4000>;
190 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
191 clocks = <&clks IMX6QDL_CLK_SATA>,
192 <&clks IMX6QDL_CLK_SATA_REF_100M>,
193 <&clks IMX6QDL_CLK_AHB>;
194 clock-names = "sata", "sata_ref", "ahb";
195 status = "disabled";
196 };
198 gpu_vg: gpu@2204000 {
199 compatible = "vivante,gc";
200 reg = <0x02204000 0x4000>;
201 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
203 <&clks IMX6QDL_CLK_GPU2D_CORE>;
204 clock-names = "bus", "core";
205 power-domains = <&pd_pu>;
206 #cooling-cells = <2>;
207 };
209 ipu2: ipu@2800000 {
210 #address-cells = <1>;
211 #size-cells = <0>;
212 compatible = "fsl,imx6q-ipu";
213 reg = <0x02800000 0x400000>;
214 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
215 <0 7 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clks IMX6QDL_CLK_IPU2>,
217 <&clks IMX6QDL_CLK_IPU2_DI0>,
218 <&clks IMX6QDL_CLK_IPU2_DI1>;
219 clock-names = "bus", "di0", "di1";
220 resets = <&src 4>;
222 ipu2_csi0: port@0 {
223 reg = <0>;
225 ipu2_csi0_from_mipi_vc2: endpoint {
226 remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
227 };
228 };
230 ipu2_csi1: port@1 {
231 reg = <1>;
233 ipu2_csi1_from_ipu2_csi1_mux: endpoint {
234 remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
235 };
236 };
238 ipu2_di0: port@2 {
239 #address-cells = <1>;
240 #size-cells = <0>;
241 reg = <2>;
243 ipu2_di0_disp0: endpoint@0 {
244 reg = <0>;
245 };
247 ipu2_di0_hdmi: endpoint@1 {
248 reg = <1>;
249 remote-endpoint = <&hdmi_mux_2>;
250 };
252 ipu2_di0_mipi: endpoint@2 {
253 reg = <2>;
254 remote-endpoint = <&mipi_mux_2>;
255 };
257 ipu2_di0_lvds0: endpoint@3 {
258 reg = <3>;
259 remote-endpoint = <&lvds0_mux_2>;
260 };
262 ipu2_di0_lvds1: endpoint@4 {
263 reg = <4>;
264 remote-endpoint = <&lvds1_mux_2>;
265 };
266 };
268 ipu2_di1: port@3 {
269 #address-cells = <1>;
270 #size-cells = <0>;
271 reg = <3>;
273 ipu2_di1_hdmi: endpoint@1 {
274 reg = <1>;
275 remote-endpoint = <&hdmi_mux_3>;
276 };
278 ipu2_di1_mipi: endpoint@2 {
279 reg = <2>;
280 remote-endpoint = <&mipi_mux_3>;
281 };
283 ipu2_di1_lvds0: endpoint@3 {
284 reg = <3>;
285 remote-endpoint = <&lvds0_mux_3>;
286 };
288 ipu2_di1_lvds1: endpoint@4 {
289 reg = <4>;
290 remote-endpoint = <&lvds1_mux_3>;
291 };
292 };
293 };
294 };
296 capture-subsystem {
297 compatible = "fsl,imx-capture-subsystem";
298 ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
299 };
301 display-subsystem {
302 compatible = "fsl,imx-display-subsystem";
303 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
304 };
305 };
307 &gpio1 {
308 gpio-ranges = <&iomuxc 0 136 2>, <&iomuxc 2 141 1>, <&iomuxc 3 139 1>,
309 <&iomuxc 4 142 2>, <&iomuxc 6 140 1>, <&iomuxc 7 144 2>,
310 <&iomuxc 9 138 1>, <&iomuxc 10 213 3>, <&iomuxc 13 20 1>,
311 <&iomuxc 14 19 1>, <&iomuxc 15 21 1>, <&iomuxc 16 208 1>,
312 <&iomuxc 17 207 1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
313 <&iomuxc 22 116 10>;
314 };
316 &gpio2 {
317 gpio-ranges = <&iomuxc 0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
318 <&iomuxc 31 44 1>;
319 };
321 &gpio3 {
322 gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
323 };
325 &gpio4 {
326 gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
327 };
329 &gpio5 {
330 gpio-ranges = <&iomuxc 0 85 1>, <&iomuxc 2 34 1>, <&iomuxc 4 53 1>,
331 <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
332 };
334 &gpio6 {
335 gpio-ranges = <&iomuxc 0 164 6>, <&iomuxc 6 54 1>, <&iomuxc 7 181 5>,
336 <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19 22 12>,
337 <&iomuxc 31 86 1>;
338 };
340 &gpio7 {
341 gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
342 };
344 &gpr {
345 ipu1_csi0_mux {
346 compatible = "video-mux";
347 mux-controls = <&mux 0>;
348 #address-cells = <1>;
349 #size-cells = <0>;
351 port@0 {
352 reg = <0>;
354 ipu1_csi0_mux_from_mipi_vc0: endpoint {
355 remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
356 };
357 };
359 port@1 {
360 reg = <1>;
362 ipu1_csi0_mux_from_parallel_sensor: endpoint {
363 };
364 };
366 port@2 {
367 reg = <2>;
369 ipu1_csi0_mux_to_ipu1_csi0: endpoint {
370 remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
371 };
372 };
373 };
375 ipu2_csi1_mux {
376 compatible = "video-mux";
377 mux-controls = <&mux 1>;
378 #address-cells = <1>;
379 #size-cells = <0>;
381 port@0 {
382 reg = <0>;
384 ipu2_csi1_mux_from_mipi_vc3: endpoint {
385 remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
386 };
387 };
389 port@1 {
390 reg = <1>;
392 ipu2_csi1_mux_from_parallel_sensor: endpoint {
393 };
394 };
396 port@2 {
397 reg = <2>;
399 ipu2_csi1_mux_to_ipu2_csi1: endpoint {
400 remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
401 };
402 };
403 };
404 };
406 &hdmi {
407 compatible = "fsl,imx6q-hdmi";
409 port@2 {
410 reg = <2>;
412 hdmi_mux_2: endpoint {
413 remote-endpoint = <&ipu2_di0_hdmi>;
414 };
415 };
417 port@3 {
418 reg = <3>;
420 hdmi_mux_3: endpoint {
421 remote-endpoint = <&ipu2_di1_hdmi>;
422 };
423 };
424 };
426 &iomuxc {
427 compatible = "fsl,imx6q-iomuxc";
428 };
430 &ipu1_csi1 {
431 ipu1_csi1_from_mipi_vc1: endpoint {
432 remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
433 };
434 };
436 &ldb {
437 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
438 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
439 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
440 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
441 clock-names = "di0_pll", "di1_pll",
442 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
443 "di0", "di1";
445 lvds-channel@0 {
446 port@2 {
447 reg = <2>;
449 lvds0_mux_2: endpoint {
450 remote-endpoint = <&ipu2_di0_lvds0>;
451 };
452 };
454 port@3 {
455 reg = <3>;
457 lvds0_mux_3: endpoint {
458 remote-endpoint = <&ipu2_di1_lvds0>;
459 };
460 };
461 };
463 lvds-channel@1 {
464 port@2 {
465 reg = <2>;
467 lvds1_mux_2: endpoint {
468 remote-endpoint = <&ipu2_di0_lvds1>;
469 };
470 };
472 port@3 {
473 reg = <3>;
475 lvds1_mux_3: endpoint {
476 remote-endpoint = <&ipu2_di1_lvds1>;
477 };
478 };
479 };
480 };
482 &mipi_csi {
483 port@1 {
484 reg = <1>;
486 mipi_vc0_to_ipu1_csi0_mux: endpoint {
487 remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
488 };
489 };
491 port@2 {
492 reg = <2>;
494 mipi_vc1_to_ipu1_csi1: endpoint {
495 remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
496 };
497 };
499 port@3 {
500 reg = <3>;
502 mipi_vc2_to_ipu2_csi0: endpoint {
503 remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
504 };
505 };
507 port@4 {
508 reg = <4>;
510 mipi_vc3_to_ipu2_csi1_mux: endpoint {
511 remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
512 };
513 };
514 };
516 &mipi_dsi {
517 ports {
518 port@2 {
519 reg = <2>;
521 mipi_mux_2: endpoint {
522 remote-endpoint = <&ipu2_di0_mipi>;
523 };
524 };
526 port@3 {
527 reg = <3>;
529 mipi_mux_3: endpoint {
530 remote-endpoint = <&ipu2_di1_mipi>;
531 };
532 };
533 };
534 };
536 &mux {
537 mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
538 <0x04 0x00100000>, /* MIPI_IPU2_MUX */
539 <0x0c 0x0000000c>, /* HDMI_MUX_CTL */
540 <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
541 <0x0c 0x00000300>, /* LVDS1_MUX_CTL */
542 <0x28 0x00000003>, /* DCIC1_MUX_CTL */
543 <0x28 0x0000000c>; /* DCIC2_MUX_CTL */
544 };
546 &vpu {
547 compatible = "fsl,imx6q-vpu", "cnm,coda960";
548 };