arch/arm/boot/dts/imx6qdl-aristainetos.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * support fot the imx6 based aristainetos board
   4  *
   5  * Copyright (C) 2014 Heiko Schocher <hs@denx.de>
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11
  12         reg_2p5v: regulator-2p5v {
  13                 compatible = "regulator-fixed";
  14                 regulator-name = "2P5V";
  15                 regulator-min-microvolt = <2500000>;
  16                 regulator-max-microvolt = <2500000>;
  17                 regulator-always-on;
  18         };
  19
  20         reg_3p3v: regulator-3p3v {
  21                 compatible = "regulator-fixed";
  22                 regulator-name = "3P3V";
  23                 regulator-min-microvolt = <3300000>;
  24                 regulator-max-microvolt = <3300000>;
  25                 regulator-always-on;
  26         };
  27
  28         reg_usbh1_vbus: regulator-usbh1-vbus {
  29                 compatible = "regulator-fixed";
  30                 enable-active-high;
  31                 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
  32                 pinctrl-names = "default";
  33                 pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>;
  34                 regulator-name = "usb_h1_vbus";
  35                 regulator-min-microvolt = <5000000>;
  36                 regulator-max-microvolt = <5000000>;
  37         };
  38
  39         reg_usbotg_vbus: regulator-usbotg-vbus {
  40                 compatible = "regulator-fixed";
  41                 enable-active-high;
  42                 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
  43                 pinctrl-names = "default";
  44                 pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>;
  45                 regulator-name = "usb_otg_vbus";
  46                 regulator-min-microvolt = <5000000>;
  47                 regulator-max-microvolt = <5000000>;
  48         };
  49 };
  50
  51 &audmux {
  52         pinctrl-names = "default";
  53         pinctrl-0 = <&pinctrl_audmux>;
  54         status = "okay";
  55 };
  56
  57 &can1 {
  58         pinctrl-names = "default";
  59         pinctrl-0 = <&pinctrl_flexcan1>;
  60         status = "okay";
  61 };
  62
  63 &can2 {
  64         pinctrl-names = "default";
  65         pinctrl-0 = <&pinctrl_flexcan2>;
  66         status = "okay";
  67 };
  68
  69 &i2c1 {
  70         clock-frequency = <100000>;
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_i2c1>;
  73         status = "okay";
  74
  75         tmp103: tmp103@71 {
  76                 compatible = "ti,tmp103";
  77                 reg = <0x71>;
  78         };
  79 };
  80
  81 &i2c3 {
  82         clock-frequency = <100000>;
  83         pinctrl-names = "default";
  84         pinctrl-0 = <&pinctrl_i2c3>;
  85         status = "okay";
  86
  87         rtc@68 {
  88                 compatible = "dallas,m41t00";
  89                 reg = <0x68>;
  90         };
  91 };
  92
  93 &ecspi4 {
  94         cs-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&pinctrl_ecspi4>;
  97         status = "okay";
  98
  99         flash: m25p80@0 {
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 compatible = "micron,n25q128a11", "jedec,spi-nor";
 103                 spi-max-frequency = <20000000>;
 104                 reg = <0>;
 105         };
 106 };
 107
 108 &fec {
 109         pinctrl-names = "default";
 110         pinctrl-0 = <&pinctrl_enet>;
 111         phy-mode = "rmii";
 112         phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 113         status = "okay";
 114 };
 115
 116 &gpmi {
 117         pinctrl-names = "default";
 118         pinctrl-0 = <&pinctrl_gpmi_nand>;
 119         status = "okay";
 120 };
 121
 122 &pcie {
 123         status = "okay";
 124 };
 125
 126 &uart2 {
 127         pinctrl-names = "default";
 128         pinctrl-0 = <&pinctrl_uart2>;
 129         status = "okay";
 130 };
 131
 132
 133 &uart4 {
 134         pinctrl-names = "default";
 135         pinctrl-0 = <&pinctrl_uart4>;
 136         uart-has-rtscts;
 137         status = "okay";
 138 };
 139
 140 &uart5 {
 141         pinctrl-names = "default";
 142         pinctrl-0 = <&pinctrl_uart5>;
 143         uart-has-rtscts;
 144         status = "okay";
 145 };
 146
 147 &usbh1 {
 148         vbus-supply = <&reg_usbh1_vbus>;
 149         dr_mode = "host";
 150         status = "okay";
 151 };
 152
 153 &usbotg {
 154         vbus-supply = <&reg_usbotg_vbus>;
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_usbotg>;
 157         disable-over-current;
 158         dr_mode = "host";
 159         status = "okay";
 160 };
 161
 162 &usdhc1 {
 163         pinctrl-names = "default";
 164         pinctrl-0 = <&pinctrl_usdhc1>;
 165         vmmc-supply = <&reg_3p3v>;
 166         cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
 167         status = "okay";
 168 };
 169
 170 &usdhc2 {
 171         pinctrl-names = "default";
 172         pinctrl-0 = <&pinctrl_usdhc2>;
 173         vmmc-supply = <&reg_3p3v>;
 174         cd-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
 175         status = "okay";
 176 };
 177
 178 &iomuxc {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>;
 181
 182         imx6qdl-aristainetos {
 183                 pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus {
 184                         fsl,pins = <MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0>;
 185                 };
 186
 187                 pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus {
 188                         fsl,pins = <MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0>;
 189                 };
 190
 191                 pinctrl_audmux: audmuxgrp {
 192                         fsl,pins = <
 193                                 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD  0x1b0b0
 194                                 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x1b0b0
 195                                 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD  0x1b0b0
 196                                 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
 197                         >;
 198                 };
 199
 200                 pinctrl_backlight: backlightgrp {
 201                         fsl,pins = <
 202                                 MX6QDL_PAD_GPIO_9__PWM1_OUT     0x1b0b0
 203                                 MX6QDL_PAD_SD4_DAT1__PWM3_OUT   0x1b0b0
 204                                 MX6QDL_PAD_GPIO_2__GPIO1_IO02   0x1b0b0
 205                         >;
 206                 };
 207
 208                 pinctrl_ecspi2: ecspi2grp {
 209                         fsl,pins = <
 210                                 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
 211                                 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
 212                                 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
 213                                 MX6QDL_PAD_EIM_D24__GPIO3_IO24  0x100b1
 214                         >;
 215                 };
 216
 217                 pinctrl_ecspi4: ecspi4grp {
 218                         fsl,pins = <
 219                                 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
 220                                 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
 221                                 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
 222                                 MX6QDL_PAD_EIM_D20__GPIO3_IO20  0x100b1
 223                                 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
 224                         >;
 225                 };
 226
 227                 pinctrl_enet: enetgrp {
 228                         fsl,pins = <
 229                                 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
 230                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO  0x1b0b0
 231                                 MX6QDL_PAD_ENET_MDC__ENET_MDC    0x1b0b0
 232                                 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
 233                                 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
 234                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN   0x1b0b0
 235                                 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER   0x1b0b0
 236                                 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
 237                                 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
 238                                 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN  0x1b0b0
 239                         >;
 240                 };
 241
 242                 pinctrl_flexcan1: flexcan1grp {
 243                         fsl,pins = <
 244                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 245                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 246                         >;
 247                 };
 248
 249                 pinctrl_flexcan2: flexcan2grp {
 250                         fsl,pins = <
 251                                 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX        0x1b0b0
 252                                 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX        0x1b0b0
 253                                 >;
 254                 };
 255
 256                 pinctrl_gpio: gpiogrp {
 257                         fsl,pins = <
 258                                 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
 259                                 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
 260                                 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
 261                                 MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0
 262                                 MX6QDL_PAD_GPIO_3__GPIO1_IO03   0x1b0b0
 263                                 MX6QDL_PAD_GPIO_4__GPIO1_IO04   0x1b0b0
 264                                 MX6QDL_PAD_GPIO_5__GPIO1_IO05   0x1b0b0
 265                                 MX6QDL_PAD_GPIO_6__GPIO1_IO06   0x1b0b0
 266                                 MX6QDL_PAD_GPIO_7__GPIO1_IO07   0x1b0b0
 267                                 MX6QDL_PAD_GPIO_8__GPIO1_IO08   0x1b0b0
 268                                 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
 269                         >;
 270                 };
 271
 272                 pinctrl_gpmi_nand: gpminandgrp {
 273                         fsl,pins = <
 274                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE     0xb0b1
 275                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE     0xb0b1
 276                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B   0xb0b1
 277                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
 278                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B   0xb0b1
 279                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B   0xb0b1
 280                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B      0xb0b1
 281                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B      0xb0b1
 282                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00   0xb0b1
 283                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01   0xb0b1
 284                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02   0xb0b1
 285                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03   0xb0b1
 286                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04   0xb0b1
 287                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05   0xb0b1
 288                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06   0xb0b1
 289                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07   0xb0b1
 290                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS      0x00b1
 291                         >;
 292                 };
 293
 294                 pinctrl_hog: hoggrp {
 295                         fsl,pins = <
 296                                 MX6QDL_PAD_EIM_D29__GPIO3_IO29   0x10
 297                         >;
 298                 };
 299
 300                 pinctrl_i2c1: i2c1grp {
 301                         fsl,pins = <
 302                                 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
 303                                 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
 304                         >;
 305                 };
 306
 307                 pinctrl_i2c2: i2c2grp {
 308                         fsl,pins = <
 309                                 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
 310                                 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
 311                         >;
 312                 };
 313
 314                 pinctrl_i2c3: i2c3grp {
 315                         fsl,pins = <
 316                                 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
 317                                 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
 318                         >;
 319                 };
 320
 321                 pinctrl_ipu_disp: ipudisp1grp {
 322                         fsl,pins = <
 323                                 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK      0x10
 324                                 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15            0x10
 325                                 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02             0x10
 326                                 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03             0x10
 327                                 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20                 0x20000
 328                                 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00        0x10
 329                                 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01        0x10
 330                                 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02        0x10
 331                                 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03        0x10
 332                                 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04        0x10
 333                                 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05        0x10
 334                                 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06        0x10
 335                                 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07        0x10
 336                                 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08        0x10
 337                                 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09        0x10
 338                                 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10       0x10
 339                                 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11       0x10
 340                                 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12       0x10
 341                                 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13       0x10
 342                                 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14       0x10
 343                                 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15       0x10
 344                                 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16       0x10
 345                                 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17       0x10
 346                                 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18       0x10
 347                                 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19       0x10
 348                                 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20       0x10
 349                                 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21       0x10
 350                                 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22       0x10
 351                                 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23       0x10
 352                                 >;
 353                 };
 354
 355                 pinctrl_uart2: uart2grp {
 356                         fsl,pins = <
 357                                 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
 358                                 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
 359                         >;
 360                 };
 361
 362                 pinctrl_uart4: uart4grp {
 363                         fsl,pins = <
 364                                 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
 365                                 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
 366                                 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
 367                                 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
 368                         >;
 369                 };
 370
 371                 pinctrl_uart5: uart5grp {
 372                         fsl,pins = <
 373                                 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
 374                                 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
 375                         >;
 376                 };
 377
 378                 pinctrl_usbotg: usbotggrp {
 379                         fsl,pins = <
 380                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
 381                         >;
 382                 };
 383
 384                 pinctrl_usdhc1: usdhc1grp {
 385                         fsl,pins = <
 386                                 MX6QDL_PAD_SD1_CMD__SD1_CMD    0x17059
 387                                 MX6QDL_PAD_SD1_CLK__SD1_CLK    0x10059
 388                                 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
 389                                 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
 390                                 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
 391                                 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
 392                                 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
 393                         >;
 394                 };
 395
 396                 pinctrl_usdhc2: usdhc2grp {
 397                         fsl,pins = <
 398                                 MX6QDL_PAD_SD2_CMD__SD2_CMD    0x17059
 399                                 MX6QDL_PAD_SD2_CLK__SD2_CLK    0x10059
 400                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
 401                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
 402                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
 403                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
 404                                 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
 405                         >;
 406                 };
 407         };
 408 };