arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
   4  */
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         model = "Phytec phyFLEX-i.MX6 Quad";
  10         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
  11
  12         memory@10000000 {
  13                 device_type = "memory";
  14                 reg = <0x10000000 0x80000000>;
  15         };
  16
  17         regulators {
  18                 compatible = "simple-bus";
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 reg_usb_otg_vbus: regulator@0 {
  23                         compatible = "regulator-fixed";
  24                         reg = <0>;
  25                         regulator-name = "usb_otg_vbus";
  26                         regulator-min-microvolt = <5000000>;
  27                         regulator-max-microvolt = <5000000>;
  28                         gpio = <&gpio4 15 0>;
  29                         enable-active-high;
  30                 };
  31
  32                 reg_usb_h1_vbus: regulator@1 {
  33                         compatible = "regulator-fixed";
  34                         reg = <1>;
  35                         regulator-name = "usb_h1_vbus";
  36                         regulator-min-microvolt = <5000000>;
  37                         regulator-max-microvolt = <5000000>;
  38                         gpio = <&gpio1 0 0>;
  39                         enable-active-high;
  40                 };
  41         };
  42
  43         gpio_leds: leds {
  44                 compatible = "gpio-leds";
  45
  46                 green {
  47                         label = "phyflex:green";
  48                         gpios = <&gpio1 30 0>;
  49                 };
  50
  51                 red {
  52                         label = "phyflex:red";
  53                         gpios = <&gpio2 31 0>;
  54                 };
  55         };
  56 };
  57
  58 &audmux {
  59         pinctrl-names = "default";
  60         pinctrl-0 = <&pinctrl_audmux>;
  61         status = "disabled";
  62 };
  63
  64 &can1 {
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_flexcan1>;
  67         status = "disabled";
  68 };
  69
  70 &ecspi3 {
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_ecspi3>;
  73         status = "okay";
  74         cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
  75
  76         som_flash: flash@0 {
  77                 compatible = "m25p80", "jedec,spi-nor";
  78                 spi-max-frequency = <20000000>;
  79                 reg = <0>;
  80         };
  81 };
  82
  83 &fec {
  84         pinctrl-names = "default";
  85         pinctrl-0 = <&pinctrl_enet>;
  86         phy-handle = <&ethphy>;
  87         phy-mode = "rgmii";
  88         phy-reset-duration = <10>; /* in msecs */
  89         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
  90         phy-supply = <&vdd_eth_io_reg>;
  91         status = "disabled";
  92
  93         fec_mdio: mdio {
  94                 #address-cells = <1>;
  95                 #size-cells = <0>;
  96
  97                 ethphy: ethernet-phy@0 {
  98                         compatible = "ethernet-phy-ieee802.3-c22";
  99                         reg = <0>;
 100                         txc-skew-ps = <1680>;
 101                         rxc-skew-ps = <1860>;
 102                 };
 103         };
 104 };
 105
 106 &gpmi {
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_gpmi_nand>;
 109         nand-on-flash-bbt;
 110         status = "okay";
 111 };
 112
 113 &i2c1 {
 114         pinctrl-names = "default";
 115         pinctrl-0 = <&pinctrl_i2c1>;
 116         status = "okay";
 117
 118         som_eeprom: eeprom@50 {
 119                 compatible = "catalyst,24c32", "atmel,24c32";
 120                 pagesize = <32>;
 121                 reg = <0x50>;
 122         };
 123
 124         pmic@58 {
 125                 compatible = "dlg,da9063";
 126                 reg = <0x58>;
 127                 interrupt-parent = <&gpio2>;
 128                 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
 129                 interrupt-controller;
 130
 131                 regulators {
 132                         vddcore_reg: bcore1 {
 133                                 regulator-min-microvolt = <730000>;
 134                                 regulator-max-microvolt = <1380000>;
 135                                 regulator-always-on;
 136                         };
 137
 138                         vddsoc_reg: bcore2 {
 139                                 regulator-min-microvolt = <730000>;
 140                                 regulator-max-microvolt = <1380000>;
 141                                 regulator-always-on;
 142                         };
 143
 144                         vdd_ddr3_reg: bpro {
 145                                 regulator-min-microvolt = <1500000>;
 146                                 regulator-max-microvolt = <1500000>;
 147                                 regulator-always-on;
 148                         };
 149
 150                         vdd_3v3_reg: bperi {
 151                                 regulator-min-microvolt = <3300000>;
 152                                 regulator-max-microvolt = <3300000>;
 153                                 regulator-always-on;
 154                         };
 155
 156                         vdd_buckmem_reg: bmem {
 157                                 regulator-min-microvolt = <3300000>;
 158                                 regulator-max-microvolt = <3300000>;
 159                                 regulator-always-on;
 160                         };
 161
 162                         vdd_eth_reg: bio {
 163                                 regulator-min-microvolt = <1200000>;
 164                                 regulator-max-microvolt = <1200000>;
 165                                 regulator-always-on;
 166                         };
 167
 168                         vdd_eth_io_reg: ldo4 {
 169                                 regulator-min-microvolt = <2500000>;
 170                                 regulator-max-microvolt = <2500000>;
 171                                 regulator-always-on;
 172                         };
 173
 174                         vdd_mx6_snvs_reg: ldo5 {
 175                                 regulator-min-microvolt = <3000000>;
 176                                 regulator-max-microvolt = <3000000>;
 177                                 regulator-always-on;
 178                         };
 179
 180                         vdd_3v3_pmic_io_reg: ldo6 {
 181                                 regulator-min-microvolt = <3300000>;
 182                                 regulator-max-microvolt = <3300000>;
 183                                 regulator-always-on;
 184                         };
 185
 186                         vdd_sd0_reg: ldo9 {
 187                                 regulator-min-microvolt = <3300000>;
 188                                 regulator-max-microvolt = <3300000>;
 189                         };
 190
 191                         vdd_sd1_reg: ldo10 {
 192                                 regulator-min-microvolt = <3300000>;
 193                                 regulator-max-microvolt = <3300000>;
 194                         };
 195
 196                         vdd_mx6_high_reg: ldo11 {
 197                                 regulator-min-microvolt = <3000000>;
 198                                 regulator-max-microvolt = <3000000>;
 199                                 regulator-always-on;
 200                         };
 201                 };
 202         };
 203 };
 204
 205 &i2c2 {
 206         pinctrl-names = "default";
 207         pinctrl-0 = <&pinctrl_i2c2>;
 208         clock-frequency = <100000>;
 209 };
 210
 211 &i2c3 {
 212         pinctrl-names = "default";
 213         pinctrl-0 = <&pinctrl_i2c3>;
 214         clock-frequency = <100000>;
 215 };
 216
 217 &iomuxc {
 218         pinctrl-names = "default";
 219         pinctrl-0 = <&pinctrl_hog>;
 220
 221         imx6q-phytec-pfla02 {
 222                 pinctrl_hog: hoggrp {
 223                         fsl,pins = <
 224                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
 225                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
 226                                 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09  0x80000000 /* PMIC interrupt */
 227                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
 228                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
 229                         >;
 230                 };
 231
 232                 pinctrl_ecspi3: ecspi3grp {
 233                         fsl,pins = <
 234                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 235                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 236                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 237                         >;
 238                 };
 239
 240                 pinctrl_enet: enetgrp {
 241                         fsl,pins = <
 242                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 243                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 244                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 245                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 246                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 247                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 248                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 249                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 250                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 251                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 252                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 253                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 254                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 255                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 256                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 257                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 258                         >;
 259                 };
 260
 261                 pinctrl_flexcan1: flexcan1grp {
 262                         fsl,pins = <
 263                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 264                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 265                         >;
 266                 };
 267
 268                 pinctrl_gpmi_nand: gpminandgrp {
 269                         fsl,pins = <
 270                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 271                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 272                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 273                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 274                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 275                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 276                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 277                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 278                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 279                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 280                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 281                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 282                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 283                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 284                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 285                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 286                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 287                         >;
 288                 };
 289
 290                 pinctrl_i2c1: i2c1grp {
 291                         fsl,pins = <
 292                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 293                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 294                         >;
 295                 };
 296
 297                 pinctrl_i2c2: i2c2grp {
 298                         fsl,pins = <
 299                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
 300                                 MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
 301                         >;
 302                 };
 303
 304                 pinctrl_i2c3: i2c3grp {
 305                         fsl,pins = <
 306                                 MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
 307                                 MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
 308                         >;
 309                 };
 310
 311                 pinctrl_pcie: pciegrp {
 312                         fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
 313                 };
 314
 315                 pinctrl_uart3: uart3grp {
 316                         fsl,pins = <
 317                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 318                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 319                                 MX6QDL_PAD_EIM_D30__UART3_RTS_B         0x1b0b1
 320                                 MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
 321                         >;
 322                 };
 323
 324                 pinctrl_uart4: uart4grp {
 325                         fsl,pins = <
 326                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 327                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 328                         >;
 329                 };
 330
 331                 pinctrl_usbh1: usbh1grp {
 332                         fsl,pins = <
 333                                 MX6QDL_PAD_GPIO_0__USB_H1_PWR           0x80000000
 334                         >;
 335                 };
 336
 337                 pinctrl_usbotg: usbotggrp {
 338                         fsl,pins = <
 339                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 340                                 MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
 341                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x80000000
 342                         >;
 343                 };
 344
 345                 pinctrl_usdhc2: usdhc2grp {
 346                         fsl,pins = <
 347                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 348                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 349                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 350                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 351                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 352                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 353                         >;
 354                 };
 355
 356                 pinctrl_usdhc3: usdhc3grp {
 357                         fsl,pins = <
 358                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 359                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 360                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 361                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 362                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 363                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 364                         >;
 365                 };
 366
 367                 pinctrl_usdhc3_cdwp: usdhc3cdwp {
 368                         fsl,pins = <
 369                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 370                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 371                         >;
 372                 };
 373
 374                 pinctrl_audmux: audmuxgrp {
 375                         fsl,pins = <
 376                                 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC        0x130b0
 377                                 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD        0x110b0
 378                                 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS       0x130b0
 379                                 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 380                         >;
 381                 };
 382         };
 383 };
 384
 385 &pcie {
 386         pinctrl-names = "default";
 387         pinctrl-0 = <&pinctrl_pcie>;
 388         reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
 389         status = "disabled";
 390 };
 391
 392 &reg_arm {
 393         vin-supply = <&vddcore_reg>;
 394 };
 395
 396 &reg_pu {
 397         vin-supply = <&vddsoc_reg>;
 398 };
 399
 400 &reg_soc {
 401         vin-supply = <&vddsoc_reg>;
 402 };
 403
 404 &uart3 {
 405         pinctrl-names = "default";
 406         pinctrl-0 = <&pinctrl_uart3>;
 407         status = "disabled";
 408 };
 409
 410 &uart4 {
 411         pinctrl-names = "default";
 412         pinctrl-0 = <&pinctrl_uart4>;
 413         status = "disabled";
 414 };
 415
 416 &usbh1 {
 417         vbus-supply = <&reg_usb_h1_vbus>;
 418         pinctrl-names = "default";
 419         pinctrl-0 = <&pinctrl_usbh1>;
 420         status = "disabled";
 421 };
 422
 423 &usbotg {
 424         vbus-supply = <&reg_usb_otg_vbus>;
 425         pinctrl-names = "default";
 426         pinctrl-0 = <&pinctrl_usbotg>;
 427         disable-over-current;
 428         status = "disabled";
 429 };
 430
 431 &usdhc2 {
 432         pinctrl-names = "default";
 433         pinctrl-0 = <&pinctrl_usdhc2>;
 434         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 435         wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 436         status = "disabled";
 437 };
 438
 439 &usdhc3 {
 440         pinctrl-names = "default";
 441         pinctrl-0 = <&pinctrl_usdhc3
 442                      &pinctrl_usdhc3_cdwp>;
 443         cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
 444         wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 445         status = "disabled";
 446 };