arch/arm/boot/dts/imx7d-sdb.dts

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Copyright (C) 2015 Freescale Semiconductor, Inc.
   4
   5 /dts-v1/;
   6
   7 #include "imx7d.dtsi"
   8
   9 / {
  10         model = "Freescale i.MX7 SabreSD Board";
  11         compatible = "fsl,imx7d-sdb", "fsl,imx7d";
  12
  13         chosen {
  14                 stdout-path = &uart1;
  15         };
  16
  17         memory@80000000 {
  18                 device_type = "memory";
  19                 reg = <0x80000000 0x80000000>;
  20         };
  21
  22         gpio-keys {
  23                 compatible = "gpio-keys";
  24                 pinctrl-names = "default";
  25                 pinctrl-0 = <&pinctrl_gpio_keys>;
  26
  27                 volume-up {
  28                         label = "Volume Up";
  29                         gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
  30                         linux,code = <KEY_VOLUMEUP>;
  31                         wakeup-source;
  32                 };
  33
  34                 volume-down {
  35                         label = "Volume Down";
  36                         gpios = <&gpio5 10 GPIO_ACTIVE_LOW>;
  37                         linux,code = <KEY_VOLUMEDOWN>;
  38                         wakeup-source;
  39                 };
  40         };
  41
  42         spi4 {
  43                 compatible = "spi-gpio";
  44                 pinctrl-names = "default";
  45                 pinctrl-0 = <&pinctrl_spi4>;
  46                 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>;
  47                 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  48                 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
  49                 num-chipselects = <1>;
  50                 #address-cells = <1>;
  51                 #size-cells = <0>;
  52
  53                 extended_io: gpio-expander@0 {
  54                         compatible = "fairchild,74hc595";
  55                         gpio-controller;
  56                         #gpio-cells = <2>;
  57                         reg = <0>;
  58                         registers-number = <1>;
  59                         spi-max-frequency = <100000>;
  60                 };
  61         };
  62
  63         reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
  64                 compatible = "regulator-fixed";
  65                 regulator-name = "usb_otg1_vbus";
  66                 regulator-min-microvolt = <5000000>;
  67                 regulator-max-microvolt = <5000000>;
  68                 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
  69                 enable-active-high;
  70         };
  71
  72         reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
  73                 compatible = "regulator-fixed";
  74                 regulator-name = "usb_otg2_vbus";
  75                 pinctrl-names = "default";
  76                 pinctrl-0 = <&pinctrl_usb_otg2_vbus_reg>;
  77                 regulator-min-microvolt = <5000000>;
  78                 regulator-max-microvolt = <5000000>;
  79                 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
  80                 enable-active-high;
  81         };
  82
  83         reg_vref_1v8: regulator-vref-1v8 {
  84                 compatible = "regulator-fixed";
  85                 regulator-name = "vref-1v8";
  86                 regulator-min-microvolt = <1800000>;
  87                 regulator-max-microvolt = <1800000>;
  88         };
  89
  90         reg_brcm: regulator-brcm {
  91                 compatible = "regulator-fixed";
  92                 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
  93                 enable-active-high;
  94                 regulator-name = "brcm_reg";
  95                 pinctrl-names = "default";
  96                 pinctrl-0 = <&pinctrl_brcm_reg>;
  97                 regulator-min-microvolt = <3300000>;
  98                 regulator-max-microvolt = <3300000>;
  99                 startup-delay-us = <200000>;
 100         };
 101
 102         reg_lcd_3v3: regulator-lcd-3v3 {
 103                 compatible = "regulator-fixed";
 104                 regulator-name = "lcd-3v3";
 105                 regulator-min-microvolt = <3300000>;
 106                 regulator-max-microvolt = <3300000>;
 107                 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>;
 108         };
 109
 110         reg_can2_3v3: regulator-can2-3v3 {
 111                 compatible = "regulator-fixed";
 112                 regulator-name = "can2-3v3";
 113                 pinctrl-names = "default";
 114                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
 118         };
 119
 120         reg_fec2_3v3: regulator-fec2-3v3 {
 121                 compatible = "regulator-fixed";
 122                 regulator-name = "fec2-3v3";
 123                 pinctrl-names = "default";
 124                 pinctrl-0 = <&pinctrl_enet2_reg>;
 125                 regulator-min-microvolt = <3300000>;
 126                 regulator-max-microvolt = <3300000>;
 127                 gpio = <&gpio1 4 GPIO_ACTIVE_LOW>;
 128         };
 129
 130         backlight: backlight {
 131                 compatible = "pwm-backlight";
 132                 pwms = <&pwm1 0 5000000 0>;
 133                 brightness-levels = <0 4 8 16 32 64 128 255>;
 134                 default-brightness-level = <6>;
 135                 status = "okay";
 136         };
 137
 138         panel {
 139                 compatible = "innolux,at043tn24";
 140                 backlight = <&backlight>;
 141                 power-supply = <&reg_lcd_3v3>;
 142
 143                 port {
 144                         panel_in: endpoint {
 145                                 remote-endpoint = <&display_out>;
 146                         };
 147                 };
 148         };
 149
 150         sound {
 151                 compatible = "fsl,imx7d-evk-wm8960",
 152                              "fsl,imx-audio-wm8960";
 153                 model = "wm8960-audio";
 154                 audio-cpu = <&sai1>;
 155                 audio-codec = <&codec>;
 156                 hp-det-gpio = <&gpio2 28 GPIO_ACTIVE_HIGH>;
 157                 audio-routing =
 158                         "Headphone Jack", "HP_L",
 159                         "Headphone Jack", "HP_R",
 160                         "Ext Spk", "SPK_LP",
 161                         "Ext Spk", "SPK_LN",
 162                         "Ext Spk", "SPK_RP",
 163                         "Ext Spk", "SPK_RN",
 164                         "LINPUT1", "AMIC",
 165                         "AMIC", "MICB";
 166         };
 167 };
 168
 169 &adc1 {
 170         vref-supply = <&reg_vref_1v8>;
 171         status = "okay";
 172 };
 173
 174 &adc2 {
 175         vref-supply = <&reg_vref_1v8>;
 176         status = "okay";
 177 };
 178
 179 &cpu0 {
 180         cpu-supply = <&sw1a_reg>;
 181 };
 182
 183 &cpu1 {
 184         cpu-supply = <&sw1a_reg>;
 185 };
 186
 187 &ecspi3 {
 188         pinctrl-names = "default";
 189         pinctrl-0 = <&pinctrl_ecspi3>;
 190         cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
 191         status = "okay";
 192
 193         tsc2046@0 {
 194                 compatible = "ti,tsc2046";
 195                 reg = <0>;
 196                 spi-max-frequency = <1000000>;
 197                 pinctrl-names ="default";
 198                 pinctrl-0 = <&pinctrl_tsc2046_pendown>;
 199                 interrupt-parent = <&gpio2>;
 200                 interrupts = <29 0>;
 201                 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>;
 202                 ti,x-min = /bits/ 16 <0>;
 203                 ti,x-max = /bits/ 16 <0>;
 204                 ti,y-min = /bits/ 16 <0>;
 205                 ti,y-max = /bits/ 16 <0>;
 206                 ti,pressure-max = /bits/ 16 <0>;
 207                 ti,x-plate-ohms = /bits/ 16 <400>;
 208                 wakeup-source;
 209         };
 210 };
 211
 212 &fec1 {
 213         pinctrl-names = "default";
 214         pinctrl-0 = <&pinctrl_enet1>;
 215         assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
 216                           <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
 217         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 218         assigned-clock-rates = <0>, <100000000>;
 219         phy-mode = "rgmii";
 220         phy-handle = <&ethphy0>;
 221         fsl,magic-packet;
 222         phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>;
 223         status = "okay";
 224
 225         mdio {
 226                 #address-cells = <1>;
 227                 #size-cells = <0>;
 228
 229                 ethphy0: ethernet-phy@0 {
 230                         reg = <0>;
 231                 };
 232
 233                 ethphy1: ethernet-phy@1 {
 234                         reg = <1>;
 235                 };
 236         };
 237 };
 238
 239 &fec2 {
 240         pinctrl-names = "default";
 241         pinctrl-0 = <&pinctrl_enet2>;
 242         assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
 243                           <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
 244         assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
 245         assigned-clock-rates = <0>, <100000000>;
 246         phy-mode = "rgmii";
 247         phy-handle = <&ethphy1>;
 248         phy-supply = <&reg_fec2_3v3>;
 249         fsl,magic-packet;
 250         status = "okay";
 251 };
 252
 253 &flexcan2 {
 254         pinctrl-names = "default";
 255         pinctrl-0 = <&pinctrl_flexcan2>;
 256         xceiver-supply = <&reg_can2_3v3>;
 257         status = "okay";
 258 };
 259
 260 &i2c1 {
 261         pinctrl-names = "default";
 262         pinctrl-0 = <&pinctrl_i2c1>;
 263         status = "okay";
 264
 265         pmic: pfuze3000@8 {
 266                 compatible = "fsl,pfuze3000";
 267                 reg = <0x08>;
 268
 269                 regulators {
 270                         sw1a_reg: sw1a {
 271                                 regulator-min-microvolt = <700000>;
 272                                 regulator-max-microvolt = <1475000>;
 273                                 regulator-boot-on;
 274                                 regulator-always-on;
 275                                 regulator-ramp-delay = <6250>;
 276                         };
 277
 278                         /* use sw1c_reg to align with pfuze100/pfuze200 */
 279                         sw1c_reg: sw1b {
 280                                 regulator-min-microvolt = <700000>;
 281                                 regulator-max-microvolt = <1475000>;
 282                                 regulator-boot-on;
 283                                 regulator-always-on;
 284                                 regulator-ramp-delay = <6250>;
 285                         };
 286
 287                         sw2_reg: sw2 {
 288                                 regulator-min-microvolt = <1800000>;
 289                                 regulator-max-microvolt = <1800000>;
 290                                 regulator-boot-on;
 291                                 regulator-always-on;
 292                         };
 293
 294                         sw3a_reg: sw3 {
 295                                 regulator-min-microvolt = <900000>;
 296                                 regulator-max-microvolt = <1650000>;
 297                                 regulator-boot-on;
 298                                 regulator-always-on;
 299                         };
 300
 301                         swbst_reg: swbst {
 302                                 regulator-min-microvolt = <5000000>;
 303                                 regulator-max-microvolt = <5150000>;
 304                         };
 305
 306                         snvs_reg: vsnvs {
 307                                 regulator-min-microvolt = <1000000>;
 308                                 regulator-max-microvolt = <3000000>;
 309                                 regulator-boot-on;
 310                                 regulator-always-on;
 311                         };
 312
 313                         vref_reg: vrefddr {
 314                                 regulator-boot-on;
 315                                 regulator-always-on;
 316                         };
 317
 318                         vgen1_reg: vldo1 {
 319                                 regulator-min-microvolt = <1800000>;
 320                                 regulator-max-microvolt = <3300000>;
 321                                 regulator-always-on;
 322                         };
 323
 324                         vgen2_reg: vldo2 {
 325                                 regulator-min-microvolt = <800000>;
 326                                 regulator-max-microvolt = <1550000>;
 327                         };
 328
 329                         vgen3_reg: vccsd {
 330                                 regulator-min-microvolt = <2850000>;
 331                                 regulator-max-microvolt = <3300000>;
 332                                 regulator-always-on;
 333                         };
 334
 335                         vgen4_reg: v33 {
 336                                 regulator-min-microvolt = <2850000>;
 337                                 regulator-max-microvolt = <3300000>;
 338                                 regulator-always-on;
 339                         };
 340
 341                         vgen5_reg: vldo3 {
 342                                 regulator-min-microvolt = <1800000>;
 343                                 regulator-max-microvolt = <3300000>;
 344                                 regulator-always-on;
 345                         };
 346
 347                         vgen6_reg: vldo4 {
 348                                 regulator-min-microvolt = <2800000>;
 349                                 regulator-max-microvolt = <2800000>;
 350                                 regulator-always-on;
 351                         };
 352                 };
 353         };
 354 };
 355
 356 &i2c2 {
 357         pinctrl-names = "default";
 358         pinctrl-0 = <&pinctrl_i2c2>;
 359         status = "okay";
 360
 361         mpl3115@60 {
 362                 compatible = "fsl,mpl3115";
 363                 reg = <0x60>;
 364         };
 365 };
 366
 367 &i2c3 {
 368         pinctrl-names = "default";
 369         pinctrl-0 = <&pinctrl_i2c3>;
 370         status = "okay";
 371 };
 372
 373 &i2c4 {
 374         pinctrl-names = "default";
 375         pinctrl-0 = <&pinctrl_i2c4>;
 376         status = "okay";
 377
 378         codec: wm8960@1a {
 379                 compatible = "wlf,wm8960";
 380                 reg = <0x1a>;
 381                 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 382                 clock-names = "mclk";
 383                 wlf,shared-lrclk;
 384                 wlf,hp-cfg = <2 2 3>;
 385                 wlf,gpio-cfg = <1 3>;
 386                 assigned-clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_SRC>,
 387                                   <&clks IMX7D_PLL_AUDIO_POST_DIV>,
 388                                   <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
 389                 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 390                 assigned-clock-rates = <0>, <884736000>, <12288000>;
 391         };
 392 };
 393
 394 &lcdif {
 395         pinctrl-names = "default";
 396         pinctrl-0 = <&pinctrl_lcdif>;
 397         status = "okay";
 398
 399         port {
 400                 display_out: endpoint {
 401                         remote-endpoint = <&panel_in>;
 402                 };
 403         };
 404 };
 405
 406 &pcie {
 407         reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
 408         status = "okay";
 409 };
 410
 411 &reg_1p0d {
 412         vin-supply = <&sw2_reg>;
 413 };
 414
 415 &reg_1p2 {
 416         vin-supply = <&sw2_reg>;
 417 };
 418
 419 &sai1 {
 420         pinctrl-names = "default";
 421         pinctrl-0 = <&pinctrl_sai1>;
 422         assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
 423                           <&clks IMX7D_PLL_AUDIO_POST_DIV>,
 424                           <&clks IMX7D_SAI1_ROOT_CLK>;
 425         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 426         assigned-clock-rates = <0>, <884736000>, <36864000>;
 427         status = "okay";
 428 };
 429
 430 &sai3 {
 431         pinctrl-names = "default";
 432         pinctrl-0 = <&pinctrl_sai3 &pinctrl_sai3_mclk>;
 433         assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>,
 434                           <&clks IMX7D_PLL_AUDIO_POST_DIV>,
 435                           <&clks IMX7D_SAI3_ROOT_CLK>;
 436         assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
 437         assigned-clock-rates = <0>, <884736000>, <36864000>;
 438         status = "okay";
 439 };
 440
 441 &snvs_pwrkey {
 442         status = "okay";
 443 };
 444
 445 &uart1 {
 446         pinctrl-names = "default";
 447         pinctrl-0 = <&pinctrl_uart1>;
 448         assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
 449         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 450         status = "okay";
 451 };
 452
 453 &uart6 {
 454         pinctrl-names = "default";
 455         pinctrl-0 = <&pinctrl_uart6>;
 456         assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
 457         assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
 458         uart-has-rtscts;
 459         status = "okay";
 460 };
 461
 462 &usbotg1 {
 463         vbus-supply = <&reg_usb_otg1_vbus>;
 464         status = "okay";
 465 };
 466
 467 &usbotg2 {
 468         vbus-supply = <&reg_usb_otg2_vbus>;
 469         dr_mode = "host";
 470         status = "okay";
 471 };
 472
 473 &usdhc1 {
 474         pinctrl-names = "default";
 475         pinctrl-0 = <&pinctrl_usdhc1>;
 476         cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
 477         wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
 478         wakeup-source;
 479         keep-power-in-suspend;
 480         status = "okay";
 481 };
 482
 483 &usdhc2 {
 484         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 485         pinctrl-0 = <&pinctrl_usdhc2>;
 486         pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
 487         pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
 488         wakeup-source;
 489         keep-power-in-suspend;
 490         non-removable;
 491         vmmc-supply = <&reg_brcm>;
 492         fsl,tuning-step = <2>;
 493         status = "okay";
 494 };
 495
 496 &usdhc3 {
 497         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 498         pinctrl-0 = <&pinctrl_usdhc3>;
 499         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 500         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 501         assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
 502         assigned-clock-rates = <400000000>;
 503         bus-width = <8>;
 504         fsl,tuning-step = <2>;
 505         non-removable;
 506         status = "okay";
 507 };
 508
 509 &wdog1 {
 510         pinctrl-names = "default";
 511         pinctrl-0 = <&pinctrl_wdog>;
 512         fsl,ext-reset-output;
 513 };
 514
 515 &iomuxc {
 516         pinctrl-names = "default";
 517         pinctrl-0 = <&pinctrl_hog>;
 518
 519         imx7d-sdb {
 520                 pinctrl_brcm_reg: brcmreggrp {
 521                         fsl,pins = <
 522                                 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21        0x14
 523                         >;
 524                 };
 525
 526                 pinctrl_ecspi3: ecspi3grp {
 527                         fsl,pins = <
 528                                 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO      0x2
 529                                 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI      0x2
 530                                 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK      0x2
 531                                 MX7D_PAD_SD2_CD_B__GPIO5_IO9            0x59
 532                         >;
 533                 };
 534
 535                 pinctrl_enet1: enet1grp {
 536                         fsl,pins = <
 537                                 MX7D_PAD_GPIO1_IO10__ENET1_MDIO                 0x3
 538                                 MX7D_PAD_GPIO1_IO11__ENET1_MDC                  0x3
 539                                 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC       0x1
 540                                 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0       0x1
 541                                 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1       0x1
 542                                 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2       0x1
 543                                 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3       0x1
 544                                 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
 545                                 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC       0x1
 546                                 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0       0x1
 547                                 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1       0x1
 548                                 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2       0x1
 549                                 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3       0x1
 550                                 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
 551                         >;
 552                 };
 553
 554                 pinctrl_enet2: enet2grp {
 555                         fsl,pins = <
 556                                 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC             0x1
 557                                 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0            0x1
 558                                 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1            0x1
 559                                 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2            0x1
 560                                 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3             0x1
 561                                 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL          0x1
 562                                 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC            0x1
 563                                 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0            0x1
 564                                 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1             0x1
 565                                 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2             0x1
 566                                 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3            0x1
 567                                 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL         0x1
 568                         >;
 569                 };
 570
 571                 pinctrl_enet2_reg: enet2reggrp {
 572                         fsl,pins = <
 573                                 MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4     0x14
 574                         >;
 575                 };
 576
 577                 pinctrl_flexcan2: flexcan2grp {
 578                         fsl,pins = <
 579                                 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX        0x59
 580                                 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX        0x59
 581                         >;
 582                 };
 583
 584                 pinctrl_flexcan2_reg: flexcan2reggrp {
 585                         fsl,pins = <
 586                                 MX7D_PAD_EPDC_DATA14__GPIO2_IO14        0x59    /* CAN_STBY */
 587                         >;
 588                 };
 589
 590                 pinctrl_gpio_keys: gpio_keysgrp {
 591                         fsl,pins = <
 592                                 MX7D_PAD_SD2_RESET_B__GPIO5_IO11        0x59
 593                                 MX7D_PAD_SD2_WP__GPIO5_IO10             0x59
 594                         >;
 595                 };
 596
 597                 pinctrl_hog: hoggrp {
 598                         fsl,pins = <
 599                                 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23         0x34  /* bt reg on */
 600                                 MX7D_PAD_EPDC_BDR0__GPIO2_IO28          0x59  /* headphone detect */
 601                         >;
 602                 };
 603
 604                 pinctrl_i2c1: i2c1grp {
 605                         fsl,pins = <
 606                                 MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
 607                                 MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
 608                         >;
 609                 };
 610
 611                 pinctrl_i2c2: i2c2grp {
 612                         fsl,pins = <
 613                                 MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
 614                                 MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
 615                         >;
 616                 };
 617
 618                 pinctrl_i2c3: i2c3grp {
 619                         fsl,pins = <
 620                                 MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
 621                                 MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
 622                         >;
 623                 };
 624
 625                 pinctrl_i2c4: i2c4grp {
 626                         fsl,pins = <
 627                                 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
 628                                 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
 629                         >;
 630                 };
 631
 632                 pinctrl_lcdif: lcdifgrp {
 633                         fsl,pins = <
 634                                 MX7D_PAD_LCD_DATA00__LCD_DATA0          0x79
 635                                 MX7D_PAD_LCD_DATA01__LCD_DATA1          0x79
 636                                 MX7D_PAD_LCD_DATA02__LCD_DATA2          0x79
 637                                 MX7D_PAD_LCD_DATA03__LCD_DATA3          0x79
 638                                 MX7D_PAD_LCD_DATA04__LCD_DATA4          0x79
 639                                 MX7D_PAD_LCD_DATA05__LCD_DATA5          0x79
 640                                 MX7D_PAD_LCD_DATA06__LCD_DATA6          0x79
 641                                 MX7D_PAD_LCD_DATA07__LCD_DATA7          0x79
 642                                 MX7D_PAD_LCD_DATA08__LCD_DATA8          0x79
 643                                 MX7D_PAD_LCD_DATA09__LCD_DATA9          0x79
 644                                 MX7D_PAD_LCD_DATA10__LCD_DATA10         0x79
 645                                 MX7D_PAD_LCD_DATA11__LCD_DATA11         0x79
 646                                 MX7D_PAD_LCD_DATA12__LCD_DATA12         0x79
 647                                 MX7D_PAD_LCD_DATA13__LCD_DATA13         0x79
 648                                 MX7D_PAD_LCD_DATA14__LCD_DATA14         0x79
 649                                 MX7D_PAD_LCD_DATA15__LCD_DATA15         0x79
 650                                 MX7D_PAD_LCD_DATA16__LCD_DATA16         0x79
 651                                 MX7D_PAD_LCD_DATA17__LCD_DATA17         0x79
 652                                 MX7D_PAD_LCD_DATA18__LCD_DATA18         0x79
 653                                 MX7D_PAD_LCD_DATA19__LCD_DATA19         0x79
 654                                 MX7D_PAD_LCD_DATA20__LCD_DATA20         0x79
 655                                 MX7D_PAD_LCD_DATA21__LCD_DATA21         0x79
 656                                 MX7D_PAD_LCD_DATA22__LCD_DATA22         0x79
 657                                 MX7D_PAD_LCD_DATA23__LCD_DATA23         0x79
 658                                 MX7D_PAD_LCD_CLK__LCD_CLK               0x79
 659                                 MX7D_PAD_LCD_ENABLE__LCD_ENABLE         0x79
 660                                 MX7D_PAD_LCD_VSYNC__LCD_VSYNC           0x79
 661                                 MX7D_PAD_LCD_HSYNC__LCD_HSYNC           0x79
 662                                 MX7D_PAD_LCD_RESET__LCD_RESET           0x79
 663                         >;
 664                 };
 665
 666                 pinctrl_sai1: sai1grp {
 667                         fsl,pins = <
 668                                 MX7D_PAD_SAI1_MCLK__SAI1_MCLK           0x1f
 669                                 MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK     0x1f
 670                                 MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC        0x1f
 671                                 MX7D_PAD_ENET1_COL__SAI1_TX_DATA0       0x30
 672                                 MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0    0x1f
 673                         >;
 674                 };
 675
 676                 pinctrl_sai2: sai2grp {
 677                         fsl,pins = <
 678                                 MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK     0x1f
 679                                 MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC     0x1f
 680                                 MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0    0x30
 681                                 MX7D_PAD_SAI2_RX_DATA__SAI2_RX_DATA0    0x1f
 682                         >;
 683                 };
 684
 685                 pinctrl_sai3: sai3grp {
 686                         fsl,pins = <
 687                                 MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK   0x1f
 688                                 MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC     0x1f
 689                                 MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0    0x30
 690                         >;
 691                 };
 692
 693                 pinctrl_spi4: spi4grp {
 694                         fsl,pins = <
 695                                 MX7D_PAD_GPIO1_IO09__GPIO1_IO9  0x59
 696                                 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59
 697                                 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59
 698                         >;
 699                 };
 700
 701                 pinctrl_tsc2046_pendown: tsc2046_pendown {
 702                         fsl,pins = <
 703                                 MX7D_PAD_EPDC_BDR1__GPIO2_IO29          0x59
 704                         >;
 705                 };
 706
 707                 pinctrl_uart1: uart1grp {
 708                         fsl,pins = <
 709                                 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX    0x79
 710                                 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX    0x79
 711                         >;
 712                 };
 713
 714                 pinctrl_uart5: uart5grp {
 715                         fsl,pins = <
 716                                 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX     0x79
 717                                 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX     0x79
 718                                 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS    0x79
 719                                 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS    0x79
 720                         >;
 721                 };
 722
 723                 pinctrl_uart6: uart6grp {
 724                         fsl,pins = <
 725                                 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX      0x79
 726                                 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX      0x79
 727                                 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS      0x79
 728                                 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS     0x79
 729                         >;
 730                 };
 731
 732                 pinctrl_usdhc1: usdhc1grp {
 733                         fsl,pins = <
 734                                 MX7D_PAD_SD1_CMD__SD1_CMD               0x59
 735                                 MX7D_PAD_SD1_CLK__SD1_CLK               0x19
 736                                 MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
 737                                 MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
 738                                 MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
 739                                 MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
 740                                 MX7D_PAD_SD1_CD_B__GPIO5_IO0            0x59 /* CD */
 741                                 MX7D_PAD_SD1_WP__GPIO5_IO1              0x59 /* WP */
 742                                 MX7D_PAD_SD1_RESET_B__GPIO5_IO2         0x59 /* vmmc */
 743                         >;
 744                 };
 745
 746                 pinctrl_usdhc2: usdhc2grp {
 747                         fsl,pins = <
 748                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x59
 749                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x19
 750                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x59
 751                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x59
 752                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x59
 753                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x59
 754                         >;
 755                 };
 756
 757                 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz {
 758                         fsl,pins = <
 759                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5a
 760                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1a
 761                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5a
 762                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5a
 763                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5a
 764                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5a
 765                         >;
 766                 };
 767
 768                 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz {
 769                         fsl,pins = <
 770                                 MX7D_PAD_SD2_CMD__SD2_CMD               0x5b
 771                                 MX7D_PAD_SD2_CLK__SD2_CLK               0x1b
 772                                 MX7D_PAD_SD2_DATA0__SD2_DATA0           0x5b
 773                                 MX7D_PAD_SD2_DATA1__SD2_DATA1           0x5b
 774                                 MX7D_PAD_SD2_DATA2__SD2_DATA2           0x5b
 775                                 MX7D_PAD_SD2_DATA3__SD2_DATA3           0x5b
 776                         >;
 777                 };
 778
 779
 780                 pinctrl_usdhc3: usdhc3grp {
 781                         fsl,pins = <
 782                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x59
 783                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x19
 784                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
 785                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
 786                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
 787                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
 788                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
 789                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
 790                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
 791                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
 792                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x19
 793                         >;
 794                 };
 795
 796                 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
 797                         fsl,pins = <
 798                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5a
 799                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1a
 800                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5a
 801                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5a
 802                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5a
 803                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5a
 804                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5a
 805                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5a
 806                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5a
 807                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5a
 808                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1a
 809                         >;
 810                 };
 811
 812                 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
 813                         fsl,pins = <
 814                                 MX7D_PAD_SD3_CMD__SD3_CMD               0x5b
 815                                 MX7D_PAD_SD3_CLK__SD3_CLK               0x1b
 816                                 MX7D_PAD_SD3_DATA0__SD3_DATA0           0x5b
 817                                 MX7D_PAD_SD3_DATA1__SD3_DATA1           0x5b
 818                                 MX7D_PAD_SD3_DATA2__SD3_DATA2           0x5b
 819                                 MX7D_PAD_SD3_DATA3__SD3_DATA3           0x5b
 820                                 MX7D_PAD_SD3_DATA4__SD3_DATA4           0x5b
 821                                 MX7D_PAD_SD3_DATA5__SD3_DATA5           0x5b
 822                                 MX7D_PAD_SD3_DATA6__SD3_DATA6           0x5b
 823                                 MX7D_PAD_SD3_DATA7__SD3_DATA7           0x5b
 824                                 MX7D_PAD_SD3_STROBE__SD3_STROBE         0x1b
 825                         >;
 826                 };
 827         };
 828 };
 829
 830 &pwm1 {
 831         pinctrl-names = "default";
 832         pinctrl-0 = <&pinctrl_pwm1>;
 833         status = "okay";
 834 };
 835
 836 &iomuxc_lpsr {
 837         pinctrl_wdog: wdoggrp {
 838                 fsl,pins = <
 839                         MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B          0x74
 840                 >;
 841         };
 842
 843         pinctrl_pwm1: pwm1grp {
 844                 fsl,pins = <
 845                         MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT              0x30
 846                 >;
 847         };
 848
 849         pinctrl_usb_otg2_vbus_reg: usbotg2vbusreggrp {
 850                 fsl,pins = <
 851                         MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7       0x14
 852                 >;
 853         };
 854
 855         pinctrl_sai3_mclk: sai3grp_mclk {
 856                 fsl,pins = <
 857                         MX7D_PAD_LPSR_GPIO1_IO03__SAI3_MCLK     0x1f
 858                 >;
 859         };
 860 };