1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014 Carlo Caione <carlo@caione.org>
9 model = "Amlogic Meson6 SoC";
10 compatible = "amlogic,meson6";
18 compatible = "arm,cortex-a9";
19 next-level-cache = <&L2>;
25 compatible = "arm,cortex-a9";
26 next-level-cache = <&L2>;
32 compatible = "simple-bus";
33 reg = <0xd0000000 0x40000>;
36 ranges = <0x0 0xd0000000 0x40000>;
41 compatible = "fixed-clock";
42 clock-frequency = <200000000>;
51 clocks = <&xtal>, <&clk81>;
52 clock-names = "xtal", "pclk";
56 clocks = <&xtal>, <&clk81>, <&clk81>;
57 clock-names = "xtal", "pclk", "baud";
61 clocks = <&xtal>, <&clk81>, <&clk81>;
62 clock-names = "xtal", "pclk", "baud";
66 clocks = <&xtal>, <&clk81>, <&clk81>;
67 clock-names = "xtal", "pclk", "baud";
71 clocks = <&xtal>, <&clk81>, <&clk81>;
72 clock-names = "xtal", "pclk", "baud";