arch/arm/boot/dts/omap36xx-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for OMAP36xx clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &cm_clocks {
   8         dpll4_ck: dpll4_ck@d00 {
   9                 #clock-cells = <0>;
  10                 compatible = "ti,omap3-dpll-per-j-type-clock";
  11                 clocks = <&sys_ck>, <&sys_ck>;
  12                 reg = <0x0d00>, <0x0d20>, <0x0d44>, <0x0d30>;
  13         };
  14
  15         dpll4_m5x2_ck: dpll4_m5x2_ck@d00 {
  16                 #clock-cells = <0>;
  17                 compatible = "ti,hsdiv-gate-clock";
  18                 clocks = <&dpll4_m5x2_mul_ck>;
  19                 ti,bit-shift = <0x1e>;
  20                 reg = <0x0d00>;
  21                 ti,set-rate-parent;
  22                 ti,set-bit-to-disable;
  23         };
  24
  25         dpll4_m2x2_ck: dpll4_m2x2_ck@d00 {
  26                 #clock-cells = <0>;
  27                 compatible = "ti,hsdiv-gate-clock";
  28                 clocks = <&dpll4_m2x2_mul_ck>;
  29                 ti,bit-shift = <0x1b>;
  30                 reg = <0x0d00>;
  31                 ti,set-bit-to-disable;
  32         };
  33
  34         dpll3_m3x2_ck: dpll3_m3x2_ck@d00 {
  35                 #clock-cells = <0>;
  36                 compatible = "ti,hsdiv-gate-clock";
  37                 clocks = <&dpll3_m3x2_mul_ck>;
  38                 ti,bit-shift = <0xc>;
  39                 reg = <0x0d00>;
  40                 ti,set-bit-to-disable;
  41         };
  42
  43         dpll4_m3x2_ck: dpll4_m3x2_ck@d00 {
  44                 #clock-cells = <0>;
  45                 compatible = "ti,hsdiv-gate-clock";
  46                 clocks = <&dpll4_m3x2_mul_ck>;
  47                 ti,bit-shift = <0x1c>;
  48                 reg = <0x0d00>;
  49                 ti,set-bit-to-disable;
  50         };
  51
  52         dpll4_m6x2_ck: dpll4_m6x2_ck@d00 {
  53                 #clock-cells = <0>;
  54                 compatible = "ti,hsdiv-gate-clock";
  55                 clocks = <&dpll4_m6x2_mul_ck>;
  56                 ti,bit-shift = <0x1f>;
  57                 reg = <0x0d00>;
  58                 ti,set-bit-to-disable;
  59         };
  60
  61         uart4_fck: uart4_fck@1000 {
  62                 #clock-cells = <0>;
  63                 compatible = "ti,wait-gate-clock";
  64                 clocks = <&per_48m_fck>;
  65                 reg = <0x1000>;
  66                 ti,bit-shift = <18>;
  67         };
  68 };
  69
  70 &dpll4_m2x2_mul_ck {
  71         clock-mult = <1>;
  72 };
  73
  74 &dpll4_m3x2_mul_ck {
  75         clock-mult = <1>;
  76 };
  77
  78 &dpll4_m4x2_mul_ck {
  79         ti,clock-mult = <1>;
  80 };
  81
  82 &dpll4_m5x2_mul_ck {
  83         ti,clock-mult = <1>;
  84 };
  85
  86 &dpll4_m6x2_mul_ck {
  87         clock-mult = <1>;
  88 };
  89
  90 &cm_clockdomains {
  91         dpll4_clkdm: dpll4_clkdm {
  92                 compatible = "ti,clockdomain";
  93                 clocks = <&dpll4_ck>;
  94         };
  95
  96         per_clkdm: per_clkdm {
  97                 compatible = "ti,clockdomain";
  98                 clocks = <&uart3_fck>, <&gpio6_dbck>, <&gpio5_dbck>,
  99                          <&gpio4_dbck>, <&gpio3_dbck>, <&gpio2_dbck>,
 100                          <&wdt3_fck>, <&gpio6_ick>, <&gpio5_ick>, <&gpio4_ick>,
 101                          <&gpio3_ick>, <&gpio2_ick>, <&wdt3_ick>, <&uart3_ick>,
 102                          <&uart4_ick>, <&gpt9_ick>, <&gpt8_ick>, <&gpt7_ick>,
 103                          <&gpt6_ick>, <&gpt5_ick>, <&gpt4_ick>, <&gpt3_ick>,
 104                          <&gpt2_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
 105                          <&mcbsp4_ick>, <&uart4_fck>;
 106         };
 107 };
 108
 109 &dpll4_m4_ck {
 110         ti,max-div = <31>;
 111 };