| blob | 5f1a8bd1388049edd7413cec78d62703786dcdbc |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/omap.h>
12 #include <dt-bindings/clock/omap5.h>
14 / {
15 #address-cells = <2>;
16 #size-cells = <2>;
18 compatible = "ti,omap5";
19 interrupt-parent = <&wakeupgen>;
20 chosen { };
22 aliases {
23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 rproc0 = &dsp;
35 rproc1 = &ipu;
36 };
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
42 cpu0: cpu@0 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a15";
45 reg = <0x0>;
47 operating-points = <
48 /* kHz uV */
49 1000000 1060000
50 1500000 1250000
51 >;
53 clocks = <&dpll_mpu_ck>;
54 clock-names = "cpu";
56 clock-latency = <300000>; /* From omap-cpufreq driver */
58 /* cooling options */
59 #cooling-cells = <2>; /* min followed by max */
60 };
61 cpu@1 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a15";
64 reg = <0x1>;
66 operating-points = <
67 /* kHz uV */
68 1000000 1060000
69 1500000 1250000
70 >;
72 clocks = <&dpll_mpu_ck>;
73 clock-names = "cpu";
75 clock-latency = <300000>; /* From omap-cpufreq driver */
77 /* cooling options */
78 #cooling-cells = <2>; /* min followed by max */
79 };
80 };
82 thermal-zones {
83 #include "omap4-cpu-thermal.dtsi"
84 #include "omap5-gpu-thermal.dtsi"
85 #include "omap5-core-thermal.dtsi"
86 };
88 timer {
89 compatible = "arm,armv7-timer";
90 /* PPI secure/nonsecure IRQ */
91 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
92 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
93 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
94 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
95 interrupt-parent = <&gic>;
96 };
98 pmu {
99 compatible = "arm,cortex-a15-pmu";
100 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
102 };
104 gic: interrupt-controller@48211000 {
105 compatible = "arm,cortex-a15-gic";
106 interrupt-controller;
107 #interrupt-cells = <3>;
108 reg = <0 0x48211000 0 0x1000>,
109 <0 0x48212000 0 0x2000>,
110 <0 0x48214000 0 0x2000>,
111 <0 0x48216000 0 0x2000>;
112 interrupt-parent = <&gic>;
113 };
115 wakeupgen: interrupt-controller@48281000 {
116 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
117 interrupt-controller;
118 #interrupt-cells = <3>;
119 reg = <0 0x48281000 0 0x1000>;
120 interrupt-parent = <&gic>;
121 };
123 /*
124 * The soc node represents the soc top level view. It is used for IPs
125 * that are not memory mapped in the MPU view or for the MPU itself.
126 */
127 soc {
128 compatible = "ti,omap-infra";
129 mpu {
130 compatible = "ti,omap4-mpu";
131 ti,hwmods = "mpu";
132 sram = <&ocmcram>;
133 };
134 };
136 /*
137 * XXX: Use a flat representation of the OMAP3 interconnect.
138 * The real OMAP interconnect network is quite complex.
139 * Since it will not bring real advantage to represent that in DT for
140 * the moment, just use a fake OCP bus entry to represent the whole bus
141 * hierarchy.
142 */
143 ocp {
144 compatible = "ti,omap5-l3-noc", "simple-bus";
145 #address-cells = <1>;
146 #size-cells = <1>;
147 ranges = <0 0 0 0xc0000000>;
148 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
149 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
150 reg = <0 0x44000000 0 0x2000>,
151 <0 0x44800000 0 0x3000>,
152 <0 0x45000000 0 0x4000>;
153 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
156 l4_wkup: interconnect@4ae00000 {
157 };
159 l4_cfg: interconnect@4a000000 {
160 };
162 l4_per: interconnect@48000000 {
163 };
165 l4_abe: interconnect@40100000 {
166 };
168 ocmcram: sram@40300000 {
169 compatible = "mmio-sram";
170 reg = <0x40300000 0x20000>; /* 128k */
171 };
173 gpmc: gpmc@50000000 {
174 compatible = "ti,omap4430-gpmc";
175 reg = <0x50000000 0x1000>;
176 #address-cells = <2>;
177 #size-cells = <1>;
178 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
179 dmas = <&sdma 4>;
180 dma-names = "rxtx";
181 gpmc,num-cs = <8>;
182 gpmc,num-waitpins = <4>;
183 ti,hwmods = "gpmc";
184 clocks = <&l3_iclk_div>;
185 clock-names = "fck";
186 interrupt-controller;
187 #interrupt-cells = <2>;
188 gpio-controller;
189 #gpio-cells = <2>;
190 };
192 target-module@55082000 {
193 compatible = "ti,sysc-omap2", "ti,sysc";
194 reg = <0x55082000 0x4>,
195 <0x55082010 0x4>,
196 <0x55082014 0x4>;
197 reg-names = "rev", "sysc", "syss";
198 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
199 <SYSC_IDLE_NO>,
200 <SYSC_IDLE_SMART>;
201 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
202 SYSC_OMAP2_SOFTRESET |
203 SYSC_OMAP2_AUTOIDLE)>;
204 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
205 clock-names = "fck";
206 resets = <&prm_core 2>;
207 reset-names = "rstctrl";
208 ranges = <0x0 0x55082000 0x100>;
209 #size-cells = <1>;
210 #address-cells = <1>;
212 mmu_ipu: mmu@0 {
213 compatible = "ti,omap4-iommu";
214 reg = <0x0 0x100>;
215 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
216 #iommu-cells = <0>;
217 ti,iommu-bus-err-back;
218 };
219 };
221 dsp: dsp {
222 compatible = "ti,omap5-dsp";
223 ti,bootreg = <&scm_conf 0x304 0>;
224 iommus = <&mmu_dsp>;
225 resets = <&prm_dsp 0>;
226 clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
227 firmware-name = "omap5-dsp-fw.xe64T";
228 mboxes = <&mailbox &mbox_dsp>;
229 status = "disabled";
230 };
232 ipu: ipu@55020000 {
233 compatible = "ti,omap5-ipu";
234 reg = <0x55020000 0x10000>;
235 reg-names = "l2ram";
236 iommus = <&mmu_ipu>;
237 resets = <&prm_core 0>, <&prm_core 1>;
238 clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
239 firmware-name = "omap5-ipu-fw.xem4";
240 mboxes = <&mailbox &mbox_ipu>;
241 status = "disabled";
242 };
244 dmm@4e000000 {
245 compatible = "ti,omap5-dmm";
246 reg = <0x4e000000 0x800>;
247 interrupts = <0 113 0x4>;
248 ti,hwmods = "dmm";
249 };
251 emif1: emif@4c000000 {
252 compatible = "ti,emif-4d5";
253 ti,hwmods = "emif1";
254 ti,no-idle-on-init;
255 phy-type = <2>; /* DDR PHY type: Intelli PHY */
256 reg = <0x4c000000 0x400>;
257 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
258 hw-caps-read-idle-ctrl;
259 hw-caps-ll-interface;
260 hw-caps-temp-alert;
261 };
263 emif2: emif@4d000000 {
264 compatible = "ti,emif-4d5";
265 ti,hwmods = "emif2";
266 ti,no-idle-on-init;
267 phy-type = <2>; /* DDR PHY type: Intelli PHY */
268 reg = <0x4d000000 0x400>;
269 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
270 hw-caps-read-idle-ctrl;
271 hw-caps-ll-interface;
272 hw-caps-temp-alert;
273 };
275 aes1_target: target-module@4b501000 {
276 compatible = "ti,sysc-omap2", "ti,sysc";
277 reg = <0x4b501080 0x4>,
278 <0x4b501084 0x4>,
279 <0x4b501088 0x4>;
280 reg-names = "rev", "sysc", "syss";
281 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
282 SYSC_OMAP2_AUTOIDLE)>;
283 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
284 <SYSC_IDLE_NO>,
285 <SYSC_IDLE_SMART>,
286 <SYSC_IDLE_SMART_WKUP>;
287 ti,syss-mask = <1>;
288 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
289 clocks = <&l4sec_clkctrl OMAP5_AES1_CLKCTRL 0>;
290 clock-names = "fck";
291 #address-cells = <1>;
292 #size-cells = <1>;
293 ranges = <0x0 0x4b501000 0x1000>;
295 aes1: aes@0 {
296 compatible = "ti,omap4-aes";
297 reg = <0 0xa0>;
298 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
299 dmas = <&sdma 111>, <&sdma 110>;
300 dma-names = "tx", "rx";
301 };
302 };
304 aes2_target: target-module@4b701000 {
305 compatible = "ti,sysc-omap2", "ti,sysc";
306 reg = <0x4b701080 0x4>,
307 <0x4b701084 0x4>,
308 <0x4b701088 0x4>;
309 reg-names = "rev", "sysc", "syss";
310 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
311 SYSC_OMAP2_AUTOIDLE)>;
312 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
313 <SYSC_IDLE_NO>,
314 <SYSC_IDLE_SMART>,
315 <SYSC_IDLE_SMART_WKUP>;
316 ti,syss-mask = <1>;
317 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
318 clocks = <&l4sec_clkctrl OMAP5_AES2_CLKCTRL 0>;
319 clock-names = "fck";
320 #address-cells = <1>;
321 #size-cells = <1>;
322 ranges = <0x0 0x4b701000 0x1000>;
324 aes2: aes@0 {
325 compatible = "ti,omap4-aes";
326 reg = <0 0xa0>;
327 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
328 dmas = <&sdma 114>, <&sdma 113>;
329 dma-names = "tx", "rx";
330 };
331 };
333 sham_target: target-module@4b100000 {
334 compatible = "ti,sysc-omap3-sham", "ti,sysc";
335 reg = <0x4b100100 0x4>,
336 <0x4b100110 0x4>,
337 <0x4b100114 0x4>;
338 reg-names = "rev", "sysc", "syss";
339 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
340 SYSC_OMAP2_AUTOIDLE)>;
341 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
342 <SYSC_IDLE_NO>,
343 <SYSC_IDLE_SMART>;
344 ti,syss-mask = <1>;
345 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
346 clocks = <&l4sec_clkctrl OMAP5_SHA2MD5_CLKCTRL 0>;
347 clock-names = "fck";
348 #address-cells = <1>;
349 #size-cells = <1>;
350 ranges = <0x0 0x4b100000 0x1000>;
352 sham: sham@0 {
353 compatible = "ti,omap4-sham";
354 reg = <0 0x300>;
355 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
356 dmas = <&sdma 119>;
357 dma-names = "rx";
358 };
359 };
361 bandgap: bandgap@4a0021e0 {
362 reg = <0x4a0021e0 0xc
363 0x4a00232c 0xc
364 0x4a002380 0x2c
365 0x4a0023C0 0x3c>;
366 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
367 compatible = "ti,omap5430-bandgap";
369 #thermal-sensor-cells = <1>;
370 };
372 /* OCP2SCP3 */
373 sata: sata@4a141100 {
374 compatible = "snps,dwc-ahci";
375 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
376 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
377 phys = <&sata_phy>;
378 phy-names = "sata-phy";
379 clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
380 ti,hwmods = "sata";
381 ports-implemented = <0x1>;
382 };
384 target-module@56000000 {
385 compatible = "ti,sysc-omap4", "ti,sysc";
386 reg = <0x5600fe00 0x4>,
387 <0x5600fe10 0x4>;
388 reg-names = "rev", "sysc";
389 ti,sysc-midle = <SYSC_IDLE_FORCE>,
390 <SYSC_IDLE_NO>,
391 <SYSC_IDLE_SMART>;
392 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
393 <SYSC_IDLE_NO>,
394 <SYSC_IDLE_SMART>;
395 clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
396 clock-names = "fck";
397 #address-cells = <1>;
398 #size-cells = <1>;
399 ranges = <0 0x56000000 0x2000000>;
401 /*
402 * Closed source PowerVR driver, no child device
403 * binding or driver in mainline
404 */
405 };
407 target-module@58000000 {
408 compatible = "ti,sysc-omap2", "ti,sysc";
409 reg = <0x58000000 4>,
410 <0x58000014 4>;
411 reg-names = "rev", "syss";
412 ti,syss-mask = <1>;
413 power-domains = <&prm_dss>;
414 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
415 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
416 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
417 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
418 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
419 #address-cells = <1>;
420 #size-cells = <1>;
421 ranges = <0 0x58000000 0x1000000>;
423 dss: dss@0 {
424 compatible = "ti,omap5-dss";
425 reg = <0 0x80>;
426 status = "disabled";
427 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
428 clock-names = "fck";
429 #address-cells = <1>;
430 #size-cells = <1>;
431 ranges = <0 0 0x1000000>;
433 target-module@1000 {
434 compatible = "ti,sysc-omap2", "ti,sysc";
435 reg = <0x1000 0x4>,
436 <0x1010 0x4>,
437 <0x1014 0x4>;
438 reg-names = "rev", "sysc", "syss";
439 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
440 <SYSC_IDLE_NO>,
441 <SYSC_IDLE_SMART>;
442 ti,sysc-midle = <SYSC_IDLE_FORCE>,
443 <SYSC_IDLE_NO>,
444 <SYSC_IDLE_SMART>;
445 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
446 SYSC_OMAP2_ENAWAKEUP |
447 SYSC_OMAP2_SOFTRESET |
448 SYSC_OMAP2_AUTOIDLE)>;
449 ti,syss-mask = <1>;
450 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
451 clock-names = "fck";
452 #address-cells = <1>;
453 #size-cells = <1>;
454 ranges = <0 0x1000 0x1000>;
456 dispc@0 {
457 compatible = "ti,omap5-dispc";
458 reg = <0 0x1000>;
459 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
461 clock-names = "fck";
462 };
463 };
465 target-module@2000 {
466 compatible = "ti,sysc-omap2", "ti,sysc";
467 reg = <0x2000 0x4>,
468 <0x2010 0x4>,
469 <0x2014 0x4>;
470 reg-names = "rev", "sysc", "syss";
471 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
472 <SYSC_IDLE_NO>,
473 <SYSC_IDLE_SMART>;
474 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
475 SYSC_OMAP2_AUTOIDLE)>;
476 ti,syss-mask = <1>;
477 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
478 clock-names = "fck";
479 #address-cells = <1>;
480 #size-cells = <1>;
481 ranges = <0 0x2000 0x1000>;
483 rfbi: encoder@0 {
484 compatible = "ti,omap5-rfbi";
485 reg = <0 0x100>;
486 status = "disabled";
487 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
488 clock-names = "fck", "ick";
489 };
490 };
492 target-module@4000 {
493 compatible = "ti,sysc-omap2", "ti,sysc";
494 reg = <0x4000 0x4>,
495 <0x4010 0x4>,
496 <0x4014 0x4>;
497 reg-names = "rev", "sysc", "syss";
498 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
499 <SYSC_IDLE_NO>,
500 <SYSC_IDLE_SMART>;
501 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
502 SYSC_OMAP2_ENAWAKEUP |
503 SYSC_OMAP2_SOFTRESET |
504 SYSC_OMAP2_AUTOIDLE)>;
505 ti,syss-mask = <1>;
506 #address-cells = <1>;
507 #size-cells = <1>;
508 ranges = <0 0x4000 0x1000>;
510 dsi1: encoder@0 {
511 compatible = "ti,omap5-dsi";
512 reg = <0 0x200>,
513 <0x200 0x40>,
514 <0x300 0x40>;
515 reg-names = "proto", "phy", "pll";
516 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
517 status = "disabled";
518 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
519 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
520 clock-names = "fck", "sys_clk";
521 };
522 };
524 target-module@9000 {
525 compatible = "ti,sysc-omap2", "ti,sysc";
526 reg = <0x9000 0x4>,
527 <0x9010 0x4>,
528 <0x9014 0x4>;
529 reg-names = "rev", "sysc", "syss";
530 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
531 <SYSC_IDLE_NO>,
532 <SYSC_IDLE_SMART>;
533 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
534 SYSC_OMAP2_ENAWAKEUP |
535 SYSC_OMAP2_SOFTRESET |
536 SYSC_OMAP2_AUTOIDLE)>;
537 ti,syss-mask = <1>;
538 #address-cells = <1>;
539 #size-cells = <1>;
540 ranges = <0 0x9000 0x1000>;
542 dsi2: encoder@0 {
543 compatible = "ti,omap5-dsi";
544 reg = <0 0x200>,
545 <0x200 0x40>,
546 <0x300 0x40>;
547 reg-names = "proto", "phy", "pll";
548 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
549 status = "disabled";
550 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
551 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
552 clock-names = "fck", "sys_clk";
553 };
554 };
556 target-module@40000 {
557 compatible = "ti,sysc-omap4", "ti,sysc";
558 reg = <0x40000 0x4>,
559 <0x40010 0x4>;
560 reg-names = "rev", "sysc";
561 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
562 <SYSC_IDLE_NO>,
563 <SYSC_IDLE_SMART>,
564 <SYSC_IDLE_SMART_WKUP>;
565 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
566 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
567 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
568 clock-names = "fck", "dss_clk";
569 #address-cells = <1>;
570 #size-cells = <1>;
571 ranges = <0 0x40000 0x40000>;
573 hdmi: encoder@0 {
574 compatible = "ti,omap5-hdmi";
575 reg = <0 0x200>,
576 <0x200 0x80>,
577 <0x300 0x80>,
578 <0x20000 0x19000>;
579 reg-names = "wp", "pll", "phy", "core";
580 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
581 status = "disabled";
582 clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
583 <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
584 clock-names = "fck", "sys_clk";
585 dmas = <&sdma 76>;
586 dma-names = "audio_tx";
587 };
588 };
589 };
590 };
592 abb_mpu: regulator-abb-mpu {
593 compatible = "ti,abb-v2";
594 regulator-name = "abb_mpu";
595 #address-cells = <0>;
596 #size-cells = <0>;
597 clocks = <&sys_clkin>;
598 ti,settling-time = <50>;
599 ti,clock-cycles = <16>;
601 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
602 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
603 reg-names = "base-address", "int-address",
604 "efuse-address", "ldo-address";
605 ti,tranxdone-status-mask = <0x80>;
606 /* LDOVBBMPU_MUX_CTRL */
607 ti,ldovbb-override-mask = <0x400>;
608 /* LDOVBBMPU_VSET_OUT */
609 ti,ldovbb-vset-mask = <0x1F>;
611 /*
612 * NOTE: only FBB mode used but actual vset will
613 * determine final biasing
614 */
615 ti,abb_info = <
616 /*uV ABB efuse rbb_m fbb_m vset_m*/
617 1060000 0 0x0 0 0x02000000 0x01F00000
618 1250000 0 0x4 0 0x02000000 0x01F00000
619 >;
620 };
622 abb_mm: regulator-abb-mm {
623 compatible = "ti,abb-v2";
624 regulator-name = "abb_mm";
625 #address-cells = <0>;
626 #size-cells = <0>;
627 clocks = <&sys_clkin>;
628 ti,settling-time = <50>;
629 ti,clock-cycles = <16>;
631 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
632 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
633 reg-names = "base-address", "int-address",
634 "efuse-address", "ldo-address";
635 ti,tranxdone-status-mask = <0x80000000>;
636 /* LDOVBBMM_MUX_CTRL */
637 ti,ldovbb-override-mask = <0x400>;
638 /* LDOVBBMM_VSET_OUT */
639 ti,ldovbb-vset-mask = <0x1F>;
641 /*
642 * NOTE: only FBB mode used but actual vset will
643 * determine final biasing
644 */
645 ti,abb_info = <
646 /*uV ABB efuse rbb_m fbb_m vset_m*/
647 1025000 0 0x0 0 0x02000000 0x01F00000
648 1120000 0 0x4 0 0x02000000 0x01F00000
649 >;
650 };
651 };
652 };
654 &cpu_thermal {
655 polling-delay = <500>; /* milliseconds */
656 coefficients = <65 (-1791)>;
657 };
659 #include "omap5-l4.dtsi"
660 #include "omap54xx-clocks.dtsi"
662 &gpu_thermal {
663 coefficients = <117 (-2992)>;
664 };
666 &core_thermal {
667 coefficients = <0 2000>;
668 };
670 #include "omap5-l4-abe.dtsi"
671 #include "omap54xx-clocks.dtsi"
673 &prm {
674 prm_mpu: prm@300 {
675 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
676 reg = <0x300 0x100>;
677 #power-domain-cells = <0>;
678 };
680 prm_dsp: prm@400 {
681 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
682 reg = <0x400 0x100>;
683 #reset-cells = <1>;
684 #power-domain-cells = <0>;
685 };
687 prm_abe: prm@500 {
688 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
689 reg = <0x500 0x100>;
690 #power-domain-cells = <0>;
691 };
693 prm_coreaon: prm@600 {
694 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
695 reg = <0x600 0x100>;
696 #power-domain-cells = <0>;
697 };
699 prm_core: prm@700 {
700 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
701 reg = <0x700 0x100>;
702 #reset-cells = <1>;
703 #power-domain-cells = <0>;
704 };
706 prm_iva: prm@1200 {
707 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
708 reg = <0x1200 0x100>;
709 #reset-cells = <1>;
710 #power-domain-cells = <0>;
711 };
713 prm_cam: prm@1300 {
714 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
715 reg = <0x1300 0x100>;
716 #power-domain-cells = <0>;
717 };
719 prm_dss: prm@1400 {
720 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
721 reg = <0x1400 0x100>;
722 #power-domain-cells = <0>;
723 };
725 prm_gpu: prm@1500 {
726 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
727 reg = <0x1500 0x100>;
728 #power-domain-cells = <0>;
729 };
731 prm_l3init: prm@1600 {
732 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
733 reg = <0x1600 0x100>;
734 #power-domain-cells = <0>;
735 };
737 prm_custefuse: prm@1700 {
738 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
739 reg = <0x1700 0x100>;
740 #power-domain-cells = <0>;
741 };
743 prm_wkupaon: prm@1800 {
744 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
745 reg = <0x1800 0x100>;
746 #power-domain-cells = <0>;
747 };
749 prm_emu: prm@1a00 {
750 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
751 reg = <0x1a00 0x100>;
752 #power-domain-cells = <0>;
753 };
755 prm_device: prm@1c00 {
756 compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
757 reg = <0x1c00 0x100>;
758 #reset-cells = <1>;
759 };
760 };
762 /* Preferred always-on timer for clockevent */
763 &timer1_target {
764 ti,no-reset-on-init;
765 ti,no-idle;
766 timer@0 {
767 assigned-clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
768 assigned-clock-parents = <&sys_32k_ck>;
769 };
770 };