| blob | 74d8e2c8e4b343f55742b49ed8797793b67d2d20 |
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
4 */
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
16 model = "Qualcomm Technologies, Inc. IPQ4019";
17 compatible = "qcom,ipq4019";
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
22 #size-cells = <0x1>;
23 ranges;
25 smem_region: smem@87e00000 {
26 reg = <0x87e00000 0x080000>;
27 no-map;
28 };
30 tz@87e80000 {
31 reg = <0x87e80000 0x180000>;
32 no-map;
33 };
34 };
36 aliases {
37 spi0 = &blsp1_spi1;
38 spi1 = &blsp1_spi2;
39 i2c0 = &blsp1_i2c3;
40 i2c1 = &blsp1_i2c4;
41 };
43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46 cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a7";
49 enable-method = "qcom,kpss-acc-v2";
50 next-level-cache = <&L2>;
51 qcom,acc = <&acc0>;
52 qcom,saw = <&saw0>;
53 reg = <0x0>;
54 clocks = <&gcc GCC_APPS_CLK_SRC>;
55 clock-frequency = <0>;
56 clock-latency = <256000>;
57 operating-points-v2 = <&cpu0_opp_table>;
58 };
60 cpu@1 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a7";
63 enable-method = "qcom,kpss-acc-v2";
64 next-level-cache = <&L2>;
65 qcom,acc = <&acc1>;
66 qcom,saw = <&saw1>;
67 reg = <0x1>;
68 clocks = <&gcc GCC_APPS_CLK_SRC>;
69 clock-frequency = <0>;
70 clock-latency = <256000>;
71 operating-points-v2 = <&cpu0_opp_table>;
72 };
74 cpu@2 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a7";
77 enable-method = "qcom,kpss-acc-v2";
78 next-level-cache = <&L2>;
79 qcom,acc = <&acc2>;
80 qcom,saw = <&saw2>;
81 reg = <0x2>;
82 clocks = <&gcc GCC_APPS_CLK_SRC>;
83 clock-frequency = <0>;
84 clock-latency = <256000>;
85 operating-points-v2 = <&cpu0_opp_table>;
86 };
88 cpu@3 {
89 device_type = "cpu";
90 compatible = "arm,cortex-a7";
91 enable-method = "qcom,kpss-acc-v2";
92 next-level-cache = <&L2>;
93 qcom,acc = <&acc3>;
94 qcom,saw = <&saw3>;
95 reg = <0x3>;
96 clocks = <&gcc GCC_APPS_CLK_SRC>;
97 clock-frequency = <0>;
98 clock-latency = <256000>;
99 operating-points-v2 = <&cpu0_opp_table>;
100 };
102 L2: l2-cache {
103 compatible = "cache";
104 cache-level = <2>;
105 qcom,saw = <&saw_l2>;
106 };
107 };
109 cpu0_opp_table: opp_table0 {
110 compatible = "operating-points-v2";
111 opp-shared;
113 opp-48000000 {
114 opp-hz = /bits/ 64 <48000000>;
115 clock-latency-ns = <256000>;
116 };
117 opp-200000000 {
118 opp-hz = /bits/ 64 <200000000>;
119 clock-latency-ns = <256000>;
120 };
121 opp-500000000 {
122 opp-hz = /bits/ 64 <500000000>;
123 clock-latency-ns = <256000>;
124 };
125 opp-716000000 {
126 opp-hz = /bits/ 64 <716000000>;
127 clock-latency-ns = <256000>;
128 };
129 };
131 memory {
132 device_type = "memory";
133 reg = <0x0 0x0>;
134 };
136 pmu {
137 compatible = "arm,cortex-a7-pmu";
138 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) |
139 IRQ_TYPE_LEVEL_HIGH)>;
140 };
142 clocks {
143 sleep_clk: sleep_clk {
144 compatible = "fixed-clock";
145 clock-frequency = <32768>;
146 #clock-cells = <0>;
147 };
149 xo: xo {
150 compatible = "fixed-clock";
151 clock-frequency = <48000000>;
152 #clock-cells = <0>;
153 };
154 };
156 firmware {
157 scm {
158 compatible = "qcom,scm-ipq4019";
159 };
160 };
162 timer {
163 compatible = "arm,armv7-timer";
164 interrupts = <1 2 0xf08>,
165 <1 3 0xf08>,
166 <1 4 0xf08>,
167 <1 1 0xf08>;
168 clock-frequency = <48000000>;
169 always-on;
170 };
172 soc {
173 #address-cells = <1>;
174 #size-cells = <1>;
175 ranges;
176 compatible = "simple-bus";
178 intc: interrupt-controller@b000000 {
179 compatible = "qcom,msm-qgic2";
180 interrupt-controller;
181 #interrupt-cells = <3>;
182 reg = <0x0b000000 0x1000>,
183 <0x0b002000 0x1000>;
184 };
186 gcc: clock-controller@1800000 {
187 compatible = "qcom,gcc-ipq4019";
188 #clock-cells = <1>;
189 #reset-cells = <1>;
190 reg = <0x1800000 0x60000>;
191 };
193 rng@22000 {
194 compatible = "qcom,prng";
195 reg = <0x22000 0x140>;
196 clocks = <&gcc GCC_PRNG_AHB_CLK>;
197 clock-names = "core";
198 status = "disabled";
199 };
201 tlmm: pinctrl@1000000 {
202 compatible = "qcom,ipq4019-pinctrl";
203 reg = <0x01000000 0x300000>;
204 gpio-controller;
205 gpio-ranges = <&tlmm 0 0 100>;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <2>;
209 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
210 };
212 sdhci: sdhci@7824900 {
213 compatible = "qcom,sdhci-msm-v4";
214 reg = <0x7824900 0x11c>, <0x7824000 0x800>;
215 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
216 interrupt-names = "hc_irq", "pwr_irq";
217 bus-width = <8>;
218 clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>,
219 <&gcc GCC_DCD_XO_CLK>;
220 clock-names = "core", "iface", "xo";
221 status = "disabled";
222 };
224 blsp_dma: dma@7884000 {
225 compatible = "qcom,bam-v1.7.0";
226 reg = <0x07884000 0x23000>;
227 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
229 clock-names = "bam_clk";
230 #dma-cells = <1>;
231 qcom,ee = <0>;
232 status = "disabled";
233 };
235 blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
236 compatible = "qcom,spi-qup-v2.2.1";
237 reg = <0x78b5000 0x600>;
238 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
239 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
240 <&gcc GCC_BLSP1_AHB_CLK>;
241 clock-names = "core", "iface";
242 #address-cells = <1>;
243 #size-cells = <0>;
244 dmas = <&blsp_dma 5>, <&blsp_dma 4>;
245 dma-names = "rx", "tx";
246 status = "disabled";
247 };
249 blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
250 compatible = "qcom,spi-qup-v2.2.1";
251 reg = <0x78b6000 0x600>;
252 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
254 <&gcc GCC_BLSP1_AHB_CLK>;
255 clock-names = "core", "iface";
256 #address-cells = <1>;
257 #size-cells = <0>;
258 dmas = <&blsp_dma 7>, <&blsp_dma 6>;
259 dma-names = "rx", "tx";
260 status = "disabled";
261 };
263 blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
264 compatible = "qcom,i2c-qup-v2.2.1";
265 reg = <0x78b7000 0x600>;
266 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
268 <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
269 clock-names = "iface", "core";
270 #address-cells = <1>;
271 #size-cells = <0>;
272 dmas = <&blsp_dma 9>, <&blsp_dma 8>;
273 dma-names = "rx", "tx";
274 status = "disabled";
275 };
277 blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
278 compatible = "qcom,i2c-qup-v2.2.1";
279 reg = <0x78b8000 0x600>;
280 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&gcc GCC_BLSP1_AHB_CLK>,
282 <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
283 clock-names = "iface", "core";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 dmas = <&blsp_dma 11>, <&blsp_dma 10>;
287 dma-names = "rx", "tx";
288 status = "disabled";
289 };
291 cryptobam: dma@8e04000 {
292 compatible = "qcom,bam-v1.7.0";
293 reg = <0x08e04000 0x20000>;
294 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
296 clock-names = "bam_clk";
297 #dma-cells = <1>;
298 qcom,ee = <1>;
299 qcom,controlled-remotely;
300 status = "disabled";
301 };
303 crypto@8e3a000 {
304 compatible = "qcom,crypto-v5.1";
305 reg = <0x08e3a000 0x6000>;
306 clocks = <&gcc GCC_CRYPTO_AHB_CLK>,
307 <&gcc GCC_CRYPTO_AXI_CLK>,
308 <&gcc GCC_CRYPTO_CLK>;
309 clock-names = "iface", "bus", "core";
310 dmas = <&cryptobam 2>, <&cryptobam 3>;
311 dma-names = "rx", "tx";
312 status = "disabled";
313 };
315 acc0: clock-controller@b088000 {
316 compatible = "qcom,kpss-acc-v2";
317 reg = <0x0b088000 0x1000>, <0xb008000 0x1000>;
318 };
320 acc1: clock-controller@b098000 {
321 compatible = "qcom,kpss-acc-v2";
322 reg = <0x0b098000 0x1000>, <0xb008000 0x1000>;
323 };
325 acc2: clock-controller@b0a8000 {
326 compatible = "qcom,kpss-acc-v2";
327 reg = <0x0b0a8000 0x1000>, <0xb008000 0x1000>;
328 };
330 acc3: clock-controller@b0b8000 {
331 compatible = "qcom,kpss-acc-v2";
332 reg = <0x0b0b8000 0x1000>, <0xb008000 0x1000>;
333 };
335 saw0: regulator@b089000 {
336 compatible = "qcom,saw2";
337 reg = <0x0b089000 0x1000>, <0x0b009000 0x1000>;
338 regulator;
339 };
341 saw1: regulator@b099000 {
342 compatible = "qcom,saw2";
343 reg = <0x0b099000 0x1000>, <0x0b009000 0x1000>;
344 regulator;
345 };
347 saw2: regulator@b0a9000 {
348 compatible = "qcom,saw2";
349 reg = <0x0b0a9000 0x1000>, <0x0b009000 0x1000>;
350 regulator;
351 };
353 saw3: regulator@b0b9000 {
354 compatible = "qcom,saw2";
355 reg = <0x0b0b9000 0x1000>, <0x0b009000 0x1000>;
356 regulator;
357 };
359 saw_l2: regulator@b012000 {
360 compatible = "qcom,saw2";
361 reg = <0xb012000 0x1000>;
362 regulator;
363 };
365 blsp1_uart1: serial@78af000 {
366 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
367 reg = <0x78af000 0x200>;
368 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
369 status = "disabled";
370 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
371 <&gcc GCC_BLSP1_AHB_CLK>;
372 clock-names = "core", "iface";
373 dmas = <&blsp_dma 1>, <&blsp_dma 0>;
374 dma-names = "rx", "tx";
375 };
377 blsp1_uart2: serial@78b0000 {
378 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
379 reg = <0x78b0000 0x200>;
380 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
381 status = "disabled";
382 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
383 <&gcc GCC_BLSP1_AHB_CLK>;
384 clock-names = "core", "iface";
385 dmas = <&blsp_dma 3>, <&blsp_dma 2>;
386 dma-names = "rx", "tx";
387 };
389 watchdog@b017000 {
390 compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019";
391 reg = <0xb017000 0x40>;
392 clocks = <&sleep_clk>;
393 timeout-sec = <10>;
394 status = "disabled";
395 };
397 restart@4ab000 {
398 compatible = "qcom,pshold";
399 reg = <0x4ab000 0x4>;
400 };
402 pcie0: pci@40000000 {
403 compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
404 reg = <0x40000000 0xf1d
405 0x40000f20 0xa8
406 0x80000 0x2000
407 0x40100000 0x1000>;
408 reg-names = "dbi", "elbi", "parf", "config";
409 device_type = "pci";
410 linux,pci-domain = <0>;
411 bus-range = <0x00 0xff>;
412 num-lanes = <1>;
413 #address-cells = <3>;
414 #size-cells = <2>;
416 ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000>,
417 <0x82000000 0 0x40300000 0x40300000 0 0x00d00000>;
419 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
420 interrupt-names = "msi";
421 #interrupt-cells = <1>;
422 interrupt-map-mask = <0 0 0 0x7>;
423 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
424 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
425 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
426 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
427 clocks = <&gcc GCC_PCIE_AHB_CLK>,
428 <&gcc GCC_PCIE_AXI_M_CLK>,
429 <&gcc GCC_PCIE_AXI_S_CLK>;
430 clock-names = "aux",
431 "master_bus",
432 "slave_bus";
434 resets = <&gcc PCIE_AXI_M_ARES>,
435 <&gcc PCIE_AXI_S_ARES>,
436 <&gcc PCIE_PIPE_ARES>,
437 <&gcc PCIE_AXI_M_VMIDMT_ARES>,
438 <&gcc PCIE_AXI_S_XPU_ARES>,
439 <&gcc PCIE_PARF_XPU_ARES>,
440 <&gcc PCIE_PHY_ARES>,
441 <&gcc PCIE_AXI_M_STICKY_ARES>,
442 <&gcc PCIE_PIPE_STICKY_ARES>,
443 <&gcc PCIE_PWR_ARES>,
444 <&gcc PCIE_AHB_ARES>,
445 <&gcc PCIE_PHY_AHB_ARES>;
446 reset-names = "axi_m",
447 "axi_s",
448 "pipe",
449 "axi_m_vmid",
450 "axi_s_xpu",
451 "parf",
452 "phy",
453 "axi_m_sticky",
454 "pipe_sticky",
455 "pwr",
456 "ahb",
457 "phy_ahb";
459 status = "disabled";
460 };
462 qpic_bam: dma@7984000 {
463 compatible = "qcom,bam-v1.7.0";
464 reg = <0x7984000 0x1a000>;
465 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&gcc GCC_QPIC_CLK>;
467 clock-names = "bam_clk";
468 #dma-cells = <1>;
469 qcom,ee = <0>;
470 status = "disabled";
471 };
473 nand: qpic-nand@79b0000 {
474 compatible = "qcom,ipq4019-nand";
475 reg = <0x79b0000 0x1000>;
476 #address-cells = <1>;
477 #size-cells = <0>;
478 clocks = <&gcc GCC_QPIC_CLK>,
479 <&gcc GCC_QPIC_AHB_CLK>;
480 clock-names = "core", "aon";
482 dmas = <&qpic_bam 0>,
483 <&qpic_bam 1>,
484 <&qpic_bam 2>;
485 dma-names = "tx", "rx", "cmd";
486 status = "disabled";
488 nand@0 {
489 reg = <0>;
491 nand-ecc-strength = <4>;
492 nand-ecc-step-size = <512>;
493 nand-bus-width = <8>;
494 };
495 };
497 wifi0: wifi@a000000 {
498 compatible = "qcom,ipq4019-wifi";
499 reg = <0xa000000 0x200000>;
500 resets = <&gcc WIFI0_CPU_INIT_RESET>,
501 <&gcc WIFI0_RADIO_SRIF_RESET>,
502 <&gcc WIFI0_RADIO_WARM_RESET>,
503 <&gcc WIFI0_RADIO_COLD_RESET>,
504 <&gcc WIFI0_CORE_WARM_RESET>,
505 <&gcc WIFI0_CORE_COLD_RESET>;
506 reset-names = "wifi_cpu_init", "wifi_radio_srif",
507 "wifi_radio_warm", "wifi_radio_cold",
508 "wifi_core_warm", "wifi_core_cold";
509 clocks = <&gcc GCC_WCSS2G_CLK>,
510 <&gcc GCC_WCSS2G_REF_CLK>,
511 <&gcc GCC_WCSS2G_RTC_CLK>;
512 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
513 "wifi_wcss_rtc";
514 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
515 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
516 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
517 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
518 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
519 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
520 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
521 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
522 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
523 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
524 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
525 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
526 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
527 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
528 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
529 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
530 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
531 interrupt-names = "msi0", "msi1", "msi2", "msi3",
532 "msi4", "msi5", "msi6", "msi7",
533 "msi8", "msi9", "msi10", "msi11",
534 "msi12", "msi13", "msi14", "msi15",
535 "legacy";
536 status = "disabled";
537 };
539 wifi1: wifi@a800000 {
540 compatible = "qcom,ipq4019-wifi";
541 reg = <0xa800000 0x200000>;
542 resets = <&gcc WIFI1_CPU_INIT_RESET>,
543 <&gcc WIFI1_RADIO_SRIF_RESET>,
544 <&gcc WIFI1_RADIO_WARM_RESET>,
545 <&gcc WIFI1_RADIO_COLD_RESET>,
546 <&gcc WIFI1_CORE_WARM_RESET>,
547 <&gcc WIFI1_CORE_COLD_RESET>;
548 reset-names = "wifi_cpu_init", "wifi_radio_srif",
549 "wifi_radio_warm", "wifi_radio_cold",
550 "wifi_core_warm", "wifi_core_cold";
551 clocks = <&gcc GCC_WCSS5G_CLK>,
552 <&gcc GCC_WCSS5G_REF_CLK>,
553 <&gcc GCC_WCSS5G_RTC_CLK>;
554 clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
555 "wifi_wcss_rtc";
556 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
557 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
558 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
559 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
560 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
561 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
562 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
563 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
564 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
565 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
566 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
567 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
568 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
569 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
570 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
571 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
572 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "msi0", "msi1", "msi2", "msi3",
574 "msi4", "msi5", "msi6", "msi7",
575 "msi8", "msi9", "msi10", "msi11",
576 "msi12", "msi13", "msi14", "msi15",
577 "legacy";
578 status = "disabled";
579 };
581 mdio: mdio@90000 {
582 #address-cells = <1>;
583 #size-cells = <0>;
584 compatible = "qcom,ipq4019-mdio";
585 reg = <0x90000 0x64>;
586 status = "disabled";
588 ethphy0: ethernet-phy@0 {
589 reg = <0>;
590 };
592 ethphy1: ethernet-phy@1 {
593 reg = <1>;
594 };
596 ethphy2: ethernet-phy@2 {
597 reg = <2>;
598 };
600 ethphy3: ethernet-phy@3 {
601 reg = <3>;
602 };
604 ethphy4: ethernet-phy@4 {
605 reg = <4>;
606 };
607 };
608 };
609 };