| blob | 51f5f904f9eb967b317b824b2b1d1df4d5e46c19 |
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
12 / {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "Qualcomm MSM8974";
16 compatible = "qcom,msm8974";
17 interrupt-parent = <&intc>;
19 reserved-memory {
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
24 mpss_region: mpss@8000000 {
25 reg = <0x08000000 0x5100000>;
26 no-map;
27 };
29 mba_region: mba@d100000 {
30 reg = <0x0d100000 0x100000>;
31 no-map;
32 };
34 wcnss_region: wcnss@d200000 {
35 reg = <0x0d200000 0xa00000>;
36 no-map;
37 };
39 adsp_region: adsp@dc00000 {
40 reg = <0x0dc00000 0x1900000>;
41 no-map;
42 };
44 venus@f500000 {
45 reg = <0x0f500000 0x500000>;
46 no-map;
47 };
49 smem_region: smem@fa00000 {
50 reg = <0xfa00000 0x200000>;
51 no-map;
52 };
54 tz@fc00000 {
55 reg = <0x0fc00000 0x160000>;
56 no-map;
57 };
59 rfsa@fd60000 {
60 reg = <0x0fd60000 0x20000>;
61 no-map;
62 };
64 rmtfs@fd80000 {
65 compatible = "qcom,rmtfs-mem";
66 reg = <0x0fd80000 0x180000>;
67 no-map;
69 qcom,client-id = <1>;
70 };
71 };
73 cpus {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 interrupts = <GIC_PPI 9 0xf04>;
78 CPU0: cpu@0 {
79 compatible = "qcom,krait";
80 enable-method = "qcom,kpss-acc-v2";
81 device_type = "cpu";
82 reg = <0>;
83 next-level-cache = <&L2>;
84 qcom,acc = <&acc0>;
85 qcom,saw = <&saw0>;
86 cpu-idle-states = <&CPU_SPC>;
87 };
89 CPU1: cpu@1 {
90 compatible = "qcom,krait";
91 enable-method = "qcom,kpss-acc-v2";
92 device_type = "cpu";
93 reg = <1>;
94 next-level-cache = <&L2>;
95 qcom,acc = <&acc1>;
96 qcom,saw = <&saw1>;
97 cpu-idle-states = <&CPU_SPC>;
98 };
100 CPU2: cpu@2 {
101 compatible = "qcom,krait";
102 enable-method = "qcom,kpss-acc-v2";
103 device_type = "cpu";
104 reg = <2>;
105 next-level-cache = <&L2>;
106 qcom,acc = <&acc2>;
107 qcom,saw = <&saw2>;
108 cpu-idle-states = <&CPU_SPC>;
109 };
111 CPU3: cpu@3 {
112 compatible = "qcom,krait";
113 enable-method = "qcom,kpss-acc-v2";
114 device_type = "cpu";
115 reg = <3>;
116 next-level-cache = <&L2>;
117 qcom,acc = <&acc3>;
118 qcom,saw = <&saw3>;
119 cpu-idle-states = <&CPU_SPC>;
120 };
122 L2: l2-cache {
123 compatible = "cache";
124 cache-level = <2>;
125 qcom,saw = <&saw_l2>;
126 };
128 idle-states {
129 CPU_SPC: spc {
130 compatible = "qcom,idle-state-spc",
131 "arm,idle-state";
132 entry-latency-us = <150>;
133 exit-latency-us = <200>;
134 min-residency-us = <2000>;
135 };
136 };
137 };
139 memory {
140 device_type = "memory";
141 reg = <0x0 0x0>;
142 };
144 thermal-zones {
145 cpu-thermal0 {
146 polling-delay-passive = <250>;
147 polling-delay = <1000>;
149 thermal-sensors = <&tsens 5>;
151 trips {
152 cpu_alert0: trip0 {
153 temperature = <75000>;
154 hysteresis = <2000>;
155 type = "passive";
156 };
157 cpu_crit0: trip1 {
158 temperature = <110000>;
159 hysteresis = <2000>;
160 type = "critical";
161 };
162 };
163 };
165 cpu-thermal1 {
166 polling-delay-passive = <250>;
167 polling-delay = <1000>;
169 thermal-sensors = <&tsens 6>;
171 trips {
172 cpu_alert1: trip0 {
173 temperature = <75000>;
174 hysteresis = <2000>;
175 type = "passive";
176 };
177 cpu_crit1: trip1 {
178 temperature = <110000>;
179 hysteresis = <2000>;
180 type = "critical";
181 };
182 };
183 };
185 cpu-thermal2 {
186 polling-delay-passive = <250>;
187 polling-delay = <1000>;
189 thermal-sensors = <&tsens 7>;
191 trips {
192 cpu_alert2: trip0 {
193 temperature = <75000>;
194 hysteresis = <2000>;
195 type = "passive";
196 };
197 cpu_crit2: trip1 {
198 temperature = <110000>;
199 hysteresis = <2000>;
200 type = "critical";
201 };
202 };
203 };
205 cpu-thermal3 {
206 polling-delay-passive = <250>;
207 polling-delay = <1000>;
209 thermal-sensors = <&tsens 8>;
211 trips {
212 cpu_alert3: trip0 {
213 temperature = <75000>;
214 hysteresis = <2000>;
215 type = "passive";
216 };
217 cpu_crit3: trip1 {
218 temperature = <110000>;
219 hysteresis = <2000>;
220 type = "critical";
221 };
222 };
223 };
225 q6-dsp-thermal {
226 polling-delay-passive = <250>;
227 polling-delay = <1000>;
229 thermal-sensors = <&tsens 1>;
231 trips {
232 q6_dsp_alert0: trip-point0 {
233 temperature = <90000>;
234 hysteresis = <2000>;
235 type = "hot";
236 };
237 };
238 };
240 modemtx-thermal {
241 polling-delay-passive = <250>;
242 polling-delay = <1000>;
244 thermal-sensors = <&tsens 2>;
246 trips {
247 modemtx_alert0: trip-point0 {
248 temperature = <90000>;
249 hysteresis = <2000>;
250 type = "hot";
251 };
252 };
253 };
255 video-thermal {
256 polling-delay-passive = <250>;
257 polling-delay = <1000>;
259 thermal-sensors = <&tsens 3>;
261 trips {
262 video_alert0: trip-point0 {
263 temperature = <95000>;
264 hysteresis = <2000>;
265 type = "hot";
266 };
267 };
268 };
270 wlan-thermal {
271 polling-delay-passive = <250>;
272 polling-delay = <1000>;
274 thermal-sensors = <&tsens 4>;
276 trips {
277 wlan_alert0: trip-point0 {
278 temperature = <105000>;
279 hysteresis = <2000>;
280 type = "hot";
281 };
282 };
283 };
285 gpu-thermal-top {
286 polling-delay-passive = <250>;
287 polling-delay = <1000>;
289 thermal-sensors = <&tsens 9>;
291 trips {
292 gpu1_alert0: trip-point0 {
293 temperature = <90000>;
294 hysteresis = <2000>;
295 type = "hot";
296 };
297 };
298 };
300 gpu-thermal-bottom {
301 polling-delay-passive = <250>;
302 polling-delay = <1000>;
304 thermal-sensors = <&tsens 10>;
306 trips {
307 gpu2_alert0: trip-point0 {
308 temperature = <90000>;
309 hysteresis = <2000>;
310 type = "hot";
311 };
312 };
313 };
314 };
316 cpu-pmu {
317 compatible = "qcom,krait-pmu";
318 interrupts = <GIC_PPI 7 0xf04>;
319 };
321 clocks {
322 xo_board: xo_board {
323 compatible = "fixed-clock";
324 #clock-cells = <0>;
325 clock-frequency = <19200000>;
326 };
328 sleep_clk: sleep_clk {
329 compatible = "fixed-clock";
330 #clock-cells = <0>;
331 clock-frequency = <32768>;
332 };
333 };
335 timer {
336 compatible = "arm,armv7-timer";
337 interrupts = <GIC_PPI 2 0xf08>,
338 <GIC_PPI 3 0xf08>,
339 <GIC_PPI 4 0xf08>,
340 <GIC_PPI 1 0xf08>;
341 clock-frequency = <19200000>;
342 };
344 adsp-pil {
345 compatible = "qcom,msm8974-adsp-pil";
347 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
348 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
349 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
350 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
351 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
352 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
354 cx-supply = <&pm8841_s2>;
356 clocks = <&xo_board>;
357 clock-names = "xo";
359 memory-region = <&adsp_region>;
361 qcom,smem-states = <&adsp_smp2p_out 0>;
362 qcom,smem-state-names = "stop";
364 smd-edge {
365 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
367 qcom,ipc = <&apcs 8 8>;
368 qcom,smd-edge = <1>;
370 label = "lpass";
371 };
372 };
374 smem {
375 compatible = "qcom,smem";
377 memory-region = <&smem_region>;
378 qcom,rpm-msg-ram = <&rpm_msg_ram>;
380 hwlocks = <&tcsr_mutex 3>;
381 };
383 smp2p-adsp {
384 compatible = "qcom,smp2p";
385 qcom,smem = <443>, <429>;
387 interrupt-parent = <&intc>;
388 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
390 qcom,ipc = <&apcs 8 10>;
392 qcom,local-pid = <0>;
393 qcom,remote-pid = <2>;
395 adsp_smp2p_out: master-kernel {
396 qcom,entry-name = "master-kernel";
397 #qcom,smem-state-cells = <1>;
398 };
400 adsp_smp2p_in: slave-kernel {
401 qcom,entry-name = "slave-kernel";
403 interrupt-controller;
404 #interrupt-cells = <2>;
405 };
406 };
408 smp2p-modem {
409 compatible = "qcom,smp2p";
410 qcom,smem = <435>, <428>;
412 interrupt-parent = <&intc>;
413 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
415 qcom,ipc = <&apcs 8 14>;
417 qcom,local-pid = <0>;
418 qcom,remote-pid = <1>;
420 modem_smp2p_out: master-kernel {
421 qcom,entry-name = "master-kernel";
422 #qcom,smem-state-cells = <1>;
423 };
425 modem_smp2p_in: slave-kernel {
426 qcom,entry-name = "slave-kernel";
428 interrupt-controller;
429 #interrupt-cells = <2>;
430 };
431 };
433 smp2p-wcnss {
434 compatible = "qcom,smp2p";
435 qcom,smem = <451>, <431>;
437 interrupt-parent = <&intc>;
438 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
440 qcom,ipc = <&apcs 8 18>;
442 qcom,local-pid = <0>;
443 qcom,remote-pid = <4>;
445 wcnss_smp2p_out: master-kernel {
446 qcom,entry-name = "master-kernel";
448 #qcom,smem-state-cells = <1>;
449 };
451 wcnss_smp2p_in: slave-kernel {
452 qcom,entry-name = "slave-kernel";
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 };
457 };
459 smsm {
460 compatible = "qcom,smsm";
462 #address-cells = <1>;
463 #size-cells = <0>;
465 qcom,ipc-1 = <&apcs 8 13>;
466 qcom,ipc-2 = <&apcs 8 9>;
467 qcom,ipc-3 = <&apcs 8 19>;
469 apps_smsm: apps@0 {
470 reg = <0>;
472 #qcom,smem-state-cells = <1>;
473 };
475 modem_smsm: modem@1 {
476 reg = <1>;
477 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
479 interrupt-controller;
480 #interrupt-cells = <2>;
481 };
483 adsp_smsm: adsp@2 {
484 reg = <2>;
485 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 };
491 wcnss_smsm: wcnss@7 {
492 reg = <7>;
493 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
495 interrupt-controller;
496 #interrupt-cells = <2>;
497 };
498 };
500 firmware {
501 scm {
502 compatible = "qcom,scm";
503 clocks = <&gcc GCC_CE1_CLK>, <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>;
504 clock-names = "core", "bus", "iface";
505 };
506 };
508 soc: soc {
509 #address-cells = <1>;
510 #size-cells = <1>;
511 ranges;
512 compatible = "simple-bus";
514 intc: interrupt-controller@f9000000 {
515 compatible = "qcom,msm-qgic2";
516 interrupt-controller;
517 #interrupt-cells = <3>;
518 reg = <0xf9000000 0x1000>,
519 <0xf9002000 0x1000>;
520 };
522 apcs: syscon@f9011000 {
523 compatible = "syscon";
524 reg = <0xf9011000 0x1000>;
525 };
527 qfprom: qfprom@fc4bc000 {
528 #address-cells = <1>;
529 #size-cells = <1>;
530 compatible = "qcom,qfprom";
531 reg = <0xfc4bc000 0x1000>;
532 tsens_calib: calib@d0 {
533 reg = <0xd0 0x18>;
534 };
535 tsens_backup: backup@440 {
536 reg = <0x440 0x10>;
537 };
538 };
540 tsens: thermal-sensor@fc4a9000 {
541 compatible = "qcom,msm8974-tsens";
542 reg = <0xfc4a9000 0x1000>, /* TM */
543 <0xfc4a8000 0x1000>; /* SROT */
544 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
545 nvmem-cell-names = "calib", "calib_backup";
546 #qcom,sensors = <11>;
547 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
548 interrupt-names = "uplow";
549 #thermal-sensor-cells = <1>;
550 };
552 timer@f9020000 {
553 #address-cells = <1>;
554 #size-cells = <1>;
555 ranges;
556 compatible = "arm,armv7-timer-mem";
557 reg = <0xf9020000 0x1000>;
558 clock-frequency = <19200000>;
560 frame@f9021000 {
561 frame-number = <0>;
562 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
564 reg = <0xf9021000 0x1000>,
565 <0xf9022000 0x1000>;
566 };
568 frame@f9023000 {
569 frame-number = <1>;
570 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
571 reg = <0xf9023000 0x1000>;
572 status = "disabled";
573 };
575 frame@f9024000 {
576 frame-number = <2>;
577 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
578 reg = <0xf9024000 0x1000>;
579 status = "disabled";
580 };
582 frame@f9025000 {
583 frame-number = <3>;
584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
585 reg = <0xf9025000 0x1000>;
586 status = "disabled";
587 };
589 frame@f9026000 {
590 frame-number = <4>;
591 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
592 reg = <0xf9026000 0x1000>;
593 status = "disabled";
594 };
596 frame@f9027000 {
597 frame-number = <5>;
598 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
599 reg = <0xf9027000 0x1000>;
600 status = "disabled";
601 };
603 frame@f9028000 {
604 frame-number = <6>;
605 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
606 reg = <0xf9028000 0x1000>;
607 status = "disabled";
608 };
609 };
611 saw0: power-controller@f9089000 {
612 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
613 reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
614 };
616 saw1: power-controller@f9099000 {
617 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
618 reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
619 };
621 saw2: power-controller@f90a9000 {
622 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
623 reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
624 };
626 saw3: power-controller@f90b9000 {
627 compatible = "qcom,msm8974-saw2-v2.1-cpu", "qcom,saw2";
628 reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
629 };
631 saw_l2: power-controller@f9012000 {
632 compatible = "qcom,saw2";
633 reg = <0xf9012000 0x1000>;
634 regulator;
635 };
637 acc0: clock-controller@f9088000 {
638 compatible = "qcom,kpss-acc-v2";
639 reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>;
640 };
642 acc1: clock-controller@f9098000 {
643 compatible = "qcom,kpss-acc-v2";
644 reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>;
645 };
647 acc2: clock-controller@f90a8000 {
648 compatible = "qcom,kpss-acc-v2";
649 reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>;
650 };
652 acc3: clock-controller@f90b8000 {
653 compatible = "qcom,kpss-acc-v2";
654 reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>;
655 };
657 restart@fc4ab000 {
658 compatible = "qcom,pshold";
659 reg = <0xfc4ab000 0x4>;
660 };
662 gcc: clock-controller@fc400000 {
663 compatible = "qcom,gcc-msm8974";
664 #clock-cells = <1>;
665 #reset-cells = <1>;
666 #power-domain-cells = <1>;
667 reg = <0xfc400000 0x4000>;
668 };
670 tcsr: syscon@fd4a0000 {
671 compatible = "syscon";
672 reg = <0xfd4a0000 0x10000>;
673 };
675 tcsr_mutex_block: syscon@fd484000 {
676 compatible = "syscon";
677 reg = <0xfd484000 0x2000>;
678 };
680 mmcc: clock-controller@fd8c0000 {
681 compatible = "qcom,mmcc-msm8974";
682 #clock-cells = <1>;
683 #reset-cells = <1>;
684 #power-domain-cells = <1>;
685 reg = <0xfd8c0000 0x6000>;
686 };
688 tcsr_mutex: tcsr-mutex {
689 compatible = "qcom,tcsr-mutex";
690 syscon = <&tcsr_mutex_block 0 0x80>;
692 #hwlock-cells = <1>;
693 };
695 rpm_msg_ram: memory@fc428000 {
696 compatible = "qcom,rpm-msg-ram";
697 reg = <0xfc428000 0x4000>;
698 };
700 blsp1_uart1: serial@f991d000 {
701 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
702 reg = <0xf991d000 0x1000>;
703 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
705 clock-names = "core", "iface";
706 status = "disabled";
707 };
709 blsp1_uart2: serial@f991e000 {
710 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
711 reg = <0xf991e000 0x1000>;
712 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
714 clock-names = "core", "iface";
715 status = "disabled";
716 };
718 blsp2_uart10: serial@f9960000 {
719 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
720 reg = <0xf9960000 0x1000>;
721 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
722 clocks = <&gcc GCC_BLSP2_UART4_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
723 clock-names = "core", "iface";
724 status = "disabled";
725 };
727 sdhci@f9824900 {
728 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
729 reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
730 reg-names = "hc_mem", "core_mem";
731 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
733 interrupt-names = "hc_irq", "pwr_irq";
734 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
735 <&gcc GCC_SDCC1_AHB_CLK>,
736 <&xo_board>;
737 clock-names = "core", "iface", "xo";
738 status = "disabled";
739 };
741 sdhci@f9864900 {
742 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
743 reg = <0xf9864900 0x11c>, <0xf9864000 0x800>;
744 reg-names = "hc_mem", "core_mem";
745 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
747 interrupt-names = "hc_irq", "pwr_irq";
748 clocks = <&gcc GCC_SDCC3_APPS_CLK>,
749 <&gcc GCC_SDCC3_AHB_CLK>,
750 <&xo_board>;
751 clock-names = "core", "iface", "xo";
752 status = "disabled";
753 };
755 sdhci@f98a4900 {
756 compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
757 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
758 reg-names = "hc_mem", "core_mem";
759 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
761 interrupt-names = "hc_irq", "pwr_irq";
762 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
763 <&gcc GCC_SDCC2_AHB_CLK>,
764 <&xo_board>;
765 clock-names = "core", "iface", "xo";
766 status = "disabled";
767 };
769 otg: usb@f9a55000 {
770 compatible = "qcom,ci-hdrc";
771 reg = <0xf9a55000 0x200>,
772 <0xf9a55200 0x200>;
773 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
775 <&gcc GCC_USB_HS_SYSTEM_CLK>;
776 clock-names = "iface", "core";
777 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
778 assigned-clock-rates = <75000000>;
779 resets = <&gcc GCC_USB_HS_BCR>;
780 reset-names = "core";
781 phy_type = "ulpi";
782 dr_mode = "otg";
783 ahb-burst-config = <0>;
784 phy-names = "usb-phy";
785 status = "disabled";
786 #reset-cells = <1>;
788 ulpi {
789 usb_hs1_phy: phy@a {
790 compatible = "qcom,usb-hs-phy-msm8974",
791 "qcom,usb-hs-phy";
792 #phy-cells = <0>;
793 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
794 clock-names = "ref", "sleep";
795 resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>;
796 reset-names = "phy", "por";
797 status = "disabled";
798 };
800 usb_hs2_phy: phy@b {
801 compatible = "qcom,usb-hs-phy-msm8974",
802 "qcom,usb-hs-phy";
803 #phy-cells = <0>;
804 clocks = <&xo_board>, <&gcc GCC_USB2B_PHY_SLEEP_CLK>;
805 clock-names = "ref", "sleep";
806 resets = <&gcc GCC_USB2B_PHY_BCR>, <&otg 1>;
807 reset-names = "phy", "por";
808 status = "disabled";
809 };
810 };
811 };
813 rng@f9bff000 {
814 compatible = "qcom,prng";
815 reg = <0xf9bff000 0x200>;
816 clocks = <&gcc GCC_PRNG_AHB_CLK>;
817 clock-names = "core";
818 };
820 remoteproc@fc880000 {
821 compatible = "qcom,msm8974-mss-pil";
822 reg = <0xfc880000 0x100>, <0xfc820000 0x020>;
823 reg-names = "qdsp6", "rmb";
825 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>,
826 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
827 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
828 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
829 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
830 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
832 clocks = <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
833 <&gcc GCC_MSS_CFG_AHB_CLK>,
834 <&gcc GCC_BOOT_ROM_AHB_CLK>,
835 <&xo_board>;
836 clock-names = "iface", "bus", "mem", "xo";
838 resets = <&gcc GCC_MSS_RESTART>;
839 reset-names = "mss_restart";
841 cx-supply = <&pm8841_s2>;
842 mss-supply = <&pm8841_s3>;
843 mx-supply = <&pm8841_s1>;
844 pll-supply = <&pm8941_l12>;
846 qcom,halt-regs = <&tcsr_mutex_block 0x1180 0x1200 0x1280>;
848 qcom,smem-states = <&modem_smp2p_out 0>;
849 qcom,smem-state-names = "stop";
851 mba {
852 memory-region = <&mba_region>;
853 };
855 mpss {
856 memory-region = <&mpss_region>;
857 };
859 smd-edge {
860 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
862 qcom,ipc = <&apcs 8 12>;
863 qcom,smd-edge = <0>;
865 label = "modem";
866 };
867 };
869 pronto: remoteproc@fb21b000 {
870 compatible = "qcom,pronto-v2-pil", "qcom,pronto";
871 reg = <0xfb204000 0x2000>, <0xfb202000 0x1000>, <0xfb21b000 0x3000>;
872 reg-names = "ccu", "dxe", "pmu";
874 memory-region = <&wcnss_region>;
876 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>,
877 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
878 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
879 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
880 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
881 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack";
883 vddpx-supply = <&pm8941_s3>;
885 qcom,smem-states = <&wcnss_smp2p_out 0>;
886 qcom,smem-state-names = "stop";
888 status = "disabled";
890 iris {
891 compatible = "qcom,wcn3680";
893 clocks = <&rpmcc RPM_SMD_CXO_A2>;
894 clock-names = "xo";
896 vddxo-supply = <&pm8941_l6>;
897 vddrfa-supply = <&pm8941_l11>;
898 vddpa-supply = <&pm8941_l19>;
899 vdddig-supply = <&pm8941_s3>;
900 };
902 smd-edge {
903 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>;
905 qcom,ipc = <&apcs 8 17>;
906 qcom,smd-edge = <6>;
908 wcnss {
909 compatible = "qcom,wcnss";
910 qcom,smd-channels = "WCNSS_CTRL";
911 status = "disabled";
913 qcom,mmio = <&pronto>;
915 bt {
916 compatible = "qcom,wcnss-bt";
917 };
919 wifi {
920 compatible = "qcom,wcnss-wlan";
922 interrupts = <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>,
923 <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>;
924 interrupt-names = "tx", "rx";
926 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
927 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
928 };
929 };
930 };
931 };
933 msmgpio: pinctrl@fd510000 {
934 compatible = "qcom,msm8974-pinctrl";
935 reg = <0xfd510000 0x4000>;
936 gpio-controller;
937 gpio-ranges = <&msmgpio 0 0 146>;
938 #gpio-cells = <2>;
939 interrupt-controller;
940 #interrupt-cells = <2>;
941 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
942 };
944 i2c@f9923000 {
945 status = "disabled";
946 compatible = "qcom,i2c-qup-v2.1.1";
947 reg = <0xf9923000 0x1000>;
948 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
950 clock-names = "core", "iface";
951 #address-cells = <1>;
952 #size-cells = <0>;
953 };
955 i2c@f9924000 {
956 status = "disabled";
957 compatible = "qcom,i2c-qup-v2.1.1";
958 reg = <0xf9924000 0x1000>;
959 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
961 clock-names = "core", "iface";
962 #address-cells = <1>;
963 #size-cells = <0>;
964 };
966 blsp_i2c3: i2c@f9925000 {
967 status = "disabled";
968 compatible = "qcom,i2c-qup-v2.1.1";
969 reg = <0xf9925000 0x1000>;
970 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
972 clock-names = "core", "iface";
973 #address-cells = <1>;
974 #size-cells = <0>;
975 };
977 blsp_i2c6: i2c@f9928000 {
978 status = "disabled";
979 compatible = "qcom,i2c-qup-v2.1.1";
980 reg = <0xf9928000 0x1000>;
981 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
983 clock-names = "core", "iface";
984 #address-cells = <1>;
985 #size-cells = <0>;
986 };
988 blsp_i2c8: i2c@f9964000 {
989 status = "disabled";
990 compatible = "qcom,i2c-qup-v2.1.1";
991 reg = <0xf9964000 0x1000>;
992 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
994 clock-names = "core", "iface";
995 #address-cells = <1>;
996 #size-cells = <0>;
997 };
999 blsp_i2c11: i2c@f9967000 {
1000 status = "disabled";
1001 compatible = "qcom,i2c-qup-v2.1.1";
1002 reg = <0xf9967000 0x1000>;
1003 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1005 clock-names = "core", "iface";
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1008 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
1009 dma-names = "tx", "rx";
1010 };
1012 blsp_i2c12: i2c@f9968000 {
1013 status = "disabled";
1014 compatible = "qcom,i2c-qup-v2.1.1";
1015 reg = <0xf9968000 0x1000>;
1016 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
1017 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1018 clock-names = "core", "iface";
1019 #address-cells = <1>;
1020 #size-cells = <0>;
1021 };
1023 spmi_bus: spmi@fc4cf000 {
1024 compatible = "qcom,spmi-pmic-arb";
1025 reg-names = "core", "intr", "cnfg";
1026 reg = <0xfc4cf000 0x1000>,
1027 <0xfc4cb000 0x1000>,
1028 <0xfc4ca000 0x1000>;
1029 interrupt-names = "periph_irq";
1030 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1031 qcom,ee = <0>;
1032 qcom,channel = <0>;
1033 #address-cells = <2>;
1034 #size-cells = <0>;
1035 interrupt-controller;
1036 #interrupt-cells = <4>;
1037 };
1039 blsp2_dma: dma-controller@f9944000 {
1040 compatible = "qcom,bam-v1.4.0";
1041 reg = <0xf9944000 0x19000>;
1042 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
1043 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1044 clock-names = "bam_clk";
1045 #dma-cells = <1>;
1046 qcom,ee = <0>;
1047 };
1049 etr@fc322000 {
1050 compatible = "arm,coresight-tmc", "arm,primecell";
1051 reg = <0xfc322000 0x1000>;
1053 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1054 clock-names = "apb_pclk", "atclk";
1056 in-ports {
1057 port {
1058 etr_in: endpoint {
1059 remote-endpoint = <&replicator_out0>;
1060 };
1061 };
1062 };
1063 };
1065 tpiu@fc318000 {
1066 compatible = "arm,coresight-tpiu", "arm,primecell";
1067 reg = <0xfc318000 0x1000>;
1069 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1070 clock-names = "apb_pclk", "atclk";
1072 in-ports {
1073 port {
1074 tpiu_in: endpoint {
1075 remote-endpoint = <&replicator_out1>;
1076 };
1077 };
1078 };
1079 };
1081 replicator@fc31c000 {
1082 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1083 reg = <0xfc31c000 0x1000>;
1085 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1086 clock-names = "apb_pclk", "atclk";
1088 out-ports {
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1092 port@0 {
1093 reg = <0>;
1094 replicator_out0: endpoint {
1095 remote-endpoint = <&etr_in>;
1096 };
1097 };
1098 port@1 {
1099 reg = <1>;
1100 replicator_out1: endpoint {
1101 remote-endpoint = <&tpiu_in>;
1102 };
1103 };
1104 };
1106 in-ports {
1107 port {
1108 replicator_in: endpoint {
1109 remote-endpoint = <&etf_out>;
1110 };
1111 };
1112 };
1113 };
1115 etf@fc307000 {
1116 compatible = "arm,coresight-tmc", "arm,primecell";
1117 reg = <0xfc307000 0x1000>;
1119 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1120 clock-names = "apb_pclk", "atclk";
1122 out-ports {
1123 port {
1124 etf_out: endpoint {
1125 remote-endpoint = <&replicator_in>;
1126 };
1127 };
1128 };
1130 in-ports {
1131 port {
1132 etf_in: endpoint {
1133 remote-endpoint = <&merger_out>;
1134 };
1135 };
1136 };
1137 };
1139 funnel@fc31b000 {
1140 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1141 reg = <0xfc31b000 0x1000>;
1143 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1144 clock-names = "apb_pclk", "atclk";
1146 in-ports {
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1150 /*
1151 * Not described input ports:
1152 * 0 - connected trought funnel to Audio, Modem and
1153 * Resource and Power Manager CPU's
1154 * 2...7 - not-connected
1155 */
1156 port@1 {
1157 reg = <1>;
1158 merger_in1: endpoint {
1159 remote-endpoint = <&funnel1_out>;
1160 };
1161 };
1162 };
1164 out-ports {
1165 port {
1166 merger_out: endpoint {
1167 remote-endpoint = <&etf_in>;
1168 };
1169 };
1170 };
1171 };
1173 funnel@fc31a000 {
1174 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1175 reg = <0xfc31a000 0x1000>;
1177 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1178 clock-names = "apb_pclk", "atclk";
1180 in-ports {
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1184 /*
1185 * Not described input ports:
1186 * 0 - not-connected
1187 * 1 - connected trought funnel to Multimedia CPU
1188 * 2 - connected to Wireless CPU
1189 * 3 - not-connected
1190 * 4 - not-connected
1191 * 6 - not-connected
1192 * 7 - connected to STM
1193 */
1194 port@5 {
1195 reg = <5>;
1196 funnel1_in5: endpoint {
1197 remote-endpoint = <&kpss_out>;
1198 };
1199 };
1200 };
1202 out-ports {
1203 port {
1204 funnel1_out: endpoint {
1205 remote-endpoint = <&merger_in1>;
1206 };
1207 };
1208 };
1209 };
1211 funnel@fc345000 { /* KPSS funnel only 4 inputs are used */
1212 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1213 reg = <0xfc345000 0x1000>;
1215 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1216 clock-names = "apb_pclk", "atclk";
1218 in-ports {
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1222 port@0 {
1223 reg = <0>;
1224 kpss_in0: endpoint {
1225 remote-endpoint = <&etm0_out>;
1226 };
1227 };
1228 port@1 {
1229 reg = <1>;
1230 kpss_in1: endpoint {
1231 remote-endpoint = <&etm1_out>;
1232 };
1233 };
1234 port@2 {
1235 reg = <2>;
1236 kpss_in2: endpoint {
1237 remote-endpoint = <&etm2_out>;
1238 };
1239 };
1240 port@3 {
1241 reg = <3>;
1242 kpss_in3: endpoint {
1243 remote-endpoint = <&etm3_out>;
1244 };
1245 };
1246 };
1248 out-ports {
1249 port {
1250 kpss_out: endpoint {
1251 remote-endpoint = <&funnel1_in5>;
1252 };
1253 };
1254 };
1255 };
1257 etm@fc33c000 {
1258 compatible = "arm,coresight-etm4x", "arm,primecell";
1259 reg = <0xfc33c000 0x1000>;
1261 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1262 clock-names = "apb_pclk", "atclk";
1264 cpu = <&CPU0>;
1266 out-ports {
1267 port {
1268 etm0_out: endpoint {
1269 remote-endpoint = <&kpss_in0>;
1270 };
1271 };
1272 };
1273 };
1275 etm@fc33d000 {
1276 compatible = "arm,coresight-etm4x", "arm,primecell";
1277 reg = <0xfc33d000 0x1000>;
1279 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1280 clock-names = "apb_pclk", "atclk";
1282 cpu = <&CPU1>;
1284 out-ports {
1285 port {
1286 etm1_out: endpoint {
1287 remote-endpoint = <&kpss_in1>;
1288 };
1289 };
1290 };
1291 };
1293 etm@fc33e000 {
1294 compatible = "arm,coresight-etm4x", "arm,primecell";
1295 reg = <0xfc33e000 0x1000>;
1297 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1298 clock-names = "apb_pclk", "atclk";
1300 cpu = <&CPU2>;
1302 out-ports {
1303 port {
1304 etm2_out: endpoint {
1305 remote-endpoint = <&kpss_in2>;
1306 };
1307 };
1308 };
1309 };
1311 etm@fc33f000 {
1312 compatible = "arm,coresight-etm4x", "arm,primecell";
1313 reg = <0xfc33f000 0x1000>;
1315 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
1316 clock-names = "apb_pclk", "atclk";
1318 cpu = <&CPU3>;
1320 out-ports {
1321 port {
1322 etm3_out: endpoint {
1323 remote-endpoint = <&kpss_in3>;
1324 };
1325 };
1326 };
1327 };
1329 ocmem@fdd00000 {
1330 compatible = "qcom,msm8974-ocmem";
1331 reg = <0xfdd00000 0x2000>,
1332 <0xfec00000 0x180000>;
1333 reg-names = "ctrl",
1334 "mem";
1335 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1336 <&mmcc OCMEMCX_OCMEMNOC_CLK>;
1337 clock-names = "core",
1338 "iface";
1340 #address-cells = <1>;
1341 #size-cells = <1>;
1343 gmu_sram: gmu-sram@0 {
1344 reg = <0x0 0x100000>;
1345 };
1346 };
1348 bimc: interconnect@fc380000 {
1349 reg = <0xfc380000 0x6a000>;
1350 compatible = "qcom,msm8974-bimc";
1351 #interconnect-cells = <1>;
1352 clock-names = "bus", "bus_a";
1353 clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
1354 <&rpmcc RPM_SMD_BIMC_A_CLK>;
1355 };
1357 snoc: interconnect@fc460000 {
1358 reg = <0xfc460000 0x4000>;
1359 compatible = "qcom,msm8974-snoc";
1360 #interconnect-cells = <1>;
1361 clock-names = "bus", "bus_a";
1362 clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
1363 <&rpmcc RPM_SMD_SNOC_A_CLK>;
1364 };
1366 pnoc: interconnect@fc468000 {
1367 reg = <0xfc468000 0x4000>;
1368 compatible = "qcom,msm8974-pnoc";
1369 #interconnect-cells = <1>;
1370 clock-names = "bus", "bus_a";
1371 clocks = <&rpmcc RPM_SMD_PNOC_CLK>,
1372 <&rpmcc RPM_SMD_PNOC_A_CLK>;
1373 };
1375 ocmemnoc: interconnect@fc470000 {
1376 reg = <0xfc470000 0x4000>;
1377 compatible = "qcom,msm8974-ocmemnoc";
1378 #interconnect-cells = <1>;
1379 clock-names = "bus", "bus_a";
1380 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>,
1381 <&rpmcc RPM_SMD_OCMEMGX_A_CLK>;
1382 };
1384 mmssnoc: interconnect@fc478000 {
1385 reg = <0xfc478000 0x4000>;
1386 compatible = "qcom,msm8974-mmssnoc";
1387 #interconnect-cells = <1>;
1388 clock-names = "bus", "bus_a";
1389 clocks = <&mmcc MMSS_S0_AXI_CLK>,
1390 <&mmcc MMSS_S0_AXI_CLK>;
1391 };
1393 cnoc: interconnect@fc480000 {
1394 reg = <0xfc480000 0x4000>;
1395 compatible = "qcom,msm8974-cnoc";
1396 #interconnect-cells = <1>;
1397 clock-names = "bus", "bus_a";
1398 clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
1399 <&rpmcc RPM_SMD_CNOC_A_CLK>;
1400 };
1402 mdss: mdss@fd900000 {
1403 status = "disabled";
1405 compatible = "qcom,mdss";
1406 reg = <0xfd900000 0x100>,
1407 <0xfd924000 0x1000>;
1408 reg-names = "mdss_phys",
1409 "vbif_phys";
1411 power-domains = <&mmcc MDSS_GDSC>;
1413 clocks = <&mmcc MDSS_AHB_CLK>,
1414 <&mmcc MDSS_AXI_CLK>,
1415 <&mmcc MDSS_VSYNC_CLK>;
1416 clock-names = "iface",
1417 "bus",
1418 "vsync";
1420 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1422 interrupt-controller;
1423 #interrupt-cells = <1>;
1425 #address-cells = <1>;
1426 #size-cells = <1>;
1427 ranges;
1429 mdp: mdp@fd900000 {
1430 status = "disabled";
1432 compatible = "qcom,mdp5";
1433 reg = <0xfd900100 0x22000>;
1434 reg-names = "mdp_phys";
1436 interrupt-parent = <&mdss>;
1437 interrupts = <0 0>;
1439 clocks = <&mmcc MDSS_AHB_CLK>,
1440 <&mmcc MDSS_AXI_CLK>,
1441 <&mmcc MDSS_MDP_CLK>,
1442 <&mmcc MDSS_VSYNC_CLK>;
1443 clock-names = "iface",
1444 "bus",
1445 "core",
1446 "vsync";
1448 interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;
1449 interconnect-names = "mdp0-mem";
1451 ports {
1452 #address-cells = <1>;
1453 #size-cells = <0>;
1455 port@0 {
1456 reg = <0>;
1457 mdp5_intf1_out: endpoint {
1458 remote-endpoint = <&dsi0_in>;
1459 };
1460 };
1461 };
1462 };
1464 dsi0: dsi@fd922800 {
1465 status = "disabled";
1467 compatible = "qcom,mdss-dsi-ctrl";
1468 reg = <0xfd922800 0x1f8>;
1469 reg-names = "dsi_ctrl";
1471 interrupt-parent = <&mdss>;
1472 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
1474 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
1475 <&mmcc PCLK0_CLK_SRC>;
1476 assigned-clock-parents = <&dsi_phy0 0>,
1477 <&dsi_phy0 1>;
1479 clocks = <&mmcc MDSS_MDP_CLK>,
1480 <&mmcc MDSS_AHB_CLK>,
1481 <&mmcc MDSS_AXI_CLK>,
1482 <&mmcc MDSS_BYTE0_CLK>,
1483 <&mmcc MDSS_PCLK0_CLK>,
1484 <&mmcc MDSS_ESC0_CLK>,
1485 <&mmcc MMSS_MISC_AHB_CLK>;
1486 clock-names = "mdp_core",
1487 "iface",
1488 "bus",
1489 "byte",
1490 "pixel",
1491 "core",
1492 "core_mmss";
1494 phys = <&dsi_phy0>;
1495 phy-names = "dsi-phy";
1497 ports {
1498 #address-cells = <1>;
1499 #size-cells = <0>;
1501 port@0 {
1502 reg = <0>;
1503 dsi0_in: endpoint {
1504 remote-endpoint = <&mdp5_intf1_out>;
1505 };
1506 };
1508 port@1 {
1509 reg = <1>;
1510 dsi0_out: endpoint {
1511 };
1512 };
1513 };
1514 };
1516 dsi_phy0: dsi-phy@fd922a00 {
1517 status = "disabled";
1519 compatible = "qcom,dsi-phy-28nm-hpm";
1520 reg = <0xfd922a00 0xd4>,
1521 <0xfd922b00 0x280>,
1522 <0xfd922d80 0x30>;
1523 reg-names = "dsi_pll",
1524 "dsi_phy",
1525 "dsi_phy_regulator";
1527 #clock-cells = <1>;
1528 #phy-cells = <0>;
1529 qcom,dsi-phy-index = <0>;
1531 clocks = <&mmcc MDSS_AHB_CLK>;
1532 clock-names = "iface";
1533 };
1534 };
1536 imem@fe805000 {
1537 status = "disabled";
1538 compatible = "syscon", "simple-mfd";
1539 reg = <0xfe805000 0x1000>;
1541 reboot-mode {
1542 compatible = "syscon-reboot-mode";
1543 offset = <0x65c>;
1544 };
1545 };
1546 };
1548 smd {
1549 compatible = "qcom,smd";
1551 rpm {
1552 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
1553 qcom,ipc = <&apcs 8 0>;
1554 qcom,smd-edge = <15>;
1556 rpm_requests {
1557 compatible = "qcom,rpm-msm8974";
1558 qcom,smd-channels = "rpm_requests";
1560 rpmcc: clock-controller {
1561 compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc";
1562 #clock-cells = <1>;
1563 };
1565 pm8841-regulators {
1566 compatible = "qcom,rpm-pm8841-regulators";
1568 pm8841_s1: s1 {};
1569 pm8841_s2: s2 {};
1570 pm8841_s3: s3 {};
1571 pm8841_s4: s4 {};
1572 pm8841_s5: s5 {};
1573 pm8841_s6: s6 {};
1574 pm8841_s7: s7 {};
1575 pm8841_s8: s8 {};
1576 };
1578 pm8941-regulators {
1579 compatible = "qcom,rpm-pm8941-regulators";
1581 pm8941_s1: s1 {};
1582 pm8941_s2: s2 {};
1583 pm8941_s3: s3 {};
1585 pm8941_l1: l1 {};
1586 pm8941_l2: l2 {};
1587 pm8941_l3: l3 {};
1588 pm8941_l4: l4 {};
1589 pm8941_l5: l5 {};
1590 pm8941_l6: l6 {};
1591 pm8941_l7: l7 {};
1592 pm8941_l8: l8 {};
1593 pm8941_l9: l9 {};
1594 pm8941_l10: l10 {};
1595 pm8941_l11: l11 {};
1596 pm8941_l12: l12 {};
1597 pm8941_l13: l13 {};
1598 pm8941_l14: l14 {};
1599 pm8941_l15: l15 {};
1600 pm8941_l16: l16 {};
1601 pm8941_l17: l17 {};
1602 pm8941_l18: l18 {};
1603 pm8941_l19: l19 {};
1604 pm8941_l20: l20 {};
1605 pm8941_l21: l21 {};
1606 pm8941_l22: l22 {};
1607 pm8941_l23: l23 {};
1608 pm8941_l24: l24 {};
1610 pm8941_lvs1: lvs1 {};
1611 pm8941_lvs2: lvs2 {};
1612 pm8941_lvs3: lvs3 {};
1613 };
1614 };
1615 };
1616 };
1618 vreg_boost: vreg-boost {
1619 compatible = "regulator-fixed";
1621 regulator-name = "vreg-boost";
1622 regulator-min-microvolt = <3150000>;
1623 regulator-max-microvolt = <3150000>;
1625 regulator-always-on;
1626 regulator-boot-on;
1628 gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>;
1629 enable-active-high;
1631 pinctrl-names = "default";
1632 pinctrl-0 = <&boost_bypass_n_pin>;
1633 };
1634 vreg_vph_pwr: vreg-vph-pwr {
1635 compatible = "regulator-fixed";
1636 regulator-name = "vph-pwr";
1638 regulator-min-microvolt = <3600000>;
1639 regulator-max-microvolt = <3600000>;
1641 regulator-always-on;
1642 };
1643 };