WIP FPC-III support
[linux/fpc-iii.git] / arch / arm / boot / dts / r8a7743-sk-rzg1m.dts
blob807e7d0d6b620c83a3e9c3116c82e7bfb501ce64
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Device Tree Source for the SK-RZG1M board
4  *
5  * Copyright (C) 2016-2017 Cogent Embedded, Inc.
6  */
8 /dts-v1/;
9 #include "r8a7743.dtsi"
11 / {
12         model = "SK-RZG1M";
13         compatible = "renesas,sk-rzg1m", "renesas,r8a7743";
15         aliases {
16                 serial0 = &scif0;
17         };
19         chosen {
20                 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
21                 stdout-path = "serial0:115200n8";
22         };
24         memory@40000000 {
25                 device_type = "memory";
26                 reg = <0 0x40000000 0 0x40000000>;
27         };
29         memory@200000000 {
30                 device_type = "memory";
31                 reg = <2 0x00000000 0 0x40000000>;
32         };
35 &extal_clk {
36         clock-frequency = <20000000>;
39 &pfc {
40         scif0_pins: scif0 {
41                 groups = "scif0_data_d";
42                 function = "scif0";
43         };
45         ether_pins: ether {
46                 groups = "eth_link", "eth_mdio", "eth_rmii";
47                 function = "eth";
48         };
50         phy1_pins: phy1 {
51                 groups = "intc_irq0";
52                 function = "intc";
53         };
56 &scif0 {
57         pinctrl-0 = <&scif0_pins>;
58         pinctrl-names = "default";
60         status = "okay";
63 &ether {
64         pinctrl-0 = <&ether_pins &phy1_pins>;
65         pinctrl-names = "default";
67         phy-handle = <&phy1>;
68         renesas,ether-link-active-low;
69         status = "okay";
71         phy1: ethernet-phy@1 {
72                 reg = <1>;
73                 interrupt-parent = <&irqc>;
74                 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
75                 micrel,led-mode = <1>;
76         };