arch/arm/boot/dts/rk3xxx.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2013 MundoReader S.L.
   4  * Author: Heiko Stuebner <heiko@sntech.de>
   5  */
   6
   7 #include <dt-bindings/interrupt-controller/irq.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/soc/rockchip,boot-mode.h>
  10
  11 / {
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14
  15         interrupt-parent = <&gic>;
  16
  17         aliases {
  18                 ethernet0 = &emac;
  19                 i2c0 = &i2c0;
  20                 i2c1 = &i2c1;
  21                 i2c2 = &i2c2;
  22                 i2c3 = &i2c3;
  23                 i2c4 = &i2c4;
  24                 mshc0 = &emmc;
  25                 mshc1 = &mmc0;
  26                 mshc2 = &mmc1;
  27                 serial0 = &uart0;
  28                 serial1 = &uart1;
  29                 serial2 = &uart2;
  30                 serial3 = &uart3;
  31                 spi0 = &spi0;
  32                 spi1 = &spi1;
  33         };
  34
  35         amba: bus {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges;
  40
  41                 dmac1_s: dma-controller@20018000 {
  42                         compatible = "arm,pl330", "arm,primecell";
  43                         reg = <0x20018000 0x4000>;
  44                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  45                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  46                         #dma-cells = <1>;
  47                         arm,pl330-broken-no-flushp;
  48                         arm,pl330-periph-burst;
  49                         clocks = <&cru ACLK_DMA1>;
  50                         clock-names = "apb_pclk";
  51                 };
  52
  53                 dmac1_ns: dma-controller@2001c000 {
  54                         compatible = "arm,pl330", "arm,primecell";
  55                         reg = <0x2001c000 0x4000>;
  56                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
  57                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
  58                         #dma-cells = <1>;
  59                         arm,pl330-broken-no-flushp;
  60                         arm,pl330-periph-burst;
  61                         clocks = <&cru ACLK_DMA1>;
  62                         clock-names = "apb_pclk";
  63                         status = "disabled";
  64                 };
  65
  66                 dmac2: dma-controller@20078000 {
  67                         compatible = "arm,pl330", "arm,primecell";
  68                         reg = <0x20078000 0x4000>;
  69                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
  70                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
  71                         #dma-cells = <1>;
  72                         arm,pl330-broken-no-flushp;
  73                         arm,pl330-periph-burst;
  74                         clocks = <&cru ACLK_DMA2>;
  75                         clock-names = "apb_pclk";
  76                 };
  77         };
  78
  79         xin24m: oscillator {
  80                 compatible = "fixed-clock";
  81                 clock-frequency = <24000000>;
  82                 #clock-cells = <0>;
  83                 clock-output-names = "xin24m";
  84         };
  85
  86         gpu: gpu@10090000 {
  87                 compatible = "arm,mali-400";
  88                 reg = <0x10090000 0x10000>;
  89                 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
  90                 clock-names = "bus", "core";
  91                 assigned-clocks = <&cru ACLK_GPU>;
  92                 assigned-clock-rates = <100000000>;
  93                 resets = <&cru SRST_GPU>;
  94                 status = "disabled";
  95         };
  96
  97         L2: cache-controller@10138000 {
  98                 compatible = "arm,pl310-cache";
  99                 reg = <0x10138000 0x1000>;
 100                 cache-unified;
 101                 cache-level = <2>;
 102         };
 103
 104         scu@1013c000 {
 105                 compatible = "arm,cortex-a9-scu";
 106                 reg = <0x1013c000 0x100>;
 107         };
 108
 109         global_timer: global-timer@1013c200 {
 110                 compatible = "arm,cortex-a9-global-timer";
 111                 reg = <0x1013c200 0x20>;
 112                 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 113                 clocks = <&cru CORE_PERI>;
 114         };
 115
 116         local_timer: local-timer@1013c600 {
 117                 compatible = "arm,cortex-a9-twd-timer";
 118                 reg = <0x1013c600 0x20>;
 119                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
 120                 clocks = <&cru CORE_PERI>;
 121         };
 122
 123         gic: interrupt-controller@1013d000 {
 124                 compatible = "arm,cortex-a9-gic";
 125                 interrupt-controller;
 126                 #interrupt-cells = <3>;
 127                 reg = <0x1013d000 0x1000>,
 128                       <0x1013c100 0x0100>;
 129         };
 130
 131         uart0: serial@10124000 {
 132                 compatible = "snps,dw-apb-uart";
 133                 reg = <0x10124000 0x400>;
 134                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 135                 reg-shift = <2>;
 136                 reg-io-width = <1>;
 137                 clock-names = "baudclk", "apb_pclk";
 138                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 139                 status = "disabled";
 140         };
 141
 142         uart1: serial@10126000 {
 143                 compatible = "snps,dw-apb-uart";
 144                 reg = <0x10126000 0x400>;
 145                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 146                 reg-shift = <2>;
 147                 reg-io-width = <1>;
 148                 clock-names = "baudclk", "apb_pclk";
 149                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 150                 status = "disabled";
 151         };
 152
 153         qos_gpu: qos@1012d000 {
 154                 compatible = "syscon";
 155                 reg = <0x1012d000 0x20>;
 156         };
 157
 158         qos_vpu: qos@1012e000 {
 159                 compatible = "syscon";
 160                 reg = <0x1012e000 0x20>;
 161         };
 162
 163         qos_lcdc0: qos@1012f000 {
 164                 compatible = "syscon";
 165                 reg = <0x1012f000 0x20>;
 166         };
 167
 168         qos_cif0: qos@1012f080 {
 169                 compatible = "syscon";
 170                 reg = <0x1012f080 0x20>;
 171         };
 172
 173         qos_ipp: qos@1012f100 {
 174                 compatible = "syscon";
 175                 reg = <0x1012f100 0x20>;
 176         };
 177
 178         qos_lcdc1: qos@1012f180 {
 179                 compatible = "syscon";
 180                 reg = <0x1012f180 0x20>;
 181         };
 182
 183         qos_cif1: qos@1012f200 {
 184                 compatible = "syscon";
 185                 reg = <0x1012f200 0x20>;
 186         };
 187
 188         qos_rga: qos@1012f280 {
 189                 compatible = "syscon";
 190                 reg = <0x1012f280 0x20>;
 191         };
 192
 193         usb_otg: usb@10180000 {
 194                 compatible = "rockchip,rk3066-usb", "snps,dwc2";
 195                 reg = <0x10180000 0x40000>;
 196                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 197                 clocks = <&cru HCLK_OTG0>;
 198                 clock-names = "otg";
 199                 dr_mode = "otg";
 200                 g-np-tx-fifo-size = <16>;
 201                 g-rx-fifo-size = <275>;
 202                 g-tx-fifo-size = <256 128 128 64 64 32>;
 203                 phys = <&usbphy0>;
 204                 phy-names = "usb2-phy";
 205                 status = "disabled";
 206         };
 207
 208         usb_host: usb@101c0000 {
 209                 compatible = "snps,dwc2";
 210                 reg = <0x101c0000 0x40000>;
 211                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 212                 clocks = <&cru HCLK_OTG1>;
 213                 clock-names = "otg";
 214                 dr_mode = "host";
 215                 phys = <&usbphy1>;
 216                 phy-names = "usb2-phy";
 217                 status = "disabled";
 218         };
 219
 220         emac: ethernet@10204000 {
 221                 compatible = "snps,arc-emac";
 222                 reg = <0x10204000 0x3c>;
 223                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226
 227                 rockchip,grf = <&grf>;
 228
 229                 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
 230                 clock-names = "hclk", "macref";
 231                 max-speed = <100>;
 232                 phy-mode = "rmii";
 233
 234                 status = "disabled";
 235         };
 236
 237         mmc0: mmc@10214000 {
 238                 compatible = "rockchip,rk2928-dw-mshc";
 239                 reg = <0x10214000 0x1000>;
 240                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 241                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
 242                 clock-names = "biu", "ciu";
 243                 dmas = <&dmac2 1>;
 244                 dma-names = "rx-tx";
 245                 fifo-depth = <256>;
 246                 resets = <&cru SRST_SDMMC>;
 247                 reset-names = "reset";
 248                 status = "disabled";
 249         };
 250
 251         mmc1: mmc@10218000 {
 252                 compatible = "rockchip,rk2928-dw-mshc";
 253                 reg = <0x10218000 0x1000>;
 254                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 255                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
 256                 clock-names = "biu", "ciu";
 257                 dmas = <&dmac2 3>;
 258                 dma-names = "rx-tx";
 259                 fifo-depth = <256>;
 260                 resets = <&cru SRST_SDIO>;
 261                 reset-names = "reset";
 262                 status = "disabled";
 263         };
 264
 265         emmc: mmc@1021c000 {
 266                 compatible = "rockchip,rk2928-dw-mshc";
 267                 reg = <0x1021c000 0x1000>;
 268                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 269                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
 270                 clock-names = "biu", "ciu";
 271                 dmas = <&dmac2 4>;
 272                 dma-names = "rx-tx";
 273                 fifo-depth = <256>;
 274                 resets = <&cru SRST_EMMC>;
 275                 reset-names = "reset";
 276                 status = "disabled";
 277         };
 278
 279         pmu: pmu@20004000 {
 280                 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
 281                 reg = <0x20004000 0x100>;
 282
 283                 reboot-mode {
 284                         compatible = "syscon-reboot-mode";
 285                         offset = <0x40>;
 286                         mode-normal = <BOOT_NORMAL>;
 287                         mode-recovery = <BOOT_RECOVERY>;
 288                         mode-bootloader = <BOOT_FASTBOOT>;
 289                         mode-loader = <BOOT_BL_DOWNLOAD>;
 290                 };
 291         };
 292
 293         grf: grf@20008000 {
 294                 compatible = "syscon";
 295                 reg = <0x20008000 0x200>;
 296         };
 297
 298         i2c0: i2c@2002d000 {
 299                 compatible = "rockchip,rk3066-i2c";
 300                 reg = <0x2002d000 0x1000>;
 301                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304
 305                 rockchip,grf = <&grf>;
 306
 307                 clock-names = "i2c";
 308                 clocks = <&cru PCLK_I2C0>;
 309
 310                 status = "disabled";
 311         };
 312
 313         i2c1: i2c@2002f000 {
 314                 compatible = "rockchip,rk3066-i2c";
 315                 reg = <0x2002f000 0x1000>;
 316                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 317                 #address-cells = <1>;
 318                 #size-cells = <0>;
 319
 320                 rockchip,grf = <&grf>;
 321
 322                 clocks = <&cru PCLK_I2C1>;
 323                 clock-names = "i2c";
 324
 325                 status = "disabled";
 326         };
 327
 328         pwm0: pwm@20030000 {
 329                 compatible = "rockchip,rk2928-pwm";
 330                 reg = <0x20030000 0x10>;
 331                 #pwm-cells = <2>;
 332                 clocks = <&cru PCLK_PWM01>;
 333                 status = "disabled";
 334         };
 335
 336         pwm1: pwm@20030010 {
 337                 compatible = "rockchip,rk2928-pwm";
 338                 reg = <0x20030010 0x10>;
 339                 #pwm-cells = <2>;
 340                 clocks = <&cru PCLK_PWM01>;
 341                 status = "disabled";
 342         };
 343
 344         wdt: watchdog@2004c000 {
 345                 compatible = "snps,dw-wdt";
 346                 reg = <0x2004c000 0x100>;
 347                 clocks = <&cru PCLK_WDT>;
 348                 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 349                 status = "disabled";
 350         };
 351
 352         pwm2: pwm@20050020 {
 353                 compatible = "rockchip,rk2928-pwm";
 354                 reg = <0x20050020 0x10>;
 355                 #pwm-cells = <2>;
 356                 clocks = <&cru PCLK_PWM23>;
 357                 status = "disabled";
 358         };
 359
 360         pwm3: pwm@20050030 {
 361                 compatible = "rockchip,rk2928-pwm";
 362                 reg = <0x20050030 0x10>;
 363                 #pwm-cells = <2>;
 364                 clocks = <&cru PCLK_PWM23>;
 365                 status = "disabled";
 366         };
 367
 368         i2c2: i2c@20056000 {
 369                 compatible = "rockchip,rk3066-i2c";
 370                 reg = <0x20056000 0x1000>;
 371                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374
 375                 rockchip,grf = <&grf>;
 376
 377                 clocks = <&cru PCLK_I2C2>;
 378                 clock-names = "i2c";
 379
 380                 status = "disabled";
 381         };
 382
 383         i2c3: i2c@2005a000 {
 384                 compatible = "rockchip,rk3066-i2c";
 385                 reg = <0x2005a000 0x1000>;
 386                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 387                 #address-cells = <1>;
 388                 #size-cells = <0>;
 389
 390                 rockchip,grf = <&grf>;
 391
 392                 clocks = <&cru PCLK_I2C3>;
 393                 clock-names = "i2c";
 394
 395                 status = "disabled";
 396         };
 397
 398         i2c4: i2c@2005e000 {
 399                 compatible = "rockchip,rk3066-i2c";
 400                 reg = <0x2005e000 0x1000>;
 401                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 402                 #address-cells = <1>;
 403                 #size-cells = <0>;
 404
 405                 rockchip,grf = <&grf>;
 406
 407                 clocks = <&cru PCLK_I2C4>;
 408                 clock-names = "i2c";
 409
 410                 status = "disabled";
 411         };
 412
 413         uart2: serial@20064000 {
 414                 compatible = "snps,dw-apb-uart";
 415                 reg = <0x20064000 0x400>;
 416                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 417                 reg-shift = <2>;
 418                 reg-io-width = <1>;
 419                 clock-names = "baudclk", "apb_pclk";
 420                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 421                 status = "disabled";
 422         };
 423
 424         uart3: serial@20068000 {
 425                 compatible = "snps,dw-apb-uart";
 426                 reg = <0x20068000 0x400>;
 427                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 428                 reg-shift = <2>;
 429                 reg-io-width = <1>;
 430                 clock-names = "baudclk", "apb_pclk";
 431                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 432                 status = "disabled";
 433         };
 434
 435         saradc: saradc@2006c000 {
 436                 compatible = "rockchip,saradc";
 437                 reg = <0x2006c000 0x100>;
 438                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 439                 #io-channel-cells = <1>;
 440                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 441                 clock-names = "saradc", "apb_pclk";
 442                 resets = <&cru SRST_SARADC>;
 443                 reset-names = "saradc-apb";
 444                 status = "disabled";
 445         };
 446
 447         spi0: spi@20070000 {
 448                 compatible = "rockchip,rk3066-spi";
 449                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 450                 clock-names = "spiclk", "apb_pclk";
 451                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 452                 reg = <0x20070000 0x1000>;
 453                 #address-cells = <1>;
 454                 #size-cells = <0>;
 455                 dmas = <&dmac2 10>, <&dmac2 11>;
 456                 dma-names = "tx", "rx";
 457                 status = "disabled";
 458         };
 459
 460         spi1: spi@20074000 {
 461                 compatible = "rockchip,rk3066-spi";
 462                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 463                 clock-names = "spiclk", "apb_pclk";
 464                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 465                 reg = <0x20074000 0x1000>;
 466                 #address-cells = <1>;
 467                 #size-cells = <0>;
 468                 dmas = <&dmac2 12>, <&dmac2 13>;
 469                 dma-names = "tx", "rx";
 470                 status = "disabled";
 471         };
 472 };