1 // SPDX-License-Identifier: GPL-2.0
3 * Samsung's S3C64xx SoC series common device tree source
5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
7 * Samsung's S3C64xx SoC series device nodes are listed in this file.
8 * Particular SoCs from S3C64xx series can include this file and provide
9 * values for SoCs specfic bindings.
11 * Note: This file does not include device nodes for all the controllers in
12 * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
13 * nodes can be added to this file.
16 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
37 compatible = "arm,arm1176jzf-s";
43 compatible = "simple-bus";
48 vic0: interrupt-controller@71200000 {
49 compatible = "arm,pl192-vic";
51 reg = <0x71200000 0x1000>;
52 #interrupt-cells = <1>;
55 vic1: interrupt-controller@71300000 {
56 compatible = "arm,pl192-vic";
58 reg = <0x71300000 0x1000>;
59 #interrupt-cells = <1>;
62 sdhci0: sdhci@7c200000 {
63 compatible = "samsung,s3c6410-sdhci";
64 reg = <0x7c200000 0x100>;
65 interrupt-parent = <&vic1>;
67 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
68 clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
73 sdhci1: sdhci@7c300000 {
74 compatible = "samsung,s3c6410-sdhci";
75 reg = <0x7c300000 0x100>;
76 interrupt-parent = <&vic1>;
78 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
79 clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
84 sdhci2: sdhci@7c400000 {
85 compatible = "samsung,s3c6410-sdhci";
86 reg = <0x7c400000 0x100>;
87 interrupt-parent = <&vic1>;
89 clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
90 clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
95 watchdog: watchdog@7e004000 {
96 compatible = "samsung,s3c6410-wdt";
97 reg = <0x7e004000 0x1000>;
98 interrupt-parent = <&vic0>;
100 clock-names = "watchdog";
101 clocks = <&clocks PCLK_WDT>;
105 compatible = "samsung,s3c2440-i2c";
106 reg = <0x7f004000 0x1000>;
107 interrupt-parent = <&vic1>;
110 clocks = <&clocks PCLK_IIC0>;
112 #address-cells = <1>;
116 uart0: serial@7f005000 {
117 compatible = "samsung,s3c6400-uart";
118 reg = <0x7f005000 0x100>;
119 interrupt-parent = <&vic1>;
121 clock-names = "uart", "clk_uart_baud2",
123 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
128 uart1: serial@7f005400 {
129 compatible = "samsung,s3c6400-uart";
130 reg = <0x7f005400 0x100>;
131 interrupt-parent = <&vic1>;
133 clock-names = "uart", "clk_uart_baud2",
135 clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
140 uart2: serial@7f005800 {
141 compatible = "samsung,s3c6400-uart";
142 reg = <0x7f005800 0x100>;
143 interrupt-parent = <&vic1>;
145 clock-names = "uart", "clk_uart_baud2",
147 clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
152 uart3: serial@7f005c00 {
153 compatible = "samsung,s3c6400-uart";
154 reg = <0x7f005c00 0x100>;
155 interrupt-parent = <&vic1>;
157 clock-names = "uart", "clk_uart_baud2",
159 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
165 compatible = "samsung,s3c6400-pwm";
166 reg = <0x7f006000 0x1000>;
167 interrupt-parent = <&vic0>;
168 interrupts = <23>, <24>, <25>, <27>, <28>;
169 clock-names = "timers";
170 clocks = <&clocks PCLK_PWM>;
171 samsung,pwm-outputs = <0>, <1>;
175 pinctrl0: pinctrl@7f008000 {
176 compatible = "samsung,s3c64xx-pinctrl";
177 reg = <0x7f008000 0x1000>;
178 interrupt-parent = <&vic1>;
181 pctrl_int_map: pinctrl-interrupt-map {
182 interrupt-map = <0 &vic0 0>,
186 #address-cells = <0>;
188 #interrupt-cells = <1>;
191 wakeup-interrupt-controller {
192 compatible = "samsung,s3c64xx-wakeup-eint";
193 interrupts = <0>, <1>, <2>, <3>;
194 interrupt-parent = <&pctrl_int_map>;
200 #include "s3c64xx-pinctrl.dtsi"