arch/arm/boot/dts/stih407.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 STMicroelectronics Limited.
   4  * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org>
   5  */
   6 #include "stih407-clock.dtsi"
   7 #include "stih407-family.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9 / {
  10         soc {
  11                 sti-display-subsystem@0 {
  12                         compatible = "st,sti-display-subsystem";
  13                         #address-cells = <1>;
  14                         #size-cells = <1>;
  15                         reg = <0 0>;
  16                         assigned-clocks = <&clk_s_d2_quadfs 0>,
  17                                           <&clk_s_d2_quadfs 1>,
  18                                           <&clk_s_c0_pll1 0>,
  19                                           <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  20                                           <&clk_s_c0_flexgen CLK_MAIN_DISP>,
  21                                           <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
  22                                           <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
  23                                           <&clk_s_d2_flexgen CLK_PIX_GDP1>,
  24                                           <&clk_s_d2_flexgen CLK_PIX_GDP2>,
  25                                           <&clk_s_d2_flexgen CLK_PIX_GDP3>,
  26                                           <&clk_s_d2_flexgen CLK_PIX_GDP4>;
  27
  28                         assigned-clock-parents = <0>,
  29                                                  <0>,
  30                                                  <0>,
  31                                                  <&clk_s_c0_pll1 0>,
  32                                                  <&clk_s_c0_pll1 0>,
  33                                                  <&clk_s_d2_quadfs 0>,
  34                                                  <&clk_s_d2_quadfs 1>,
  35                                                  <&clk_s_d2_quadfs 0>,
  36                                                  <&clk_s_d2_quadfs 0>,
  37                                                  <&clk_s_d2_quadfs 0>,
  38                                                  <&clk_s_d2_quadfs 0>;
  39
  40                         assigned-clock-rates = <297000000>,
  41                                                <108000000>,
  42                                                <0>,
  43                                                <400000000>,
  44                                                <400000000>;
  45
  46                         ranges;
  47
  48                         sti-compositor@9d11000 {
  49                                 compatible = "st,stih407-compositor";
  50                                 reg = <0x9d11000 0x1000>;
  51
  52                                 clock-names = "compo_main",
  53                                               "compo_aux",
  54                                               "pix_main",
  55                                               "pix_aux",
  56                                               "pix_gdp1",
  57                                               "pix_gdp2",
  58                                               "pix_gdp3",
  59                                               "pix_gdp4",
  60                                               "main_parent",
  61                                               "aux_parent";
  62
  63                                 clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  64                                          <&clk_s_c0_flexgen CLK_COMPO_DVP>,
  65                                          <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
  66                                          <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
  67                                          <&clk_s_d2_flexgen CLK_PIX_GDP1>,
  68                                          <&clk_s_d2_flexgen CLK_PIX_GDP2>,
  69                                          <&clk_s_d2_flexgen CLK_PIX_GDP3>,
  70                                          <&clk_s_d2_flexgen CLK_PIX_GDP4>,
  71                                          <&clk_s_d2_quadfs 0>,
  72                                          <&clk_s_d2_quadfs 1>;
  73
  74                                 reset-names = "compo-main", "compo-aux";
  75                                 resets = <&softreset STIH407_COMPO_SOFTRESET>,
  76                                          <&softreset STIH407_COMPO_SOFTRESET>;
  77                                 st,vtg = <&vtg_main>, <&vtg_aux>;
  78                         };
  79
  80                         sti-tvout@8d08000 {
  81                                 compatible = "st,stih407-tvout";
  82                                 reg = <0x8d08000 0x1000>;
  83                                 reg-names = "tvout-reg";
  84                                 reset-names = "tvout";
  85                                 resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
  86                                 #address-cells = <1>;
  87                                 #size-cells = <1>;
  88                                 assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
  89                                                   <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
  90                                                   <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
  91                                                   <&clk_s_d0_flexgen CLK_PCM_0>,
  92                                                   <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
  93                                                   <&clk_s_d2_flexgen CLK_HDDAC>;
  94
  95                                 assigned-clock-parents = <&clk_s_d2_quadfs 0>,
  96                                                          <&clk_tmdsout_hdmi>,
  97                                                          <&clk_s_d2_quadfs 0>,
  98                                                          <&clk_s_d0_quadfs 0>,
  99                                                          <&clk_s_d2_quadfs 0>,
 100                                                          <&clk_s_d2_quadfs 0>;
 101                         };
 102
 103                         sti_hdmi: sti-hdmi@8d04000 {
 104                                 compatible = "st,stih407-hdmi";
 105                                 reg = <0x8d04000 0x1000>;
 106                                 reg-names = "hdmi-reg";
 107                                 #sound-dai-cells = <0>;
 108                                 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 109                                 interrupt-names = "irq";
 110                                 clock-names = "pix",
 111                                               "tmds",
 112                                               "phy",
 113                                               "audio",
 114                                               "main_parent",
 115                                               "aux_parent";
 116
 117                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
 118                                          <&clk_s_d2_flexgen CLK_TMDS_HDMI>,
 119                                          <&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
 120                                          <&clk_s_d0_flexgen CLK_PCM_0>,
 121                                          <&clk_s_d2_quadfs 0>,
 122                                          <&clk_s_d2_quadfs 1>;
 123
 124                                 hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
 125                                 reset-names = "hdmi";
 126                                 resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
 127                                 ddc = <&hdmiddc>;
 128                         };
 129
 130                         sti-hda@8d02000 {
 131                                 compatible = "st,stih407-hda";
 132                                 reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
 133                                 reg-names = "hda-reg", "video-dacs-ctrl";
 134                                 clock-names = "pix",
 135                                               "hddac",
 136                                               "main_parent",
 137                                               "aux_parent";
 138                                 clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
 139                                          <&clk_s_d2_flexgen CLK_HDDAC>,
 140                                          <&clk_s_d2_quadfs 0>,
 141                                          <&clk_s_d2_quadfs 1>;
 142                         };
 143                 };
 144         };
 145 };