arch/arm/boot/dts/suniv-f1c100s.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
   2 /*
   3  * Copyright 2018 Icenowy Zheng <icenowy@aosc.io>
   4  * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
   5  */
   6
   7 / {
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10         interrupt-parent = <&intc>;
  11
  12         clocks {
  13                 osc24M: clk-24M {
  14                         #clock-cells = <0>;
  15                         compatible = "fixed-clock";
  16                         clock-frequency = <24000000>;
  17                         clock-output-names = "osc24M";
  18                 };
  19
  20                 osc32k: clk-32k {
  21                         #clock-cells = <0>;
  22                         compatible = "fixed-clock";
  23                         clock-frequency = <32768>;
  24                         clock-output-names = "osc32k";
  25                 };
  26         };
  27
  28         cpus {
  29                 cpu {
  30                         compatible = "arm,arm926ej-s";
  31                         device_type = "cpu";
  32                 };
  33         };
  34
  35         soc {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges;
  40
  41                 sram-controller@1c00000 {
  42                         compatible = "allwinner,suniv-f1c100s-system-control",
  43                                      "allwinner,sun4i-a10-system-control";
  44                         reg = <0x01c00000 0x30>;
  45                         #address-cells = <1>;
  46                         #size-cells = <1>;
  47                         ranges;
  48
  49                         sram_d: sram@10000 {
  50                                 compatible = "mmio-sram";
  51                                 reg = <0x00010000 0x1000>;
  52                                 #address-cells = <1>;
  53                                 #size-cells = <1>;
  54                                 ranges = <0 0x00010000 0x1000>;
  55
  56                                 otg_sram: sram-section@0 {
  57                                         compatible = "allwinner,suniv-f1c100s-sram-d",
  58                                                      "allwinner,sun4i-a10-sram-d";
  59                                         reg = <0x0000 0x1000>;
  60                                         status = "disabled";
  61                                 };
  62                         };
  63                 };
  64
  65                 ccu: clock@1c20000 {
  66                         compatible = "allwinner,suniv-f1c100s-ccu";
  67                         reg = <0x01c20000 0x400>;
  68                         clocks = <&osc24M>, <&osc32k>;
  69                         clock-names = "hosc", "losc";
  70                         #clock-cells = <1>;
  71                         #reset-cells = <1>;
  72                 };
  73
  74                 intc: interrupt-controller@1c20400 {
  75                         compatible = "allwinner,suniv-f1c100s-ic";
  76                         reg = <0x01c20400 0x400>;
  77                         interrupt-controller;
  78                         #interrupt-cells = <1>;
  79                 };
  80
  81                 pio: pinctrl@1c20800 {
  82                         compatible = "allwinner,suniv-f1c100s-pinctrl";
  83                         reg = <0x01c20800 0x400>;
  84                         interrupts = <38>, <39>, <40>;
  85                         clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
  86                         clock-names = "apb", "hosc", "losc";
  87                         gpio-controller;
  88                         interrupt-controller;
  89                         #interrupt-cells = <3>;
  90                         #gpio-cells = <3>;
  91
  92                         uart0_pe_pins: uart0-pe-pins {
  93                                 pins = "PE0", "PE1";
  94                                 function = "uart0";
  95                         };
  96                 };
  97
  98                 timer@1c20c00 {
  99                         compatible = "allwinner,suniv-f1c100s-timer";
 100                         reg = <0x01c20c00 0x90>;
 101                         interrupts = <13>;
 102                         clocks = <&osc24M>;
 103                 };
 104
 105                 wdt: watchdog@1c20ca0 {
 106                         compatible = "allwinner,suniv-f1c100s-wdt",
 107                                      "allwinner,sun4i-a10-wdt";
 108                         reg = <0x01c20ca0 0x20>;
 109                 };
 110
 111                 uart0: serial@1c25000 {
 112                         compatible = "snps,dw-apb-uart";
 113                         reg = <0x01c25000 0x400>;
 114                         interrupts = <1>;
 115                         reg-shift = <2>;
 116                         reg-io-width = <4>;
 117                         clocks = <&ccu 38>;
 118                         resets = <&ccu 24>;
 119                         status = "disabled";
 120                 };
 121
 122                 uart1: serial@1c25400 {
 123                         compatible = "snps,dw-apb-uart";
 124                         reg = <0x01c25400 0x400>;
 125                         interrupts = <2>;
 126                         reg-shift = <2>;
 127                         reg-io-width = <4>;
 128                         clocks = <&ccu 39>;
 129                         resets = <&ccu 25>;
 130                         status = "disabled";
 131                 };
 132
 133                 uart2: serial@1c25800 {
 134                         compatible = "snps,dw-apb-uart";
 135                         reg = <0x01c25800 0x400>;
 136                         interrupts = <3>;
 137                         reg-shift = <2>;
 138                         reg-io-width = <4>;
 139                         clocks = <&ccu 40>;
 140                         resets = <&ccu 26>;
 141                         status = "disabled";
 142                 };
 143         };
 144 };