| blob | d3b99535d755ef47167994d5efb48556e7d52add |
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
8 #include "tegra20.dtsi"
9 #include "tegra20-cpu-opp.dtsi"
10 #include "tegra20-cpu-opp-microvolt.dtsi"
12 / {
13 model = "Acer Iconia Tab A500";
14 compatible = "acer,picasso", "nvidia,tegra20";
16 aliases {
17 mmc0 = &sdmmc4; /* eMMC */
18 mmc1 = &sdmmc3; /* MicroSD */
19 mmc2 = &sdmmc1; /* WiFi */
21 rtc0 = &pmic;
22 rtc1 = "/rtc@7000e000";
24 serial0 = &uartd; /* Docking station */
25 serial1 = &uartc; /* Bluetooth */
26 serial2 = &uartb; /* GPS */
27 };
29 /*
30 * The decompressor and also some bootloaders rely on a
31 * pre-existing /chosen node to be available to insert the
32 * command line and merge other ATAGS info.
33 */
34 chosen {};
36 memory@0 {
37 reg = <0x00000000 0x40000000>;
38 };
40 reserved-memory {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
45 ramoops@2ffe0000 {
46 compatible = "ramoops";
47 reg = <0x2ffe0000 0x10000>; /* 64kB */
48 console-size = <0x8000>; /* 32kB */
49 record-size = <0x400>; /* 1kB */
50 ecc-size = <16>;
51 };
53 linux,cma@30000000 {
54 compatible = "shared-dma-pool";
55 alloc-ranges = <0x30000000 0x10000000>;
56 size = <0x10000000>; /* 256MiB */
57 linux,cma-default;
58 reusable;
59 };
60 };
62 host1x@50000000 {
63 dc@54200000 {
64 rgb {
65 status = "okay";
67 port@0 {
68 lcd_output: endpoint {
69 remote-endpoint = <&lvds_encoder_input>;
70 bus-width = <18>;
71 };
72 };
73 };
74 };
76 hdmi@54280000 {
77 status = "okay";
79 vdd-supply = <&hdmi_vdd_reg>;
80 pll-supply = <&hdmi_pll_reg>;
81 hdmi-supply = <&vdd_5v0_sys>;
83 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
84 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
85 GPIO_ACTIVE_HIGH>;
86 };
87 };
89 pinmux@70000014 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&state_default>;
93 state_default: pinmux {
94 ata {
95 nvidia,pins = "ata";
96 nvidia,function = "ide";
97 };
98 atb {
99 nvidia,pins = "atb", "gma", "gme";
100 nvidia,function = "sdio4";
101 };
102 atc {
103 nvidia,pins = "atc";
104 nvidia,function = "nand";
105 };
106 atd {
107 nvidia,pins = "atd", "ate", "gmb", "spia",
108 "spib", "spic";
109 nvidia,function = "gmi";
110 };
111 cdev1 {
112 nvidia,pins = "cdev1";
113 nvidia,function = "plla_out";
114 };
115 cdev2 {
116 nvidia,pins = "cdev2";
117 nvidia,function = "pllp_out4";
118 };
119 crtp {
120 nvidia,pins = "crtp", "lm1";
121 nvidia,function = "crt";
122 };
123 csus {
124 nvidia,pins = "csus";
125 nvidia,function = "vi_sensor_clk";
126 };
127 dap1 {
128 nvidia,pins = "dap1";
129 nvidia,function = "dap1";
130 };
131 dap2 {
132 nvidia,pins = "dap2";
133 nvidia,function = "dap2";
134 };
135 dap3 {
136 nvidia,pins = "dap3";
137 nvidia,function = "dap3";
138 };
139 dap4 {
140 nvidia,pins = "dap4";
141 nvidia,function = "dap4";
142 };
143 dta {
144 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
145 nvidia,function = "vi";
146 };
147 dtf {
148 nvidia,pins = "dtf";
149 nvidia,function = "i2c3";
150 };
151 gmc {
152 nvidia,pins = "gmc";
153 nvidia,function = "uartd";
154 };
155 gmd {
156 nvidia,pins = "gmd";
157 nvidia,function = "sflash";
158 };
159 gpu {
160 nvidia,pins = "gpu";
161 nvidia,function = "pwm";
162 };
163 gpu7 {
164 nvidia,pins = "gpu7";
165 nvidia,function = "rtck";
166 };
167 gpv {
168 nvidia,pins = "gpv", "slxa";
169 nvidia,function = "pcie";
170 };
171 hdint {
172 nvidia,pins = "hdint";
173 nvidia,function = "hdmi";
174 };
175 i2cp {
176 nvidia,pins = "i2cp";
177 nvidia,function = "i2cp";
178 };
179 irrx {
180 nvidia,pins = "irrx", "irtx";
181 nvidia,function = "uartb";
182 };
183 kbca {
184 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
185 "kbce", "kbcf";
186 nvidia,function = "kbc";
187 };
188 lcsn {
189 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
190 "lsdi", "lvp0";
191 nvidia,function = "rsvd4";
192 };
193 ld0 {
194 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
195 "ld5", "ld6", "ld7", "ld8", "ld9",
196 "ld10", "ld11", "ld12", "ld13", "ld14",
197 "ld15", "ld16", "ld17", "ldi", "lhp0",
198 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
199 "lsc1", "lsck", "lsda", "lspi", "lvp1",
200 "lvs";
201 nvidia,function = "displaya";
202 };
203 owc {
204 nvidia,pins = "owc", "spdi", "spdo", "uac";
205 nvidia,function = "rsvd2";
206 };
207 pmc {
208 nvidia,pins = "pmc";
209 nvidia,function = "pwr_on";
210 };
211 rm {
212 nvidia,pins = "rm";
213 nvidia,function = "i2c1";
214 };
215 sdb {
216 nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
217 nvidia,function = "sdio3";
218 };
219 sdio1 {
220 nvidia,pins = "sdio1";
221 nvidia,function = "sdio1";
222 };
223 slxd {
224 nvidia,pins = "slxd";
225 nvidia,function = "spdif";
226 };
227 spid {
228 nvidia,pins = "spid", "spie", "spif";
229 nvidia,function = "spi1";
230 };
231 spig {
232 nvidia,pins = "spig", "spih";
233 nvidia,function = "spi2_alt";
234 };
235 uaa {
236 nvidia,pins = "uaa", "uab", "uda";
237 nvidia,function = "ulpi";
238 };
239 uad {
240 nvidia,pins = "uad";
241 nvidia,function = "irda";
242 };
243 uca {
244 nvidia,pins = "uca", "ucb";
245 nvidia,function = "uartc";
246 };
247 conf_ata {
248 nvidia,pins = "ata", "atb", "atc", "atd",
249 "cdev1", "cdev2", "csus", "dap1",
250 "dap4", "dte", "dtf", "gma", "gmc",
251 "gme", "gpu", "gpu7", "gpv", "i2cp",
252 "irrx", "irtx", "pta", "rm",
253 "sdc", "sdd", "slxc", "slxd", "slxk",
254 "spdi", "spdo", "uac", "uad", "uda";
255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
257 };
258 conf_ate {
259 nvidia,pins = "ate", "dap2", "dap3",
260 "gmd", "owc", "spia", "spib", "spic",
261 "spid", "spie";
262 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263 nvidia,tristate = <TEGRA_PIN_ENABLE>;
264 };
265 conf_ck32 {
266 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
267 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 };
270 conf_crtp {
271 nvidia,pins = "crtp", "gmb", "slxa", "spig",
272 "spih";
273 nvidia,pull = <TEGRA_PIN_PULL_UP>;
274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
275 };
276 conf_dta {
277 nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
278 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
280 };
281 conf_dte {
282 nvidia,pins = "spif";
283 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
284 nvidia,tristate = <TEGRA_PIN_ENABLE>;
285 };
286 conf_hdint {
287 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
288 "lpw1", "lsck", "lsda", "lsdi",
289 "lvp0";
290 nvidia,tristate = <TEGRA_PIN_ENABLE>;
291 };
292 conf_kbca {
293 nvidia,pins = "kbca", "kbcc", "kbcd",
294 "kbce", "kbcf", "sdio1", "uaa",
295 "uab", "uca", "ucb";
296 nvidia,pull = <TEGRA_PIN_PULL_UP>;
297 nvidia,tristate = <TEGRA_PIN_DISABLE>;
298 };
299 conf_lc {
300 nvidia,pins = "lc", "ls";
301 nvidia,pull = <TEGRA_PIN_PULL_UP>;
302 };
303 conf_ld0 {
304 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
305 "ld5", "ld6", "ld7", "ld8", "ld9",
306 "ld10", "ld11", "ld12", "ld13", "ld14",
307 "ld15", "ld16", "ld17", "ldi", "lhp0",
308 "lhp1", "lhp2", "lhs", "lm0", "lpp",
309 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
310 "lvp1", "lvs", "pmc", "sdb";
311 nvidia,tristate = <TEGRA_PIN_DISABLE>;
312 };
313 conf_ld17_0 {
314 nvidia,pins = "ld17_0";
315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316 };
317 drive_ddc {
318 nvidia,pins = "drive_ddc",
319 "drive_vi1",
320 "drive_sdio1";
321 nvidia,pull-up-strength = <31>;
322 nvidia,pull-down-strength = <31>;
323 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
324 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
325 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
326 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
327 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
328 };
329 drive_dbg {
330 nvidia,pins = "drive_dbg",
331 "drive_vi2",
332 "drive_at1",
333 "drive_ao1";
334 nvidia,pull-up-strength = <31>;
335 nvidia,pull-down-strength = <31>;
336 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
337 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
338 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
339 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
340 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341 };
342 };
344 state_i2cmux_ddc: pinmux_i2cmux_ddc {
345 ddc {
346 nvidia,pins = "ddc";
347 nvidia,function = "i2c2";
348 };
349 pta {
350 nvidia,pins = "pta";
351 nvidia,function = "rsvd4";
352 };
353 };
355 state_i2cmux_pta: pinmux_i2cmux_pta {
356 ddc {
357 nvidia,pins = "ddc";
358 nvidia,function = "rsvd4";
359 };
360 pta {
361 nvidia,pins = "pta";
362 nvidia,function = "i2c2";
363 };
364 };
366 state_i2cmux_idle: pinmux_i2cmux_idle {
367 ddc {
368 nvidia,pins = "ddc";
369 nvidia,function = "rsvd4";
370 };
371 pta {
372 nvidia,pins = "pta";
373 nvidia,function = "rsvd4";
374 };
375 };
376 };
378 tegra_i2s1: i2s@70002800 {
379 status = "okay";
380 };
382 uartb: serial@70006040 {
383 compatible = "nvidia,tegra20-hsuart";
384 /* GPS BCM4751 */
385 };
387 uartc: serial@70006200 {
388 compatible = "nvidia,tegra20-hsuart";
389 status = "okay";
391 /* Azurewave AW-NH665 BCM4329B1 */
392 bluetooth {
393 compatible = "brcm,bcm4329-bt";
395 /* PLLP 216MHz / 16 / 4 */
396 max-speed = <3375000>;
398 clocks = <&rtc_32k_wifi>;
399 clock-names = "txco";
401 vbat-supply = <&vdd_3v3_sys>;
402 vddio-supply = <&vdd_1v8_sys>;
404 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
405 host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
406 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
407 };
408 };
410 uartd: serial@70006300 {
411 /* Docking station */
412 };
414 i2c@7000c000 {
415 clock-frequency = <400000>;
416 status = "okay";
418 wm8903: audio-codec@1a {
419 compatible = "wlf,wm8903";
420 reg = <0x1a>;
422 interrupt-parent = <&gpio>;
423 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
425 gpio-controller;
426 #gpio-cells = <2>;
428 gpio-cfg = <
429 0x0000 /* MIC_LR_OUT# GPIO, output, low */
430 0x0000 /* FM2018-enable GPIO, output, low */
431 0x0000 /* Speaker-enable GPIO, output, low */
432 0x0200 /* Interrupt, output */
433 0x01a0 /* BCLK, input, active high */
434 >;
436 AVDD-supply = <&vdd_1v8_sys>;
437 CPVDD-supply = <&vdd_1v8_sys>;
438 DBVDD-supply = <&vdd_1v8_sys>;
439 DCVDD-supply = <&vdd_1v8_sys>;
440 };
442 touchscreen@4c {
443 compatible = "atmel,maxtouch";
444 reg = <0x4c>;
446 interrupt-parent = <&gpio>;
447 interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
449 reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
451 avdd-supply = <&vdd_3v3_sys>;
452 vdd-supply = <&vdd_3v3_sys>;
453 };
455 gyroscope@68 {
456 compatible = "invensense,mpu3050";
457 reg = <0x68>;
459 interrupt-parent = <&gpio>;
460 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
462 vdd-supply = <&vdd_3v3_sys>;
463 vlogic-supply = <&vdd_1v8_sys>;
465 mount-matrix = "0", "1", "0",
466 "1", "0", "0",
467 "0", "0", "-1";
469 i2c-gate {
470 #address-cells = <1>;
471 #size-cells = <0>;
473 accelerometer@f {
474 compatible = "kionix,kxtf9";
475 reg = <0x0f>;
477 interrupt-parent = <&gpio>;
478 interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
480 mount-matrix = "0", "1", "0",
481 "1", "0", "0",
482 "0", "0", "-1";
483 };
484 };
485 };
486 };
488 i2c@7000c400 {
489 clock-frequency = <10000>;
490 status = "okay";
491 };
493 i2cmux {
494 compatible = "i2c-mux-pinctrl";
495 #address-cells = <1>;
496 #size-cells = <0>;
498 i2c-parent = <&{/i2c@7000c400}>;
500 pinctrl-names = "ddc", "pta", "idle";
501 pinctrl-0 = <&state_i2cmux_ddc>;
502 pinctrl-1 = <&state_i2cmux_pta>;
503 pinctrl-2 = <&state_i2cmux_idle>;
505 hdmi_ddc: i2c@0 {
506 reg = <0>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 };
511 panel_ddc: i2c@1 {
512 reg = <1>;
513 #address-cells = <1>;
514 #size-cells = <0>;
516 embedded-controller@58 {
517 compatible = "acer,a500-iconia-ec", "ene,kb930";
518 reg = <0x58>;
520 system-power-controller;
522 monitored-battery = <&bat1010>;
523 power-supplies = <&mains>;
524 };
525 };
526 };
528 pwm: pwm@7000a000 {
529 status = "okay";
530 };
532 i2c@7000d000 {
533 clock-frequency = <100000>;
534 status = "okay";
536 magnetometer@c {
537 compatible = "ak,ak8975";
538 reg = <0x0c>;
540 interrupt-parent = <&gpio>;
541 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
543 vdd-supply = <&vdd_3v3_sys>;
544 vid-supply = <&vdd_1v8_sys>;
546 mount-matrix = "1", "0", "0",
547 "0", "-1", "0",
548 "0", "0", "-1";
549 };
551 pmic: pmic@34 {
552 compatible = "ti,tps6586x";
553 reg = <0x34>;
555 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
557 #gpio-cells = <2>;
558 gpio-controller;
560 sys-supply = <&vdd_5v0_sys>;
561 vin-sm0-supply = <&sys_reg>;
562 vin-sm1-supply = <&sys_reg>;
563 vin-sm2-supply = <&sys_reg>;
564 vinldo01-supply = <&sm2_reg>;
565 vinldo23-supply = <&sm2_reg>;
566 vinldo4-supply = <&sm2_reg>;
567 vinldo678-supply = <&sm2_reg>;
568 vinldo9-supply = <&sm2_reg>;
570 regulators {
571 sys_reg: sys {
572 regulator-name = "vdd_sys";
573 regulator-always-on;
574 };
576 vdd_core: sm0 {
577 regulator-name = "vdd_sm0,vdd_core";
578 regulator-min-microvolt = <1200000>;
579 regulator-max-microvolt = <1300000>;
580 regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
581 regulator-coupled-max-spread = <170000 550000>;
582 regulator-always-on;
583 regulator-boot-on;
585 nvidia,tegra-core-regulator;
586 };
588 vdd_cpu: sm1 {
589 regulator-name = "vdd_sm1,vdd_cpu";
590 regulator-min-microvolt = <750000>;
591 regulator-max-microvolt = <1125000>;
592 regulator-coupled-with = <&vdd_core &rtc_vdd>;
593 regulator-coupled-max-spread = <550000 550000>;
594 regulator-always-on;
595 regulator-boot-on;
597 nvidia,tegra-cpu-regulator;
598 };
600 sm2_reg: sm2 {
601 regulator-name = "vdd_sm2,vin_ldo*";
602 regulator-min-microvolt = <3700000>;
603 regulator-max-microvolt = <3700000>;
604 regulator-always-on;
605 };
607 /* LDO0 is not connected to anything */
609 ldo1 {
610 regulator-name = "vdd_ldo1,avdd_pll*";
611 regulator-min-microvolt = <1100000>;
612 regulator-max-microvolt = <1100000>;
613 regulator-always-on;
614 regulator-boot-on;
615 };
617 rtc_vdd: ldo2 {
618 regulator-name = "vdd_ldo2,vdd_rtc";
619 regulator-min-microvolt = <1200000>;
620 regulator-max-microvolt = <1300000>;
621 regulator-coupled-with = <&vdd_core &vdd_cpu>;
622 regulator-coupled-max-spread = <170000 550000>;
623 regulator-always-on;
624 regulator-boot-on;
626 nvidia,tegra-rtc-regulator;
627 };
629 ldo3 {
630 regulator-name = "vdd_ldo3,avdd_usb*";
631 regulator-min-microvolt = <3300000>;
632 regulator-max-microvolt = <3300000>;
633 regulator-always-on;
634 };
636 ldo4 {
637 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
638 regulator-min-microvolt = <1800000>;
639 regulator-max-microvolt = <1800000>;
640 regulator-always-on;
641 regulator-boot-on;
642 };
644 vcore_emmc: ldo5 {
645 regulator-name = "vdd_ldo5,vcore_mmc";
646 regulator-min-microvolt = <2850000>;
647 regulator-max-microvolt = <2850000>;
648 regulator-always-on;
649 };
651 avdd_vdac_reg: ldo6 {
652 regulator-name = "vdd_ldo6,avdd_vdac";
653 regulator-min-microvolt = <2850000>;
654 regulator-max-microvolt = <2850000>;
655 };
657 hdmi_vdd_reg: ldo7 {
658 regulator-name = "vdd_ldo7,avdd_hdmi";
659 regulator-min-microvolt = <3300000>;
660 regulator-max-microvolt = <3300000>;
661 };
663 hdmi_pll_reg: ldo8 {
664 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
665 regulator-min-microvolt = <1800000>;
666 regulator-max-microvolt = <1800000>;
667 };
669 ldo9 {
670 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
671 regulator-min-microvolt = <2850000>;
672 regulator-max-microvolt = <2850000>;
673 regulator-always-on;
674 regulator-boot-on;
675 };
677 ldo_rtc {
678 regulator-name = "vdd_rtc_out,vdd_cell";
679 regulator-min-microvolt = <3300000>;
680 regulator-max-microvolt = <3300000>;
681 regulator-always-on;
682 regulator-boot-on;
683 };
684 };
685 };
687 nct1008: temperature-sensor@4c {
688 compatible = "onnn,nct1008";
689 reg = <0x4c>;
690 vcc-supply = <&vdd_3v3_sys>;
691 #thermal-sensor-cells = <1>;
692 };
693 };
695 pmc@7000e400 {
696 nvidia,invert-interrupt;
697 nvidia,suspend-mode = <1>;
698 nvidia,cpu-pwr-good-time = <2000>;
699 nvidia,cpu-pwr-off-time = <100>;
700 nvidia,core-pwr-good-time = <3845 3845>;
701 nvidia,core-pwr-off-time = <458>;
702 nvidia,sys-clock-req-active-high;
703 };
705 usb@c5000000 {
706 compatible = "nvidia,tegra20-udc";
707 status = "okay";
708 dr_mode = "peripheral";
709 };
711 usb-phy@c5000000 {
712 status = "okay";
713 dr_mode = "peripheral";
714 nvidia,xcvr-setup-use-fuses;
715 nvidia,xcvr-lsfslew = <2>;
716 nvidia,xcvr-lsrslew = <2>;
717 vbus-supply = <&vdd_vbus1>;
718 };
720 usb@c5008000 {
721 status = "okay";
722 };
724 usb-phy@c5008000 {
725 status = "okay";
726 nvidia,xcvr-setup-use-fuses;
727 nvidia,xcvr-lsfslew = <2>;
728 nvidia,xcvr-lsrslew = <2>;
729 vbus-supply = <&vdd_vbus3>;
730 };
732 brcm_wifi_pwrseq: wifi-pwrseq {
733 compatible = "mmc-pwrseq-simple";
735 clocks = <&rtc_32k_wifi>;
736 clock-names = "ext_clock";
738 reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
739 post-power-on-delay-ms = <300>;
740 power-off-delay-us = <300>;
741 };
743 sdmmc1: mmc@c8000000 {
744 status = "okay";
746 #address-cells = <1>;
747 #size-cells = <0>;
749 assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
750 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
751 assigned-clock-rates = <50000000>;
753 max-frequency = <50000000>;
754 keep-power-in-suspend;
755 bus-width = <4>;
756 non-removable;
758 mmc-pwrseq = <&brcm_wifi_pwrseq>;
759 vmmc-supply = <&vdd_3v3_sys>;
760 vqmmc-supply = <&vdd_3v3_sys>;
762 /* Azurewave AW-NH611 BCM4329 */
763 wifi@1 {
764 reg = <1>;
765 compatible = "brcm,bcm4329-fmac";
766 interrupt-parent = <&gpio>;
767 interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
768 interrupt-names = "host-wake";
769 };
770 };
772 sdmmc3: mmc@c8000400 {
773 status = "okay";
774 bus-width = <4>;
775 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
776 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
777 vmmc-supply = <&vdd_3v3_sys>;
778 vqmmc-supply = <&vdd_3v3_sys>;
779 };
781 sdmmc4: mmc@c8000600 {
782 status = "okay";
783 bus-width = <8>;
784 vmmc-supply = <&vcore_emmc>;
785 vqmmc-supply = <&vdd_3v3_sys>;
786 non-removable;
787 };
789 mains: ac-adapter-detect {
790 compatible = "gpio-charger";
791 charger-type = "mains";
792 gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
793 };
795 backlight: backlight {
796 compatible = "pwm-backlight";
798 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
799 power-supply = <&vdd_3v3_sys>;
800 pwms = <&pwm 2 41667>;
802 brightness-levels = <7 255>;
803 num-interpolated-steps = <248>;
804 default-brightness-level = <20>;
805 };
807 bat1010: battery-2s1p {
808 compatible = "simple-battery";
809 charge-full-design-microamp-hours = <3260000>;
810 energy-full-design-microwatt-hours = <24000000>;
811 operating-range-celsius = <0 40>;
812 };
814 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
815 clk32k_in: clock@0 {
816 compatible = "fixed-clock";
817 #clock-cells = <0>;
818 clock-frequency = <32768>;
819 clock-output-names = "tps658621-out32k";
820 };
822 /*
823 * This standalone onboard fixed-clock always-ON 32KHz
824 * oscillator is used as a reference clock-source by the
825 * Azurewave WiFi/BT module.
826 */
827 rtc_32k_wifi: clock@1 {
828 compatible = "fixed-clock";
829 #clock-cells = <0>;
830 clock-frequency = <32768>;
831 clock-output-names = "kk3270032";
832 };
834 cpus {
835 cpu0: cpu@0 {
836 cpu-supply = <&vdd_cpu>;
837 operating-points-v2 = <&cpu0_opp_table>;
838 #cooling-cells = <2>;
839 };
841 cpu@1 {
842 cpu-supply = <&vdd_cpu>;
843 operating-points-v2 = <&cpu0_opp_table>;
844 };
845 };
847 display-panel {
848 compatible = "auo,b101ew05", "panel-lvds";
850 ddc-i2c-bus = <&panel_ddc>;
851 power-supply = <&vdd_pnl>;
852 backlight = <&backlight>;
854 width-mm = <218>;
855 height-mm = <135>;
857 data-mapping = "jeida-18";
859 panel-timing {
860 clock-frequency = <71200000>;
861 hactive = <1280>;
862 vactive = <800>;
863 hfront-porch = <8>;
864 hback-porch = <18>;
865 hsync-len = <184>;
866 vsync-len = <3>;
867 vfront-porch = <4>;
868 vback-porch = <8>;
869 };
871 port {
872 panel_input: endpoint {
873 remote-endpoint = <&lvds_encoder_output>;
874 };
875 };
876 };
878 gpio-keys {
879 compatible = "gpio-keys";
881 power {
882 label = "Power";
883 gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
884 linux,code = <KEY_POWER>;
885 debounce-interval = <10>;
886 wakeup-event-action = <EV_ACT_ASSERTED>;
887 wakeup-source;
888 };
890 rotation-lock {
891 label = "Rotate-lock";
892 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
893 linux,code = <SW_ROTATE_LOCK>;
894 linux,input-type = <EV_SW>;
895 debounce-interval = <10>;
896 };
898 volume-up {
899 label = "Volume Up";
900 gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
901 linux,code = <KEY_VOLUMEUP>;
902 debounce-interval = <10>;
903 wakeup-event-action = <EV_ACT_ASSERTED>;
904 wakeup-source;
905 };
907 volume-down {
908 label = "Volume Down";
909 gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
910 linux,code = <KEY_VOLUMEDOWN>;
911 debounce-interval = <10>;
912 wakeup-event-action = <EV_ACT_ASSERTED>;
913 wakeup-source;
914 };
915 };
917 haptic-feedback {
918 compatible = "gpio-vibrator";
919 enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
920 vcc-supply = <&vdd_3v3_sys>;
921 };
923 lvds-encoder {
924 compatible = "ti,sn75lvds83", "lvds-encoder";
926 powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
927 power-supply = <&vdd_3v3_sys>;
929 ports {
930 #address-cells = <1>;
931 #size-cells = <0>;
933 port@0 {
934 reg = <0>;
936 lvds_encoder_input: endpoint {
937 remote-endpoint = <&lcd_output>;
938 };
939 };
941 port@1 {
942 reg = <1>;
944 lvds_encoder_output: endpoint {
945 remote-endpoint = <&panel_input>;
946 };
947 };
948 };
949 };
951 vdd_5v0_sys: regulator@0 {
952 compatible = "regulator-fixed";
953 regulator-name = "vdd_5v0";
954 regulator-min-microvolt = <5000000>;
955 regulator-max-microvolt = <5000000>;
956 regulator-always-on;
957 };
959 vdd_3v3_sys: regulator@1 {
960 compatible = "regulator-fixed";
961 regulator-name = "vdd_3v3_vs";
962 regulator-min-microvolt = <3300000>;
963 regulator-max-microvolt = <3300000>;
964 regulator-always-on;
965 vin-supply = <&vdd_5v0_sys>;
966 };
968 vdd_1v8_sys: regulator@2 {
969 compatible = "regulator-fixed";
970 regulator-name = "vdd_1v8_vs";
971 regulator-min-microvolt = <1800000>;
972 regulator-max-microvolt = <1800000>;
973 regulator-always-on;
974 vin-supply = <&vdd_5v0_sys>;
975 };
977 vdd_pnl: regulator@3 {
978 compatible = "regulator-fixed";
979 regulator-name = "vdd_panel";
980 regulator-min-microvolt = <3300000>;
981 regulator-max-microvolt = <3300000>;
982 regulator-enable-ramp-delay = <300000>;
983 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
984 enable-active-high;
985 vin-supply = <&vdd_5v0_sys>;
986 };
988 vdd_vbus1: regulator@4 {
989 compatible = "regulator-fixed";
990 regulator-name = "vdd_usb1_vbus";
991 regulator-min-microvolt = <5000000>;
992 regulator-max-microvolt = <5000000>;
993 regulator-always-on;
994 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
995 enable-active-high;
996 vin-supply = <&vdd_5v0_sys>;
997 };
999 vdd_vbus3: regulator@5 {
1000 compatible = "regulator-fixed";
1001 regulator-name = "vdd_usb3_vbus";
1002 regulator-min-microvolt = <5000000>;
1003 regulator-max-microvolt = <5000000>;
1004 regulator-always-on;
1005 gpio = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
1006 enable-active-high;
1007 vin-supply = <&vdd_5v0_sys>;
1008 };
1010 sound {
1011 compatible = "nvidia,tegra-audio-wm8903-picasso",
1012 "nvidia,tegra-audio-wm8903";
1013 nvidia,model = "Acer Iconia Tab A500 WM8903";
1015 nvidia,audio-routing =
1016 "Headphone Jack", "HPOUTR",
1017 "Headphone Jack", "HPOUTL",
1018 "Int Spk", "LINEOUTL",
1019 "Int Spk", "LINEOUTR",
1020 "Mic Jack", "MICBIAS",
1021 "IN2L", "Mic Jack",
1022 "IN2R", "Mic Jack",
1023 "IN1L", "Int Mic",
1024 "IN1R", "Int Mic";
1026 nvidia,i2s-controller = <&tegra_i2s1>;
1027 nvidia,audio-codec = <&wm8903>;
1029 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
1030 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
1031 nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
1032 nvidia,headset;
1034 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
1035 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
1036 <&tegra_car TEGRA20_CLK_CDEV1>;
1037 clock-names = "pll_a", "pll_a_out0", "mclk";
1038 };
1040 thermal-zones {
1041 skin-thermal {
1042 polling-delay-passive = <1000>; /* milliseconds */
1043 polling-delay = <0>; /* milliseconds */
1045 thermal-sensors = <&nct1008 0>;
1046 };
1048 cpu-thermal {
1049 polling-delay-passive = <1000>; /* milliseconds */
1050 polling-delay = <5000>; /* milliseconds */
1052 thermal-sensors = <&nct1008 1>;
1054 trips {
1055 trip0: cpu-alert0 {
1056 /* start throttling at 50C */
1057 temperature = <50000>;
1058 hysteresis = <3000>;
1059 type = "passive";
1060 };
1062 trip1: cpu-crit {
1063 /* shut down at 60C */
1064 temperature = <60000>;
1065 hysteresis = <2000>;
1066 type = "critical";
1067 };
1068 };
1070 cooling-maps {
1071 map0 {
1072 trip = <&trip0>;
1073 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1074 };
1075 };
1076 };
1077 };
1079 memory-controller@7000f400 {
1080 nvidia,use-ram-code;
1082 emc-tables@0 {
1083 nvidia,ram-code = <0>; /* elpida-8gb */
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1088 emc-table@25000 {
1089 reg = <25000>;
1090 compatible = "nvidia,tegra20-emc-table";
1091 clock-frequency = <25000>;
1092 nvidia,emc-registers = <0x00000002 0x00000006
1093 0x00000003 0x00000003 0x00000006 0x00000004
1094 0x00000002 0x00000009 0x00000003 0x00000003
1095 0x00000002 0x00000002 0x00000002 0x00000004
1096 0x00000003 0x00000008 0x0000000b 0x0000004d
1097 0x00000000 0x00000003 0x00000003 0x00000003
1098 0x00000008 0x00000001 0x0000000a 0x00000004
1099 0x00000003 0x00000008 0x00000004 0x00000006
1100 0x00000002 0x00000068 0x00000000 0x00000003
1101 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1102 0x00070000 0x00000000 0x00000000 0x00000003
1103 0x00000000 0x00000000 0x00000000 0x00000000>;
1104 };
1106 emc-table@50000 {
1107 reg = <50000>;
1108 compatible = "nvidia,tegra20-emc-table";
1109 clock-frequency = <50000>;
1110 nvidia,emc-registers = <0x00000003 0x00000007
1111 0x00000003 0x00000003 0x00000006 0x00000004
1112 0x00000002 0x00000009 0x00000003 0x00000003
1113 0x00000002 0x00000002 0x00000002 0x00000005
1114 0x00000003 0x00000008 0x0000000b 0x0000009f
1115 0x00000000 0x00000003 0x00000003 0x00000003
1116 0x00000008 0x00000001 0x0000000a 0x00000007
1117 0x00000003 0x00000008 0x00000004 0x00000006
1118 0x00000002 0x000000d0 0x00000000 0x00000000
1119 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1120 0x00070000 0x00000000 0x00000000 0x00000005
1121 0x00000000 0x00000000 0x00000000 0x00000000>;
1122 };
1124 emc-table@75000 {
1125 reg = <75000>;
1126 compatible = "nvidia,tegra20-emc-table";
1127 clock-frequency = <75000>;
1128 nvidia,emc-registers = <0x00000005 0x0000000a
1129 0x00000004 0x00000003 0x00000006 0x00000004
1130 0x00000002 0x00000009 0x00000003 0x00000003
1131 0x00000002 0x00000002 0x00000002 0x00000005
1132 0x00000003 0x00000008 0x0000000b 0x000000ff
1133 0x00000000 0x00000003 0x00000003 0x00000003
1134 0x00000008 0x00000001 0x0000000a 0x0000000b
1135 0x00000003 0x00000008 0x00000004 0x00000006
1136 0x00000002 0x00000138 0x00000000 0x00000000
1137 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1138 0x00070000 0x00000000 0x00000000 0x00000007
1139 0x00000000 0x00000000 0x00000000 0x00000000>;
1140 };
1142 emc-table@150000 {
1143 reg = <150000>;
1144 compatible = "nvidia,tegra20-emc-table";
1145 clock-frequency = <150000>;
1146 nvidia,emc-registers = <0x00000009 0x00000014
1147 0x00000007 0x00000003 0x00000006 0x00000004
1148 0x00000002 0x00000009 0x00000003 0x00000003
1149 0x00000002 0x00000002 0x00000002 0x00000005
1150 0x00000003 0x00000008 0x0000000b 0x0000021f
1151 0x00000000 0x00000003 0x00000003 0x00000003
1152 0x00000008 0x00000001 0x0000000a 0x00000015
1153 0x00000003 0x00000008 0x00000004 0x00000006
1154 0x00000002 0x00000270 0x00000000 0x00000001
1155 0x00000000 0x00000000 0x00000282 0xa07c04ae
1156 0x007dd510 0x00000000 0x00000000 0x0000000e
1157 0x00000000 0x00000000 0x00000000 0x00000000>;
1158 };
1160 emc-table@300000 {
1161 reg = <300000>;
1162 compatible = "nvidia,tegra20-emc-table";
1163 clock-frequency = <300000>;
1164 nvidia,emc-registers = <0x00000012 0x00000027
1165 0x0000000d 0x00000006 0x00000007 0x00000005
1166 0x00000003 0x00000009 0x00000006 0x00000006
1167 0x00000003 0x00000003 0x00000002 0x00000006
1168 0x00000003 0x00000009 0x0000000c 0x0000045f
1169 0x00000000 0x00000004 0x00000004 0x00000006
1170 0x00000008 0x00000001 0x0000000e 0x0000002a
1171 0x00000003 0x0000000f 0x00000007 0x00000005
1172 0x00000002 0x000004e1 0x00000005 0x00000002
1173 0x00000000 0x00000000 0x00000282 0xe059048b
1174 0x007e1510 0x00000000 0x00000000 0x0000001b
1175 0x00000000 0x00000000 0x00000000 0x00000000>;
1176 };
1177 };
1179 emc-tables@1 {
1180 nvidia,ram-code = <1>; /* elpida-4gb */
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1185 emc-table@25000 {
1186 reg = <25000>;
1187 compatible = "nvidia,tegra20-emc-table";
1188 clock-frequency = <25000>;
1189 nvidia,emc-registers = <0x00000002 0x00000006
1190 0x00000003 0x00000003 0x00000006 0x00000004
1191 0x00000002 0x00000009 0x00000003 0x00000003
1192 0x00000002 0x00000002 0x00000002 0x00000004
1193 0x00000003 0x00000008 0x0000000b 0x0000004d
1194 0x00000000 0x00000003 0x00000003 0x00000003
1195 0x00000008 0x00000001 0x0000000a 0x00000004
1196 0x00000003 0x00000008 0x00000004 0x00000006
1197 0x00000002 0x00000068 0x00000000 0x00000003
1198 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1199 0x0007c000 0x00000000 0x00000000 0x00000003
1200 0x00000000 0x00000000 0x00000000 0x00000000>;
1201 };
1203 emc-table@50000 {
1204 reg = <50000>;
1205 compatible = "nvidia,tegra20-emc-table";
1206 clock-frequency = <50000>;
1207 nvidia,emc-registers = <0x00000003 0x00000007
1208 0x00000003 0x00000003 0x00000006 0x00000004
1209 0x00000002 0x00000009 0x00000003 0x00000003
1210 0x00000002 0x00000002 0x00000002 0x00000005
1211 0x00000003 0x00000008 0x0000000b 0x0000009f
1212 0x00000000 0x00000003 0x00000003 0x00000003
1213 0x00000008 0x00000001 0x0000000a 0x00000007
1214 0x00000003 0x00000008 0x00000004 0x00000006
1215 0x00000002 0x000000d0 0x00000000 0x00000000
1216 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1217 0x0007c000 0x00000000 0x00000000 0x00000005
1218 0x00000000 0x00000000 0x00000000 0x00000000>;
1219 };
1221 emc-table@75000 {
1222 reg = <75000>;
1223 compatible = "nvidia,tegra20-emc-table";
1224 clock-frequency = <75000>;
1225 nvidia,emc-registers = <0x00000005 0x0000000a
1226 0x00000004 0x00000003 0x00000006 0x00000004
1227 0x00000002 0x00000009 0x00000003 0x00000003
1228 0x00000002 0x00000002 0x00000002 0x00000005
1229 0x00000003 0x00000008 0x0000000b 0x000000ff
1230 0x00000000 0x00000003 0x00000003 0x00000003
1231 0x00000008 0x00000001 0x0000000a 0x0000000b
1232 0x00000003 0x00000008 0x00000004 0x00000006
1233 0x00000002 0x00000138 0x00000000 0x00000000
1234 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1235 0x0007c000 0x00000000 0x00000000 0x00000007
1236 0x00000000 0x00000000 0x00000000 0x00000000>;
1237 };
1239 emc-table@150000 {
1240 reg = <150000>;
1241 compatible = "nvidia,tegra20-emc-table";
1242 clock-frequency = <150000>;
1243 nvidia,emc-registers = <0x00000009 0x00000014
1244 0x00000007 0x00000003 0x00000006 0x00000004
1245 0x00000002 0x00000009 0x00000003 0x00000003
1246 0x00000002 0x00000002 0x00000002 0x00000005
1247 0x00000003 0x00000008 0x0000000b 0x0000021f
1248 0x00000000 0x00000003 0x00000003 0x00000003
1249 0x00000008 0x00000001 0x0000000a 0x00000015
1250 0x00000003 0x00000008 0x00000004 0x00000006
1251 0x00000002 0x00000270 0x00000000 0x00000001
1252 0x00000000 0x00000000 0x00000282 0xa07c04ae
1253 0x007e4010 0x00000000 0x00000000 0x0000000e
1254 0x00000000 0x00000000 0x00000000 0x00000000>;
1255 };
1257 emc-table@300000 {
1258 reg = <300000>;
1259 compatible = "nvidia,tegra20-emc-table";
1260 clock-frequency = <300000>;
1261 nvidia,emc-registers = <0x00000012 0x00000027
1262 0x0000000d 0x00000006 0x00000007 0x00000005
1263 0x00000003 0x00000009 0x00000006 0x00000006
1264 0x00000003 0x00000003 0x00000002 0x00000006
1265 0x00000003 0x00000009 0x0000000c 0x0000045f
1266 0x00000000 0x00000004 0x00000004 0x00000006
1267 0x00000008 0x00000001 0x0000000e 0x0000002a
1268 0x00000003 0x0000000f 0x00000007 0x00000005
1269 0x00000002 0x000004e1 0x00000005 0x00000002
1270 0x00000000 0x00000000 0x00000282 0xe059048b
1271 0x007e0010 0x00000000 0x00000000 0x0000001b
1272 0x00000000 0x00000000 0x00000000 0x00000000>;
1273 };
1274 };
1276 emc-tables@2 {
1277 nvidia,ram-code = <2>; /* hynix-8gb */
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1282 emc-table@25000 {
1283 reg = <25000>;
1284 compatible = "nvidia,tegra20-emc-table";
1285 clock-frequency = <25000>;
1286 nvidia,emc-registers = <0x00000002 0x00000006
1287 0x00000003 0x00000003 0x00000006 0x00000004
1288 0x00000002 0x00000009 0x00000003 0x00000003
1289 0x00000002 0x00000002 0x00000002 0x00000004
1290 0x00000003 0x00000008 0x0000000b 0x0000004d
1291 0x00000000 0x00000003 0x00000003 0x00000003
1292 0x00000008 0x00000001 0x0000000a 0x00000004
1293 0x00000003 0x00000008 0x00000004 0x00000006
1294 0x00000002 0x00000068 0x00000000 0x00000003
1295 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1296 0x00070000 0x00000000 0x00000000 0x00000003
1297 0x00000000 0x00000000 0x00000000 0x00000000>;
1298 };
1300 emc-table@50000 {
1301 reg = <50000>;
1302 compatible = "nvidia,tegra20-emc-table";
1303 clock-frequency = <50000>;
1304 nvidia,emc-registers = <0x00000003 0x00000007
1305 0x00000003 0x00000003 0x00000006 0x00000004
1306 0x00000002 0x00000009 0x00000003 0x00000003
1307 0x00000002 0x00000002 0x00000002 0x00000005
1308 0x00000003 0x00000008 0x0000000b 0x0000009f
1309 0x00000000 0x00000003 0x00000003 0x00000003
1310 0x00000008 0x00000001 0x0000000a 0x00000007
1311 0x00000003 0x00000008 0x00000004 0x00000006
1312 0x00000002 0x000000d0 0x00000000 0x00000000
1313 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1314 0x00070000 0x00000000 0x00000000 0x00000005
1315 0x00000000 0x00000000 0x00000000 0x00000000>;
1316 };
1318 emc-table@75000 {
1319 reg = <75000>;
1320 compatible = "nvidia,tegra20-emc-table";
1321 clock-frequency = <75000>;
1322 nvidia,emc-registers = <0x00000005 0x0000000a
1323 0x00000004 0x00000003 0x00000006 0x00000004
1324 0x00000002 0x00000009 0x00000003 0x00000003
1325 0x00000002 0x00000002 0x00000002 0x00000005
1326 0x00000003 0x00000008 0x0000000b 0x000000ff
1327 0x00000000 0x00000003 0x00000003 0x00000003
1328 0x00000008 0x00000001 0x0000000a 0x0000000b
1329 0x00000003 0x00000008 0x00000004 0x00000006
1330 0x00000002 0x00000138 0x00000000 0x00000000
1331 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1332 0x00070000 0x00000000 0x00000000 0x00000007
1333 0x00000000 0x00000000 0x00000000 0x00000000>;
1334 };
1336 emc-table@150000 {
1337 reg = <150000>;
1338 compatible = "nvidia,tegra20-emc-table";
1339 clock-frequency = <150000>;
1340 nvidia,emc-registers = <0x00000009 0x00000014
1341 0x00000007 0x00000003 0x00000006 0x00000004
1342 0x00000002 0x00000009 0x00000003 0x00000003
1343 0x00000002 0x00000002 0x00000002 0x00000005
1344 0x00000003 0x00000008 0x0000000b 0x0000021f
1345 0x00000000 0x00000003 0x00000003 0x00000003
1346 0x00000008 0x00000001 0x0000000a 0x00000015
1347 0x00000003 0x00000008 0x00000004 0x00000006
1348 0x00000002 0x00000270 0x00000000 0x00000001
1349 0x00000000 0x00000000 0x00000282 0xa07c04ae
1350 0x007dd010 0x00000000 0x00000000 0x0000000e
1351 0x00000000 0x00000000 0x00000000 0x00000000>;
1352 };
1354 emc-table@300000 {
1355 reg = <300000>;
1356 compatible = "nvidia,tegra20-emc-table";
1357 clock-frequency = <300000>;
1358 nvidia,emc-registers = <0x00000012 0x00000027
1359 0x0000000d 0x00000006 0x00000007 0x00000005
1360 0x00000003 0x00000009 0x00000006 0x00000006
1361 0x00000003 0x00000003 0x00000002 0x00000006
1362 0x00000003 0x00000009 0x0000000c 0x0000045f
1363 0x00000000 0x00000004 0x00000004 0x00000006
1364 0x00000008 0x00000001 0x0000000e 0x0000002a
1365 0x00000003 0x0000000f 0x00000007 0x00000005
1366 0x00000002 0x000004e1 0x00000005 0x00000002
1367 0x00000000 0x00000000 0x00000282 0xe059048b
1368 0x007e2010 0x00000000 0x00000000 0x0000001b
1369 0x00000000 0x00000000 0x00000000 0x00000000>;
1370 };
1371 };
1373 emc-tables@3 {
1374 nvidia,ram-code = <3>; /* hynix-4gb */
1376 #address-cells = <1>;
1377 #size-cells = <0>;
1379 emc-table@25000 {
1380 reg = <25000>;
1381 compatible = "nvidia,tegra20-emc-table";
1382 clock-frequency = <25000>;
1383 nvidia,emc-registers = <0x00000002 0x00000006
1384 0x00000003 0x00000003 0x00000006 0x00000004
1385 0x00000002 0x00000009 0x00000003 0x00000003
1386 0x00000002 0x00000002 0x00000002 0x00000004
1387 0x00000003 0x00000008 0x0000000b 0x0000004d
1388 0x00000000 0x00000003 0x00000003 0x00000003
1389 0x00000008 0x00000001 0x0000000a 0x00000004
1390 0x00000003 0x00000008 0x00000004 0x00000006
1391 0x00000002 0x00000068 0x00000000 0x00000003
1392 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1393 0x0007c000 0x00000000 0x00000000 0x00000003
1394 0x00000000 0x00000000 0x00000000 0x00000000>;
1395 };
1397 emc-table@50000 {
1398 reg = <50000>;
1399 compatible = "nvidia,tegra20-emc-table";
1400 clock-frequency = <50000>;
1401 nvidia,emc-registers = <0x00000003 0x00000007
1402 0x00000003 0x00000003 0x00000006 0x00000004
1403 0x00000002 0x00000009 0x00000003 0x00000003
1404 0x00000002 0x00000002 0x00000002 0x00000005
1405 0x00000003 0x00000008 0x0000000b 0x0000009f
1406 0x00000000 0x00000003 0x00000003 0x00000003
1407 0x00000008 0x00000001 0x0000000a 0x00000007
1408 0x00000003 0x00000008 0x00000004 0x00000006
1409 0x00000002 0x000000d0 0x00000000 0x00000000
1410 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1411 0x0007c000 0x00078000 0x00000000 0x00000005
1412 0x00000000 0x00000000 0x00000000 0x00000000>;
1413 };
1415 emc-table@75000 {
1416 reg = <75000>;
1417 compatible = "nvidia,tegra20-emc-table";
1418 clock-frequency = <75000>;
1419 nvidia,emc-registers = <0x00000005 0x0000000a
1420 0x00000004 0x00000003 0x00000006 0x00000004
1421 0x00000002 0x00000009 0x00000003 0x00000003
1422 0x00000002 0x00000002 0x00000002 0x00000005
1423 0x00000003 0x00000008 0x0000000b 0x000000ff
1424 0x00000000 0x00000003 0x00000003 0x00000003
1425 0x00000008 0x00000001 0x0000000a 0x0000000b
1426 0x00000003 0x00000008 0x00000004 0x00000006
1427 0x00000002 0x00000138 0x00000000 0x00000000
1428 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1429 0x0007c000 0x00000000 0x00000000 0x00000007
1430 0x00000000 0x00000000 0x00000000 0x00000000>;
1431 };
1433 emc-table@150000 {
1434 reg = <150000>;
1435 compatible = "nvidia,tegra20-emc-table";
1436 clock-frequency = <150000>;
1437 nvidia,emc-registers = <0x00000009 0x00000014
1438 0x00000007 0x00000003 0x00000006 0x00000004
1439 0x00000002 0x00000009 0x00000003 0x00000003
1440 0x00000002 0x00000002 0x00000002 0x00000005
1441 0x00000003 0x00000008 0x0000000b 0x0000021f
1442 0x00000000 0x00000003 0x00000003 0x00000003
1443 0x00000008 0x00000001 0x0000000a 0x00000015
1444 0x00000003 0x00000008 0x00000004 0x00000006
1445 0x00000002 0x00000270 0x00000000 0x00000001
1446 0x00000000 0x00000000 0x00000282 0xa07c04ae
1447 0x007e4010 0x00000000 0x00000000 0x0000000e
1448 0x00000000 0x00000000 0x00000000 0x00000000>;
1449 };
1451 emc-table@300000 {
1452 reg = <300000>;
1453 compatible = "nvidia,tegra20-emc-table";
1454 clock-frequency = <300000>;
1455 nvidia,emc-registers = <0x00000012 0x00000027
1456 0x0000000d 0x00000006 0x00000007 0x00000005
1457 0x00000003 0x00000009 0x00000006 0x00000006
1458 0x00000003 0x00000003 0x00000002 0x00000006
1459 0x00000003 0x00000009 0x0000000c 0x0000045f
1460 0x00000000 0x00000004 0x00000004 0x00000006
1461 0x00000008 0x00000001 0x0000000e 0x0000002a
1462 0x00000003 0x0000000f 0x00000007 0x00000005
1463 0x00000002 0x000004e1 0x00000005 0x00000002
1464 0x00000000 0x00000000 0x00000282 0xe059048b
1465 0x007e0010 0x00000000 0x00000000 0x0000001b
1466 0x00000000 0x00000000 0x00000000 0x00000000>;
1467 };
1468 };
1469 };
1470 };
1472 &emc_icc_dvfs_opp_table {
1473 /delete-node/ opp@666000000;
1474 /delete-node/ opp@760000000;
1475 };