| blob | 6ce498178105499f953528fbf4ee155d4acdb17b |
1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra20-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra20-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
9 #include "tegra20-peripherals-opp.dtsi"
11 / {
12 compatible = "nvidia,tegra20";
13 interrupt-parent = <&lic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
17 memory@0 {
18 device_type = "memory";
19 reg = <0 0>;
20 };
22 sram@40000000 {
23 compatible = "mmio-sram";
24 reg = <0x40000000 0x40000>;
25 #address-cells = <1>;
26 #size-cells = <1>;
27 ranges = <0 0x40000000 0x40000>;
29 vde_pool: sram@400 {
30 reg = <0x400 0x3fc00>;
31 pool;
32 };
33 };
35 host1x@50000000 {
36 compatible = "nvidia,tegra20-host1x";
37 reg = <0x50000000 0x00024000>;
38 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
39 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
40 interrupt-names = "syncpt", "host1x";
41 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
42 clock-names = "host1x";
43 resets = <&tegra_car 28>;
44 reset-names = "host1x";
46 #address-cells = <1>;
47 #size-cells = <1>;
49 ranges = <0x54000000 0x54000000 0x04000000>;
51 mpe@54040000 {
52 compatible = "nvidia,tegra20-mpe";
53 reg = <0x54040000 0x00040000>;
54 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&tegra_car TEGRA20_CLK_MPE>;
56 resets = <&tegra_car 60>;
57 reset-names = "mpe";
58 };
60 vi@54080000 {
61 compatible = "nvidia,tegra20-vi";
62 reg = <0x54080000 0x00040000>;
63 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&tegra_car TEGRA20_CLK_VI>;
65 resets = <&tegra_car 20>;
66 reset-names = "vi";
67 };
69 epp@540c0000 {
70 compatible = "nvidia,tegra20-epp";
71 reg = <0x540c0000 0x00040000>;
72 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
73 clocks = <&tegra_car TEGRA20_CLK_EPP>;
74 resets = <&tegra_car 19>;
75 reset-names = "epp";
76 };
78 isp@54100000 {
79 compatible = "nvidia,tegra20-isp";
80 reg = <0x54100000 0x00040000>;
81 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
82 clocks = <&tegra_car TEGRA20_CLK_ISP>;
83 resets = <&tegra_car 23>;
84 reset-names = "isp";
85 };
87 gr2d@54140000 {
88 compatible = "nvidia,tegra20-gr2d";
89 reg = <0x54140000 0x00040000>;
90 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
91 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
92 resets = <&tegra_car 21>;
93 reset-names = "2d";
94 };
96 gr3d@54180000 {
97 compatible = "nvidia,tegra20-gr3d";
98 reg = <0x54180000 0x00040000>;
99 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
100 resets = <&tegra_car 24>;
101 reset-names = "3d";
102 };
104 dc@54200000 {
105 compatible = "nvidia,tegra20-dc";
106 reg = <0x54200000 0x00040000>;
107 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
109 <&tegra_car TEGRA20_CLK_PLL_P>;
110 clock-names = "dc", "parent";
111 resets = <&tegra_car 27>;
112 reset-names = "dc";
114 nvidia,head = <0>;
116 interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>,
117 <&mc TEGRA20_MC_DISPLAY0B &emc>,
118 <&mc TEGRA20_MC_DISPLAY1B &emc>,
119 <&mc TEGRA20_MC_DISPLAY0C &emc>,
120 <&mc TEGRA20_MC_DISPLAYHC &emc>;
121 interconnect-names = "wina",
122 "winb",
123 "winb-vfilter",
124 "winc",
125 "cursor";
127 rgb {
128 status = "disabled";
129 };
130 };
132 dc@54240000 {
133 compatible = "nvidia,tegra20-dc";
134 reg = <0x54240000 0x00040000>;
135 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
136 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
137 <&tegra_car TEGRA20_CLK_PLL_P>;
138 clock-names = "dc", "parent";
139 resets = <&tegra_car 26>;
140 reset-names = "dc";
142 nvidia,head = <1>;
144 interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>,
145 <&mc TEGRA20_MC_DISPLAY0BB &emc>,
146 <&mc TEGRA20_MC_DISPLAY1BB &emc>,
147 <&mc TEGRA20_MC_DISPLAY0CB &emc>,
148 <&mc TEGRA20_MC_DISPLAYHCB &emc>;
149 interconnect-names = "wina",
150 "winb",
151 "winb-vfilter",
152 "winc",
153 "cursor";
155 rgb {
156 status = "disabled";
157 };
158 };
160 hdmi@54280000 {
161 compatible = "nvidia,tegra20-hdmi";
162 reg = <0x54280000 0x00040000>;
163 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
165 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
166 clock-names = "hdmi", "parent";
167 resets = <&tegra_car 51>;
168 reset-names = "hdmi";
169 status = "disabled";
170 };
172 tvo@542c0000 {
173 compatible = "nvidia,tegra20-tvo";
174 reg = <0x542c0000 0x00040000>;
175 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&tegra_car TEGRA20_CLK_TVO>;
177 status = "disabled";
178 };
180 dsi@54300000 {
181 compatible = "nvidia,tegra20-dsi";
182 reg = <0x54300000 0x00040000>;
183 clocks = <&tegra_car TEGRA20_CLK_DSI>,
184 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
185 clock-names = "dsi", "parent";
186 resets = <&tegra_car 48>;
187 reset-names = "dsi";
188 status = "disabled";
189 };
190 };
192 timer@50040600 {
193 compatible = "arm,cortex-a9-twd-timer";
194 interrupt-parent = <&intc>;
195 reg = <0x50040600 0x20>;
196 interrupts = <GIC_PPI 13
197 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
198 clocks = <&tegra_car TEGRA20_CLK_TWD>;
199 };
201 intc: interrupt-controller@50041000 {
202 compatible = "arm,cortex-a9-gic";
203 reg = <0x50041000 0x1000>,
204 <0x50040100 0x0100>;
205 interrupt-controller;
206 #interrupt-cells = <3>;
207 interrupt-parent = <&intc>;
208 };
210 cache-controller@50043000 {
211 compatible = "arm,pl310-cache";
212 reg = <0x50043000 0x1000>;
213 arm,data-latency = <5 5 2>;
214 arm,tag-latency = <4 4 2>;
215 cache-unified;
216 cache-level = <2>;
217 };
219 lic: interrupt-controller@60004000 {
220 compatible = "nvidia,tegra20-ictlr";
221 reg = <0x60004000 0x100>,
222 <0x60004100 0x50>,
223 <0x60004200 0x50>,
224 <0x60004300 0x50>;
225 interrupt-controller;
226 #interrupt-cells = <3>;
227 interrupt-parent = <&intc>;
228 };
230 timer@60005000 {
231 compatible = "nvidia,tegra20-timer";
232 reg = <0x60005000 0x60>;
233 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
238 };
240 tegra_car: clock@60006000 {
241 compatible = "nvidia,tegra20-car";
242 reg = <0x60006000 0x1000>;
243 #clock-cells = <1>;
244 #reset-cells = <1>;
245 };
247 flow-controller@60007000 {
248 compatible = "nvidia,tegra20-flowctrl";
249 reg = <0x60007000 0x1000>;
250 };
252 apbdma: dma@6000a000 {
253 compatible = "nvidia,tegra20-apbdma";
254 reg = <0x6000a000 0x1200>;
255 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
256 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
268 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
269 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
270 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
272 resets = <&tegra_car 34>;
273 reset-names = "dma";
274 #dma-cells = <1>;
275 };
277 ahb@6000c000 {
278 compatible = "nvidia,tegra20-ahb";
279 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */
280 };
282 gpio: gpio@6000d000 {
283 compatible = "nvidia,tegra20-gpio";
284 reg = <0x6000d000 0x1000>;
285 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
292 #gpio-cells = <2>;
293 gpio-controller;
294 #interrupt-cells = <2>;
295 interrupt-controller;
296 /*
297 gpio-ranges = <&pinmux 0 0 224>;
298 */
299 };
301 vde@6001a000 {
302 compatible = "nvidia,tegra20-vde";
303 reg = <0x6001a000 0x1000>, /* Syntax Engine */
304 <0x6001b000 0x1000>, /* Video Bitstream Engine */
305 <0x6001c000 0x100>, /* Macroblock Engine */
306 <0x6001c200 0x100>, /* Post-processing Engine */
307 <0x6001c400 0x100>, /* Motion Compensation Engine */
308 <0x6001c600 0x100>, /* Transform Engine */
309 <0x6001c800 0x100>, /* Pixel prediction block */
310 <0x6001ca00 0x100>, /* Video DMA */
311 <0x6001d800 0x300>; /* Video frame controls */
312 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
313 "tfe", "ppb", "vdma", "frameid";
314 iram = <&vde_pool>; /* IRAM region */
315 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
316 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
317 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
318 interrupt-names = "sync-token", "bsev", "sxe";
319 clocks = <&tegra_car TEGRA20_CLK_VDE>;
320 reset-names = "vde", "mc";
321 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>;
322 };
324 apbmisc@70000800 {
325 compatible = "nvidia,tegra20-apbmisc";
326 reg = <0x70000800 0x64>, /* Chip revision */
327 <0x70000008 0x04>; /* Strapping options */
328 };
330 pinmux: pinmux@70000014 {
331 compatible = "nvidia,tegra20-pinmux";
332 reg = <0x70000014 0x10>, /* Tri-state registers */
333 <0x70000080 0x20>, /* Mux registers */
334 <0x700000a0 0x14>, /* Pull-up/down registers */
335 <0x70000868 0xa8>; /* Pad control registers */
336 };
338 das@70000c00 {
339 compatible = "nvidia,tegra20-das";
340 reg = <0x70000c00 0x80>;
341 };
343 tegra_ac97: ac97@70002000 {
344 compatible = "nvidia,tegra20-ac97";
345 reg = <0x70002000 0x200>;
346 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&tegra_car TEGRA20_CLK_AC97>;
348 resets = <&tegra_car 3>;
349 reset-names = "ac97";
350 dmas = <&apbdma 12>, <&apbdma 12>;
351 dma-names = "rx", "tx";
352 status = "disabled";
353 };
355 tegra_i2s1: i2s@70002800 {
356 compatible = "nvidia,tegra20-i2s";
357 reg = <0x70002800 0x200>;
358 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
360 resets = <&tegra_car 11>;
361 reset-names = "i2s";
362 dmas = <&apbdma 2>, <&apbdma 2>;
363 dma-names = "rx", "tx";
364 status = "disabled";
365 };
367 tegra_i2s2: i2s@70002a00 {
368 compatible = "nvidia,tegra20-i2s";
369 reg = <0x70002a00 0x200>;
370 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
372 resets = <&tegra_car 18>;
373 reset-names = "i2s";
374 dmas = <&apbdma 1>, <&apbdma 1>;
375 dma-names = "rx", "tx";
376 status = "disabled";
377 };
379 /*
380 * There are two serial driver i.e. 8250 based simple serial
381 * driver and APB DMA based serial driver for higher baudrate
382 * and performace. To enable the 8250 based driver, the compatible
383 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
384 * driver, the compatible is "nvidia,tegra20-hsuart".
385 */
386 uarta: serial@70006000 {
387 compatible = "nvidia,tegra20-uart";
388 reg = <0x70006000 0x40>;
389 reg-shift = <2>;
390 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
392 resets = <&tegra_car 6>;
393 reset-names = "serial";
394 dmas = <&apbdma 8>, <&apbdma 8>;
395 dma-names = "rx", "tx";
396 status = "disabled";
397 };
399 uartb: serial@70006040 {
400 compatible = "nvidia,tegra20-uart";
401 reg = <0x70006040 0x40>;
402 reg-shift = <2>;
403 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
405 resets = <&tegra_car 7>;
406 reset-names = "serial";
407 dmas = <&apbdma 9>, <&apbdma 9>;
408 dma-names = "rx", "tx";
409 status = "disabled";
410 };
412 uartc: serial@70006200 {
413 compatible = "nvidia,tegra20-uart";
414 reg = <0x70006200 0x100>;
415 reg-shift = <2>;
416 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
418 resets = <&tegra_car 55>;
419 reset-names = "serial";
420 dmas = <&apbdma 10>, <&apbdma 10>;
421 dma-names = "rx", "tx";
422 status = "disabled";
423 };
425 uartd: serial@70006300 {
426 compatible = "nvidia,tegra20-uart";
427 reg = <0x70006300 0x100>;
428 reg-shift = <2>;
429 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
431 resets = <&tegra_car 65>;
432 reset-names = "serial";
433 dmas = <&apbdma 19>, <&apbdma 19>;
434 dma-names = "rx", "tx";
435 status = "disabled";
436 };
438 uarte: serial@70006400 {
439 compatible = "nvidia,tegra20-uart";
440 reg = <0x70006400 0x100>;
441 reg-shift = <2>;
442 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
444 resets = <&tegra_car 66>;
445 reset-names = "serial";
446 dmas = <&apbdma 20>, <&apbdma 20>;
447 dma-names = "rx", "tx";
448 status = "disabled";
449 };
451 nand-controller@70008000 {
452 compatible = "nvidia,tegra20-nand";
453 reg = <0x70008000 0x100>;
454 #address-cells = <1>;
455 #size-cells = <0>;
456 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
458 clock-names = "nand";
459 resets = <&tegra_car 13>;
460 reset-names = "nand";
461 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
462 assigned-clock-rates = <150000000>;
463 status = "disabled";
464 };
466 gmi@70009000 {
467 compatible = "nvidia,tegra20-gmi";
468 reg = <0x70009000 0x1000>;
469 #address-cells = <2>;
470 #size-cells = <1>;
471 ranges = <0 0 0xd0000000 0xfffffff>;
472 clocks = <&tegra_car TEGRA20_CLK_NOR>;
473 clock-names = "gmi";
474 resets = <&tegra_car 42>;
475 reset-names = "gmi";
476 status = "disabled";
477 };
479 pwm: pwm@7000a000 {
480 compatible = "nvidia,tegra20-pwm";
481 reg = <0x7000a000 0x100>;
482 #pwm-cells = <2>;
483 clocks = <&tegra_car TEGRA20_CLK_PWM>;
484 resets = <&tegra_car 17>;
485 reset-names = "pwm";
486 status = "disabled";
487 };
489 rtc@7000e000 {
490 compatible = "nvidia,tegra20-rtc";
491 reg = <0x7000e000 0x100>;
492 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&tegra_car TEGRA20_CLK_RTC>;
494 };
496 i2c@7000c000 {
497 compatible = "nvidia,tegra20-i2c";
498 reg = <0x7000c000 0x100>;
499 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
503 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
504 clock-names = "div-clk", "fast-clk";
505 resets = <&tegra_car 12>;
506 reset-names = "i2c";
507 dmas = <&apbdma 21>, <&apbdma 21>;
508 dma-names = "rx", "tx";
509 status = "disabled";
510 };
512 spi@7000c380 {
513 compatible = "nvidia,tegra20-sflash";
514 reg = <0x7000c380 0x80>;
515 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 clocks = <&tegra_car TEGRA20_CLK_SPI>;
519 resets = <&tegra_car 43>;
520 reset-names = "spi";
521 dmas = <&apbdma 11>, <&apbdma 11>;
522 dma-names = "rx", "tx";
523 status = "disabled";
524 };
526 i2c@7000c400 {
527 compatible = "nvidia,tegra20-i2c";
528 reg = <0x7000c400 0x100>;
529 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
530 #address-cells = <1>;
531 #size-cells = <0>;
532 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
533 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
534 clock-names = "div-clk", "fast-clk";
535 resets = <&tegra_car 54>;
536 reset-names = "i2c";
537 dmas = <&apbdma 22>, <&apbdma 22>;
538 dma-names = "rx", "tx";
539 status = "disabled";
540 };
542 i2c@7000c500 {
543 compatible = "nvidia,tegra20-i2c";
544 reg = <0x7000c500 0x100>;
545 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
546 #address-cells = <1>;
547 #size-cells = <0>;
548 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
549 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
550 clock-names = "div-clk", "fast-clk";
551 resets = <&tegra_car 67>;
552 reset-names = "i2c";
553 dmas = <&apbdma 23>, <&apbdma 23>;
554 dma-names = "rx", "tx";
555 status = "disabled";
556 };
558 i2c@7000d000 {
559 compatible = "nvidia,tegra20-i2c-dvc";
560 reg = <0x7000d000 0x200>;
561 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
562 #address-cells = <1>;
563 #size-cells = <0>;
564 clocks = <&tegra_car TEGRA20_CLK_DVC>,
565 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
566 clock-names = "div-clk", "fast-clk";
567 resets = <&tegra_car 47>;
568 reset-names = "i2c";
569 dmas = <&apbdma 24>, <&apbdma 24>;
570 dma-names = "rx", "tx";
571 status = "disabled";
572 };
574 spi@7000d400 {
575 compatible = "nvidia,tegra20-slink";
576 reg = <0x7000d400 0x200>;
577 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
578 #address-cells = <1>;
579 #size-cells = <0>;
580 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
581 resets = <&tegra_car 41>;
582 reset-names = "spi";
583 dmas = <&apbdma 15>, <&apbdma 15>;
584 dma-names = "rx", "tx";
585 status = "disabled";
586 };
588 spi@7000d600 {
589 compatible = "nvidia,tegra20-slink";
590 reg = <0x7000d600 0x200>;
591 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
592 #address-cells = <1>;
593 #size-cells = <0>;
594 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
595 resets = <&tegra_car 44>;
596 reset-names = "spi";
597 dmas = <&apbdma 16>, <&apbdma 16>;
598 dma-names = "rx", "tx";
599 status = "disabled";
600 };
602 spi@7000d800 {
603 compatible = "nvidia,tegra20-slink";
604 reg = <0x7000d800 0x200>;
605 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
606 #address-cells = <1>;
607 #size-cells = <0>;
608 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
609 resets = <&tegra_car 46>;
610 reset-names = "spi";
611 dmas = <&apbdma 17>, <&apbdma 17>;
612 dma-names = "rx", "tx";
613 status = "disabled";
614 };
616 spi@7000da00 {
617 compatible = "nvidia,tegra20-slink";
618 reg = <0x7000da00 0x200>;
619 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
620 #address-cells = <1>;
621 #size-cells = <0>;
622 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
623 resets = <&tegra_car 68>;
624 reset-names = "spi";
625 dmas = <&apbdma 18>, <&apbdma 18>;
626 dma-names = "rx", "tx";
627 status = "disabled";
628 };
630 kbc@7000e200 {
631 compatible = "nvidia,tegra20-kbc";
632 reg = <0x7000e200 0x100>;
633 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&tegra_car TEGRA20_CLK_KBC>;
635 resets = <&tegra_car 36>;
636 reset-names = "kbc";
637 status = "disabled";
638 };
640 tegra_pmc: pmc@7000e400 {
641 compatible = "nvidia,tegra20-pmc";
642 reg = <0x7000e400 0x400>;
643 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
644 clock-names = "pclk", "clk32k_in";
645 #clock-cells = <1>;
646 };
648 mc: memory-controller@7000f000 {
649 compatible = "nvidia,tegra20-mc-gart";
650 reg = <0x7000f000 0x00000400>, /* controller registers */
651 <0x58000000 0x02000000>; /* GART aperture */
652 clocks = <&tegra_car TEGRA20_CLK_MC>;
653 clock-names = "mc";
654 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
655 #reset-cells = <1>;
656 #iommu-cells = <0>;
657 #interconnect-cells = <1>;
658 };
660 emc: memory-controller@7000f400 {
661 compatible = "nvidia,tegra20-emc";
662 reg = <0x7000f400 0x400>;
663 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&tegra_car TEGRA20_CLK_EMC>;
665 #address-cells = <1>;
666 #size-cells = <0>;
667 #interconnect-cells = <0>;
669 operating-points-v2 = <&emc_icc_dvfs_opp_table>;
670 nvidia,memory-controller = <&mc>;
671 };
673 fuse@7000f800 {
674 compatible = "nvidia,tegra20-efuse";
675 reg = <0x7000f800 0x400>;
676 clocks = <&tegra_car TEGRA20_CLK_FUSE>;
677 clock-names = "fuse";
678 resets = <&tegra_car 39>;
679 reset-names = "fuse";
680 };
682 pcie@80003000 {
683 compatible = "nvidia,tegra20-pcie";
684 device_type = "pci";
685 reg = <0x80003000 0x00000800>, /* PADS registers */
686 <0x80003800 0x00000200>, /* AFI registers */
687 <0x90000000 0x10000000>; /* configuration space */
688 reg-names = "pads", "afi", "cs";
689 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
690 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
691 interrupt-names = "intr", "msi";
693 #interrupt-cells = <1>;
694 interrupt-map-mask = <0 0 0 0>;
695 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
697 bus-range = <0x00 0xff>;
698 #address-cells = <3>;
699 #size-cells = <2>;
701 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
702 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
703 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */
704 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
705 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
707 clocks = <&tegra_car TEGRA20_CLK_PEX>,
708 <&tegra_car TEGRA20_CLK_AFI>,
709 <&tegra_car TEGRA20_CLK_PLL_E>;
710 clock-names = "pex", "afi", "pll_e";
711 resets = <&tegra_car 70>,
712 <&tegra_car 72>,
713 <&tegra_car 74>;
714 reset-names = "pex", "afi", "pcie_x";
715 status = "disabled";
717 pci@1,0 {
718 device_type = "pci";
719 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
720 reg = <0x000800 0 0 0 0>;
721 bus-range = <0x00 0xff>;
722 status = "disabled";
724 #address-cells = <3>;
725 #size-cells = <2>;
726 ranges;
728 nvidia,num-lanes = <2>;
729 };
731 pci@2,0 {
732 device_type = "pci";
733 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
734 reg = <0x001000 0 0 0 0>;
735 bus-range = <0x00 0xff>;
736 status = "disabled";
738 #address-cells = <3>;
739 #size-cells = <2>;
740 ranges;
742 nvidia,num-lanes = <2>;
743 };
744 };
746 usb@c5000000 {
747 compatible = "nvidia,tegra20-ehci", "usb-ehci";
748 reg = <0xc5000000 0x4000>;
749 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
750 phy_type = "utmi";
751 nvidia,has-legacy-mode;
752 clocks = <&tegra_car TEGRA20_CLK_USBD>;
753 resets = <&tegra_car 22>;
754 reset-names = "usb";
755 nvidia,needs-double-reset;
756 nvidia,phy = <&phy1>;
757 status = "disabled";
758 };
760 phy1: usb-phy@c5000000 {
761 compatible = "nvidia,tegra20-usb-phy";
762 reg = <0xc5000000 0x4000>,
763 <0xc5000000 0x4000>;
764 phy_type = "utmi";
765 clocks = <&tegra_car TEGRA20_CLK_USBD>,
766 <&tegra_car TEGRA20_CLK_PLL_U>,
767 <&tegra_car TEGRA20_CLK_CLK_M>,
768 <&tegra_car TEGRA20_CLK_USBD>;
769 clock-names = "reg", "pll_u", "timer", "utmi-pads";
770 resets = <&tegra_car 22>, <&tegra_car 22>;
771 reset-names = "usb", "utmi-pads";
772 #phy-cells = <0>;
773 nvidia,has-legacy-mode;
774 nvidia,hssync-start-delay = <9>;
775 nvidia,idle-wait-delay = <17>;
776 nvidia,elastic-limit = <16>;
777 nvidia,term-range-adj = <6>;
778 nvidia,xcvr-setup = <9>;
779 nvidia,xcvr-lsfslew = <1>;
780 nvidia,xcvr-lsrslew = <1>;
781 nvidia,has-utmi-pad-registers;
782 status = "disabled";
783 };
785 usb@c5004000 {
786 compatible = "nvidia,tegra20-ehci", "usb-ehci";
787 reg = <0xc5004000 0x4000>;
788 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
789 phy_type = "ulpi";
790 clocks = <&tegra_car TEGRA20_CLK_USB2>;
791 resets = <&tegra_car 58>;
792 reset-names = "usb";
793 nvidia,phy = <&phy2>;
794 status = "disabled";
795 };
797 phy2: usb-phy@c5004000 {
798 compatible = "nvidia,tegra20-usb-phy";
799 reg = <0xc5004000 0x4000>;
800 phy_type = "ulpi";
801 clocks = <&tegra_car TEGRA20_CLK_USB2>,
802 <&tegra_car TEGRA20_CLK_PLL_U>,
803 <&tegra_car TEGRA20_CLK_CDEV2>;
804 clock-names = "reg", "pll_u", "ulpi-link";
805 resets = <&tegra_car 58>, <&tegra_car 22>;
806 reset-names = "usb", "utmi-pads";
807 #phy-cells = <0>;
808 status = "disabled";
809 };
811 usb@c5008000 {
812 compatible = "nvidia,tegra20-ehci", "usb-ehci";
813 reg = <0xc5008000 0x4000>;
814 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
815 phy_type = "utmi";
816 clocks = <&tegra_car TEGRA20_CLK_USB3>;
817 resets = <&tegra_car 59>;
818 reset-names = "usb";
819 nvidia,phy = <&phy3>;
820 status = "disabled";
821 };
823 phy3: usb-phy@c5008000 {
824 compatible = "nvidia,tegra20-usb-phy";
825 reg = <0xc5008000 0x4000>,
826 <0xc5000000 0x4000>;
827 phy_type = "utmi";
828 clocks = <&tegra_car TEGRA20_CLK_USB3>,
829 <&tegra_car TEGRA20_CLK_PLL_U>,
830 <&tegra_car TEGRA20_CLK_CLK_M>,
831 <&tegra_car TEGRA20_CLK_USBD>;
832 clock-names = "reg", "pll_u", "timer", "utmi-pads";
833 resets = <&tegra_car 59>, <&tegra_car 22>;
834 reset-names = "usb", "utmi-pads";
835 #phy-cells = <0>;
836 nvidia,hssync-start-delay = <9>;
837 nvidia,idle-wait-delay = <17>;
838 nvidia,elastic-limit = <16>;
839 nvidia,term-range-adj = <6>;
840 nvidia,xcvr-setup = <9>;
841 nvidia,xcvr-lsfslew = <2>;
842 nvidia,xcvr-lsrslew = <2>;
843 status = "disabled";
844 };
846 mmc@c8000000 {
847 compatible = "nvidia,tegra20-sdhci";
848 reg = <0xc8000000 0x200>;
849 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
850 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
851 clock-names = "sdhci";
852 resets = <&tegra_car 14>;
853 reset-names = "sdhci";
854 status = "disabled";
855 };
857 mmc@c8000200 {
858 compatible = "nvidia,tegra20-sdhci";
859 reg = <0xc8000200 0x200>;
860 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
862 clock-names = "sdhci";
863 resets = <&tegra_car 9>;
864 reset-names = "sdhci";
865 status = "disabled";
866 };
868 mmc@c8000400 {
869 compatible = "nvidia,tegra20-sdhci";
870 reg = <0xc8000400 0x200>;
871 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
873 clock-names = "sdhci";
874 resets = <&tegra_car 69>;
875 reset-names = "sdhci";
876 status = "disabled";
877 };
879 mmc@c8000600 {
880 compatible = "nvidia,tegra20-sdhci";
881 reg = <0xc8000600 0x200>;
882 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
883 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
884 clock-names = "sdhci";
885 resets = <&tegra_car 15>;
886 reset-names = "sdhci";
887 status = "disabled";
888 };
890 cpus {
891 #address-cells = <1>;
892 #size-cells = <0>;
894 cpu@0 {
895 device_type = "cpu";
896 compatible = "arm,cortex-a9";
897 reg = <0>;
898 clocks = <&tegra_car TEGRA20_CLK_CCLK>;
899 };
901 cpu@1 {
902 device_type = "cpu";
903 compatible = "arm,cortex-a9";
904 reg = <1>;
905 clocks = <&tegra_car TEGRA20_CLK_CCLK>;
906 };
907 };
909 pmu {
910 compatible = "arm,cortex-a9-pmu";
911 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
912 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
913 interrupt-affinity = <&{/cpus/cpu@0}>,
914 <&{/cpus/cpu@1}>;
915 };
916 };