| blob | a53b73ee93e90f38a6387b08848e3424002b95c2 |
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
2 //
3 // Device Tree Source for UniPhier Pro4 SoC
4 //
5 // Copyright (C) 2015-2016 Socionext Inc.
6 // Author: Masahiro Yamada <yamada.masahiro@socionext.com>
8 #include <dt-bindings/gpio/uniphier-gpio.h>
10 / {
11 compatible = "socionext,uniphier-pro4";
12 #address-cells = <1>;
13 #size-cells = <1>;
15 cpus {
16 #address-cells = <1>;
17 #size-cells = <0>;
19 cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a9";
22 reg = <0>;
23 enable-method = "psci";
24 next-level-cache = <&l2>;
25 };
27 cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a9";
30 reg = <1>;
31 enable-method = "psci";
32 next-level-cache = <&l2>;
33 };
34 };
36 psci {
37 compatible = "arm,psci-0.2";
38 method = "smc";
39 };
41 clocks {
42 refclk: ref {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <25000000>;
46 };
48 arm_timer_clk: arm-timer {
49 #clock-cells = <0>;
50 compatible = "fixed-clock";
51 clock-frequency = <50000000>;
52 };
53 };
55 soc {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60 interrupt-parent = <&intc>;
62 l2: cache-controller@500c0000 {
63 compatible = "socionext,uniphier-system-cache";
64 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
65 <0x506c0000 0x400>;
66 interrupts = <0 174 4>, <0 175 4>;
67 cache-unified;
68 cache-size = <(768 * 1024)>;
69 cache-sets = <256>;
70 cache-line-size = <128>;
71 cache-level = <2>;
72 };
74 spi0: spi@54006000 {
75 compatible = "socionext,uniphier-scssi";
76 status = "disabled";
77 reg = <0x54006000 0x100>;
78 #address-cells = <1>;
79 #size-cells = <0>;
80 interrupts = <0 39 4>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_spi0>;
83 clocks = <&peri_clk 11>;
84 resets = <&peri_rst 11>;
85 };
87 serial0: serial@54006800 {
88 compatible = "socionext,uniphier-uart";
89 status = "disabled";
90 reg = <0x54006800 0x40>;
91 interrupts = <0 33 4>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_uart0>;
94 clocks = <&peri_clk 0>;
95 resets = <&peri_rst 0>;
96 };
98 serial1: serial@54006900 {
99 compatible = "socionext,uniphier-uart";
100 status = "disabled";
101 reg = <0x54006900 0x40>;
102 interrupts = <0 35 4>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_uart1>;
105 clocks = <&peri_clk 1>;
106 resets = <&peri_rst 1>;
107 };
109 serial2: serial@54006a00 {
110 compatible = "socionext,uniphier-uart";
111 status = "disabled";
112 reg = <0x54006a00 0x40>;
113 interrupts = <0 37 4>;
114 pinctrl-names = "default";
115 pinctrl-0 = <&pinctrl_uart2>;
116 clocks = <&peri_clk 2>;
117 resets = <&peri_rst 2>;
118 };
120 serial3: serial@54006b00 {
121 compatible = "socionext,uniphier-uart";
122 status = "disabled";
123 reg = <0x54006b00 0x40>;
124 interrupts = <0 177 4>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_uart3>;
127 clocks = <&peri_clk 3>;
128 resets = <&peri_rst 3>;
129 };
131 gpio: gpio@55000000 {
132 compatible = "socionext,uniphier-gpio";
133 reg = <0x55000000 0x200>;
134 interrupt-parent = <&aidet>;
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 gpio-ranges = <&pinctrl 0 0 0>;
140 gpio-ranges-group-names = "gpio_range";
141 ngpios = <248>;
142 socionext,interrupt-ranges = <0 48 16>, <16 154 5>;
143 };
145 i2c0: i2c@58780000 {
146 compatible = "socionext,uniphier-fi2c";
147 status = "disabled";
148 reg = <0x58780000 0x80>;
149 #address-cells = <1>;
150 #size-cells = <0>;
151 interrupts = <0 41 4>;
152 pinctrl-names = "default";
153 pinctrl-0 = <&pinctrl_i2c0>;
154 clocks = <&peri_clk 4>;
155 resets = <&peri_rst 4>;
156 clock-frequency = <100000>;
157 };
159 i2c1: i2c@58781000 {
160 compatible = "socionext,uniphier-fi2c";
161 status = "disabled";
162 reg = <0x58781000 0x80>;
163 #address-cells = <1>;
164 #size-cells = <0>;
165 interrupts = <0 42 4>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_i2c1>;
168 clocks = <&peri_clk 5>;
169 resets = <&peri_rst 5>;
170 clock-frequency = <100000>;
171 };
173 i2c2: i2c@58782000 {
174 compatible = "socionext,uniphier-fi2c";
175 status = "disabled";
176 reg = <0x58782000 0x80>;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 interrupts = <0 43 4>;
180 pinctrl-names = "default";
181 pinctrl-0 = <&pinctrl_i2c2>;
182 clocks = <&peri_clk 6>;
183 resets = <&peri_rst 6>;
184 clock-frequency = <100000>;
185 };
187 i2c3: i2c@58783000 {
188 compatible = "socionext,uniphier-fi2c";
189 status = "disabled";
190 reg = <0x58783000 0x80>;
191 #address-cells = <1>;
192 #size-cells = <0>;
193 interrupts = <0 44 4>;
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_i2c3>;
196 clocks = <&peri_clk 7>;
197 resets = <&peri_rst 7>;
198 clock-frequency = <100000>;
199 };
201 /* i2c4 does not exist */
203 /* chip-internal connection for DMD */
204 i2c5: i2c@58785000 {
205 compatible = "socionext,uniphier-fi2c";
206 reg = <0x58785000 0x80>;
207 #address-cells = <1>;
208 #size-cells = <0>;
209 interrupts = <0 25 4>;
210 clocks = <&peri_clk 9>;
211 resets = <&peri_rst 9>;
212 clock-frequency = <400000>;
213 };
215 /* chip-internal connection for HDMI */
216 i2c6: i2c@58786000 {
217 compatible = "socionext,uniphier-fi2c";
218 reg = <0x58786000 0x80>;
219 #address-cells = <1>;
220 #size-cells = <0>;
221 interrupts = <0 26 4>;
222 clocks = <&peri_clk 10>;
223 resets = <&peri_rst 10>;
224 clock-frequency = <400000>;
225 };
227 system_bus: system-bus@58c00000 {
228 compatible = "socionext,uniphier-system-bus";
229 status = "disabled";
230 reg = <0x58c00000 0x400>;
231 #address-cells = <2>;
232 #size-cells = <1>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_system_bus>;
235 };
237 smpctrl@59801000 {
238 compatible = "socionext,uniphier-smpctrl";
239 reg = <0x59801000 0x400>;
240 };
242 mioctrl@59810000 {
243 compatible = "socionext,uniphier-pro4-mioctrl",
244 "simple-mfd", "syscon";
245 reg = <0x59810000 0x800>;
247 mio_clk: clock {
248 compatible = "socionext,uniphier-pro4-mio-clock";
249 #clock-cells = <1>;
250 };
252 mio_rst: reset {
253 compatible = "socionext,uniphier-pro4-mio-reset";
254 #reset-cells = <1>;
255 };
256 };
258 perictrl@59820000 {
259 compatible = "socionext,uniphier-pro4-perictrl",
260 "simple-mfd", "syscon";
261 reg = <0x59820000 0x200>;
263 peri_clk: clock {
264 compatible = "socionext,uniphier-pro4-peri-clock";
265 #clock-cells = <1>;
266 };
268 peri_rst: reset {
269 compatible = "socionext,uniphier-pro4-peri-reset";
270 #reset-cells = <1>;
271 };
272 };
274 dmac: dma-controller@5a000000 {
275 compatible = "socionext,uniphier-mio-dmac";
276 reg = <0x5a000000 0x1000>;
277 interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
278 <0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
279 clocks = <&mio_clk 7>;
280 resets = <&mio_rst 7>;
281 #dma-cells = <1>;
282 };
284 sd: mmc@5a400000 {
285 compatible = "socionext,uniphier-sd-v2.91";
286 status = "disabled";
287 reg = <0x5a400000 0x200>;
288 interrupts = <0 76 4>;
289 pinctrl-names = "default", "uhs";
290 pinctrl-0 = <&pinctrl_sd>;
291 pinctrl-1 = <&pinctrl_sd_uhs>;
292 clocks = <&mio_clk 0>;
293 reset-names = "host", "bridge";
294 resets = <&mio_rst 0>, <&mio_rst 3>;
295 dma-names = "rx-tx";
296 dmas = <&dmac 4>;
297 bus-width = <4>;
298 cap-sd-highspeed;
299 sd-uhs-sdr12;
300 sd-uhs-sdr25;
301 sd-uhs-sdr50;
302 };
304 emmc: mmc@5a500000 {
305 compatible = "socionext,uniphier-sd-v2.91";
306 status = "disabled";
307 reg = <0x5a500000 0x200>;
308 interrupts = <0 78 4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_emmc>;
311 clocks = <&mio_clk 1>;
312 reset-names = "host", "bridge", "hw";
313 resets = <&mio_rst 1>, <&mio_rst 4>, <&mio_rst 6>;
314 dma-names = "rx-tx";
315 dmas = <&dmac 5>;
316 bus-width = <8>;
317 cap-mmc-highspeed;
318 cap-mmc-hw-reset;
319 non-removable;
320 };
322 sd1: mmc@5a600000 {
323 compatible = "socionext,uniphier-sd-v2.91";
324 status = "disabled";
325 reg = <0x5a600000 0x200>;
326 interrupts = <0 85 4>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_sd1>;
329 clocks = <&mio_clk 2>;
330 reset-names = "host", "bridge";
331 resets = <&mio_rst 2>, <&mio_rst 5>;
332 dma-names = "rx-tx";
333 dmas = <&dmac 6>;
334 bus-width = <4>;
335 cap-sd-highspeed;
336 };
338 usb2: usb@5a800100 {
339 compatible = "socionext,uniphier-ehci", "generic-ehci";
340 status = "disabled";
341 reg = <0x5a800100 0x100>;
342 interrupts = <0 80 4>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&pinctrl_usb2>;
345 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
346 <&mio_clk 12>;
347 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
348 <&mio_rst 12>;
349 phy-names = "usb";
350 phys = <&usb_phy0>;
351 has-transaction-translator;
352 };
354 usb3: usb@5a810100 {
355 compatible = "socionext,uniphier-ehci", "generic-ehci";
356 status = "disabled";
357 reg = <0x5a810100 0x100>;
358 interrupts = <0 81 4>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_usb3>;
361 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
362 <&mio_clk 13>;
363 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
364 <&mio_rst 13>;
365 phy-names = "usb";
366 phys = <&usb_phy1>;
367 has-transaction-translator;
368 };
370 soc_glue: soc-glue@5f800000 {
371 compatible = "socionext,uniphier-pro4-soc-glue",
372 "simple-mfd", "syscon";
373 reg = <0x5f800000 0x2000>;
375 pinctrl: pinctrl {
376 compatible = "socionext,uniphier-pro4-pinctrl";
377 };
379 usb-phy {
380 compatible = "socionext,uniphier-pro4-usb2-phy";
381 #address-cells = <1>;
382 #size-cells = <0>;
384 usb_phy0: phy@0 {
385 reg = <0>;
386 #phy-cells = <0>;
387 };
389 usb_phy1: phy@1 {
390 reg = <1>;
391 #phy-cells = <0>;
392 };
394 usb_phy2: phy@2 {
395 reg = <2>;
396 #phy-cells = <0>;
397 vbus-supply = <&usb0_vbus>;
398 };
400 usb_phy3: phy@3 {
401 reg = <3>;
402 #phy-cells = <0>;
403 vbus-supply = <&usb1_vbus>;
404 };
405 };
406 };
408 soc-glue@5f900000 {
409 compatible = "socionext,uniphier-pro4-soc-glue-debug",
410 "simple-mfd";
411 #address-cells = <1>;
412 #size-cells = <1>;
413 ranges = <0 0x5f900000 0x2000>;
415 efuse@100 {
416 compatible = "socionext,uniphier-efuse";
417 reg = <0x100 0x28>;
418 };
420 efuse@130 {
421 compatible = "socionext,uniphier-efuse";
422 reg = <0x130 0x8>;
423 };
425 efuse@200 {
426 compatible = "socionext,uniphier-efuse";
427 reg = <0x200 0x14>;
428 };
429 };
431 xdmac: dma-controller@5fc10000 {
432 compatible = "socionext,uniphier-xdmac";
433 reg = <0x5fc10000 0x5300>;
434 interrupts = <0 188 4>;
435 dma-channels = <16>;
436 #dma-cells = <2>;
437 };
439 aidet: interrupt-controller@5fc20000 {
440 compatible = "socionext,uniphier-pro4-aidet";
441 reg = <0x5fc20000 0x200>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 };
446 timer@60000200 {
447 compatible = "arm,cortex-a9-global-timer";
448 reg = <0x60000200 0x20>;
449 interrupts = <1 11 0x304>;
450 clocks = <&arm_timer_clk>;
451 };
453 timer@60000600 {
454 compatible = "arm,cortex-a9-twd-timer";
455 reg = <0x60000600 0x20>;
456 interrupts = <1 13 0x304>;
457 clocks = <&arm_timer_clk>;
458 };
460 intc: interrupt-controller@60001000 {
461 compatible = "arm,cortex-a9-gic";
462 reg = <0x60001000 0x1000>,
463 <0x60000100 0x100>;
464 #interrupt-cells = <3>;
465 interrupt-controller;
466 };
468 sysctrl@61840000 {
469 compatible = "socionext,uniphier-pro4-sysctrl",
470 "simple-mfd", "syscon";
471 reg = <0x61840000 0x10000>;
473 sys_clk: clock {
474 compatible = "socionext,uniphier-pro4-clock";
475 #clock-cells = <1>;
476 };
478 sys_rst: reset {
479 compatible = "socionext,uniphier-pro4-reset";
480 #reset-cells = <1>;
481 };
482 };
484 eth: ethernet@65000000 {
485 compatible = "socionext,uniphier-pro4-ave4";
486 status = "disabled";
487 reg = <0x65000000 0x8500>;
488 interrupts = <0 66 4>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_ether_rgmii>;
491 clock-names = "gio", "ether", "ether-gb", "ether-phy";
492 clocks = <&sys_clk 12>, <&sys_clk 6>, <&sys_clk 7>,
493 <&sys_clk 10>;
494 reset-names = "gio", "ether";
495 resets = <&sys_rst 12>, <&sys_rst 6>;
496 phy-mode = "rgmii";
497 local-mac-address = [00 00 00 00 00 00];
498 socionext,syscon-phy-mode = <&soc_glue 0>;
500 mdio: mdio {
501 #address-cells = <1>;
502 #size-cells = <0>;
503 };
504 };
506 usb0: usb@65a00000 {
507 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
508 status = "disabled";
509 reg = <0x65a00000 0xcd00>;
510 interrupt-names = "host", "peripheral";
511 interrupts = <0 134 4>, <0 135 4>;
512 pinctrl-names = "default";
513 pinctrl-0 = <&pinctrl_usb0>;
514 clock-names = "ref", "bus_early", "suspend";
515 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
516 resets = <&usb0_rst 4>;
517 phys = <&usb_phy2>, <&usb0_ssphy>;
518 dr_mode = "host";
519 };
521 usb-glue@65b00000 {
522 compatible = "socionext,uniphier-pro4-dwc3-glue",
523 "simple-mfd";
524 #address-cells = <1>;
525 #size-cells = <1>;
526 ranges = <0 0x65b00000 0x100>;
528 usb0_vbus: regulator@0 {
529 compatible = "socionext,uniphier-pro4-usb3-regulator";
530 reg = <0 0x10>;
531 clock-names = "gio", "link";
532 clocks = <&sys_clk 12>, <&sys_clk 14>;
533 reset-names = "gio", "link";
534 resets = <&sys_rst 12>, <&sys_rst 14>;
535 };
537 usb0_ssphy: ss-phy@10 {
538 compatible = "socionext,uniphier-pro4-usb3-ssphy";
539 reg = <0x10 0x10>;
540 #phy-cells = <0>;
541 clock-names = "gio", "link";
542 clocks = <&sys_clk 12>, <&sys_clk 14>;
543 reset-names = "gio", "link";
544 resets = <&sys_rst 12>, <&sys_rst 14>;
545 vbus-supply = <&usb0_vbus>;
546 };
548 usb0_rst: reset@40 {
549 compatible = "socionext,uniphier-pro4-usb3-reset";
550 reg = <0x40 0x4>;
551 #reset-cells = <1>;
552 clock-names = "gio", "link";
553 clocks = <&sys_clk 12>, <&sys_clk 14>;
554 reset-names = "gio", "link";
555 resets = <&sys_rst 12>, <&sys_rst 14>;
556 };
557 };
559 usb1: usb@65c00000 {
560 compatible = "socionext,uniphier-dwc3", "snps,dwc3";
561 status = "disabled";
562 reg = <0x65c00000 0xcd00>;
563 interrupt-names = "host", "peripheral";
564 interrupts = <0 137 4>, <0 138 4>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_usb1>;
567 clock-names = "ref", "bus_early", "suspend";
568 clocks = <&sys_clk 12>, <&sys_clk 12>, <&sys_clk 12>;
569 resets = <&usb1_rst 4>;
570 phys = <&usb_phy3>;
571 dr_mode = "host";
572 };
574 usb-glue@65d00000 {
575 compatible = "socionext,uniphier-pro4-dwc3-glue",
576 "simple-mfd";
577 #address-cells = <1>;
578 #size-cells = <1>;
579 ranges = <0 0x65d00000 0x100>;
581 usb1_vbus: regulator@0 {
582 compatible = "socionext,uniphier-pro4-usb3-regulator";
583 reg = <0 0x10>;
584 clock-names = "gio", "link";
585 clocks = <&sys_clk 12>, <&sys_clk 15>;
586 reset-names = "gio", "link";
587 resets = <&sys_rst 12>, <&sys_rst 15>;
588 };
590 usb1_rst: reset@40 {
591 compatible = "socionext,uniphier-pro4-usb3-reset";
592 reg = <0x40 0x4>;
593 #reset-cells = <1>;
594 clock-names = "gio", "link";
595 clocks = <&sys_clk 12>, <&sys_clk 15>;
596 reset-names = "gio", "link";
597 resets = <&sys_rst 12>, <&sys_rst 15>;
598 };
599 };
601 nand: nand-controller@68000000 {
602 compatible = "socionext,uniphier-denali-nand-v5a";
603 status = "disabled";
604 reg-names = "nand_data", "denali_reg";
605 reg = <0x68000000 0x20>, <0x68100000 0x1000>;
606 #address-cells = <1>;
607 #size-cells = <0>;
608 interrupts = <0 65 4>;
609 pinctrl-names = "default";
610 pinctrl-0 = <&pinctrl_nand>;
611 clock-names = "nand", "nand_x", "ecc";
612 clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
613 reset-names = "nand", "reg";
614 resets = <&sys_rst 2>, <&sys_rst 2>;
615 };
616 };
617 };
619 #include "uniphier-pinctrl.dtsi"