WIP FPC-III support
[linux/fpc-iii.git] / arch / arm / include / debug / brcmstb.S
blob0ff32ffc610c72a97adaa6f6ab43b510302d052f
1 /*
2  * Copyright (C) 2016 Broadcom
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation version 2.
7  *
8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9  * kind, whether express or implied; without even the implied warranty
10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 #include <linux/serial_reg.h>
14 #include <asm/cputype.h>
16 /* Physical register offset and virtual register offset */
17 #define REG_PHYS_BASE           0xf0000000
18 #define REG_PHYS_BASE_V7        0x08000000
19 #define REG_VIRT_BASE           0xfc000000
20 #define REG_PHYS_ADDR(x)        ((x) + REG_PHYS_BASE)
21 #define REG_PHYS_ADDR_V7(x)     ((x) + REG_PHYS_BASE_V7)
23 /* Product id can be read from here */
24 #define SUN_TOP_CTRL_BASE       REG_PHYS_ADDR(0x404000)
25 #define SUN_TOP_CTRL_BASE_V7    REG_PHYS_ADDR_V7(0x404000)
27 #define UARTA_3390              REG_PHYS_ADDR(0x40a900)
28 #define UARTA_7250              REG_PHYS_ADDR(0x40b400)
29 #define UARTA_7255              REG_PHYS_ADDR(0x40c000)
30 #define UARTA_7260              UARTA_7255
31 #define UARTA_7268              UARTA_7255
32 #define UARTA_7271              UARTA_7268
33 #define UARTA_7278              REG_PHYS_ADDR_V7(0x40c000)
34 #define UARTA_7216              UARTA_7278
35 #define UARTA_72164             UARTA_7278
36 #define UARTA_72165             UARTA_7278
37 #define UARTA_7364              REG_PHYS_ADDR(0x40b000)
38 #define UARTA_7366              UARTA_7364
39 #define UARTA_74371             REG_PHYS_ADDR(0x406b00)
40 #define UARTA_7439              REG_PHYS_ADDR(0x40a900)
41 #define UARTA_7445              REG_PHYS_ADDR(0x40ab00)
43 #define UART_SHIFT              2
45 #define checkuart(rp, rv, family_id, family) \
46                 /* Load family id */ \
47                 ldr     rp, =family_id ; \
48                 /* Compare SUN_TOP_CTRL value against it */ \
49                 cmp     rp, rv ; \
50                 /* Passed test, load address */ \
51                 ldreq   rp, =UARTA_##family ; \
52                 /* Jump to save UART address */ \
53                 beq     91f
55                 .macro  addruart, rp, rv, tmp
56                 adr     \rp, 99f                @ actual addr of 99f
57                 ldr     \rv, [\rp]              @ linked addr is stored there
58                 sub     \rv, \rv, \rp           @ offset between the two
59                 ldr     \rp, [\rp, #4]          @ linked brcmstb_uart_config
60                 sub     \tmp, \rp, \rv          @ actual brcmstb_uart_config
61                 ldr     \rp, [\tmp]             @ Load brcmstb_uart_config
62                 cmp     \rp, #1                 @ needs initialization?
63                 bne     100f                    @ no; go load the addresses
64                 mov     \rv, #0                 @ yes; record init is done
65                 str     \rv, [\tmp]
67                 /* Check for V7 memory map if B53 */
68                 mrc     p15, 0, \rv, c0, c0, 0  @ get Main ID register
69                 ldr     \rp, =ARM_CPU_PART_MASK
70                 and     \rv, \rv, \rp
71                 ldr     \rp, =ARM_CPU_PART_BRAHMA_B53   @ check for B53 CPU
72                 cmp     \rv, \rp
73                 bne     10f
75                 /* if PERIPHBASE doesn't overlap REG_PHYS_BASE use V7 map */
76                 mrc     p15, 1, \rv, c15, c3, 0 @ get PERIPHBASE from CBAR
77                 ands    \rv, \rv, #REG_PHYS_BASE
78                 ldreq   \rp, =SUN_TOP_CTRL_BASE_V7
80                 /* Check SUN_TOP_CTRL base */
81 10:             ldrne   \rp, =SUN_TOP_CTRL_BASE @ load SUN_TOP_CTRL PA
82                 ldr     \rv, [\rp, #0]          @ get register contents
83 ARM_BE8(        rev     \rv, \rv )
84                 and     \rv, \rv, #0xffffff00   @ strip revision bits [7:0]
86                 /* Chip specific detection starts here */
87 20:             checkuart(\rp, \rv, 0x33900000, 3390)
88 21:             checkuart(\rp, \rv, 0x72160000, 7216)
89 22:             checkuart(\rp, \rv, 0x07216400, 72164)
90 23:             checkuart(\rp, \rv, 0x07216500, 72165)
91 24:             checkuart(\rp, \rv, 0x72500000, 7250)
92 25:             checkuart(\rp, \rv, 0x72550000, 7255)
93 26:             checkuart(\rp, \rv, 0x72600000, 7260)
94 27:             checkuart(\rp, \rv, 0x72680000, 7268)
95 28:             checkuart(\rp, \rv, 0x72710000, 7271)
96 29:             checkuart(\rp, \rv, 0x72780000, 7278)
97 30:             checkuart(\rp, \rv, 0x73640000, 7364)
98 31:             checkuart(\rp, \rv, 0x73660000, 7366)
99 32:             checkuart(\rp, \rv, 0x07437100, 74371)
100 33:             checkuart(\rp, \rv, 0x74390000, 7439)
101 34:             checkuart(\rp, \rv, 0x74450000, 7445)
103                 /* No valid UART found */
104 90:             mov     \rp, #0
105                 /* fall through */
107                 /* Record whichever UART we chose */
108 91:             str     \rp, [\tmp, #4]         @ Store in brcmstb_uart_phys
109                 cmp     \rp, #0                 @ Valid UART address?
110                 bne     92f                     @ Yes, go process it
111                 str     \rp, [\tmp, #8]         @ Store 0 in brcmstb_uart_virt
112                 b       100f                    @ Done
113 92:             and     \rv, \rp, #0xffffff     @ offset within 16MB section
114                 add     \rv, \rv, #REG_VIRT_BASE
115                 str     \rv, [\tmp, #8]         @ Store in brcmstb_uart_virt
116                 b       100f
118                 .align
119 99:             .word   .
120                 .word   brcmstb_uart_config
121                 .ltorg
123                 /* Load previously selected UART address */
124 100:            ldr     \rp, [\tmp, #4]         @ Load brcmstb_uart_phys
125                 ldr     \rv, [\tmp, #8]         @ Load brcmstb_uart_virt
126                 .endm
128                 .macro  store, rd, rx:vararg
129 ARM_BE8(        rev     \rd, \rd )
130                 str     \rd, \rx
131                 .endm
133                 .macro  load, rd, rx:vararg
134                 ldr     \rd, \rx
135 ARM_BE8(        rev     \rd, \rd )
136                 .endm
138                 .macro  senduart,rd,rx
139                 store   \rd, [\rx, #UART_TX << UART_SHIFT]
140                 .endm
142                 .macro  busyuart,rd,rx
143 1002:           load    \rd, [\rx, #UART_LSR << UART_SHIFT]
144                 and     \rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
145                 teq     \rd, #UART_LSR_TEMT | UART_LSR_THRE
146                 bne     1002b
147                 .endm
149                 .macro  waituarttxrdy,rd,rx
150                 .endm
152                 .macro  waituartcts,rd,rx
153                 .endm
156  * Storage for the state maintained by the macros above.
158  * In the kernel proper, this data is located in arch/arm/mach-bcm/brcmstb.c.
159  * That's because this header is included from multiple files, and we only
160  * want a single copy of the data. In particular, the UART probing code above
161  * assumes it's running using physical addresses. This is true when this file
162  * is included from head.o, but not when included from debug.o. So we need
163  * to share the probe results between the two copies, rather than having
164  * to re-run the probing again later.
166  * In the decompressor, we put the symbol/storage right here, since common.c
167  * isn't included in the decompressor build. This symbol gets put in .text
168  * even though it's really data, since .data is discarded from the
169  * decompressor. Luckily, .text is writeable in the decompressor, unless
170  * CONFIG_ZBOOT_ROM. That dependency is handled in arch/arm/Kconfig.debug.
171  */
172 #if defined(ZIMAGE)
173 brcmstb_uart_config:
174         /* Debug UART initialization required */
175         .word 1
176         /* Debug UART physical address */
177         .word 0
178         /* Debug UART virtual address */
179         .word 0
180 #endif