arch/arm/mach-s3c/regs-adc.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * Copyright (c) 2004 Shannon Holland <holland@loser.net>
   4  *
   5  * S3C2410 ADC registers
   6  */
   7
   8 #ifndef __ASM_ARCH_REGS_ADC_H
   9 #define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
  10
  11 #define S3C2410_ADCREG(x) (x)
  12
  13 #define S3C2410_ADCCON     S3C2410_ADCREG(0x00)
  14 #define S3C2410_ADCTSC     S3C2410_ADCREG(0x04)
  15 #define S3C2410_ADCDLY     S3C2410_ADCREG(0x08)
  16 #define S3C2410_ADCDAT0    S3C2410_ADCREG(0x0C)
  17 #define S3C2410_ADCDAT1    S3C2410_ADCREG(0x10)
  18 #define S3C64XX_ADCUPDN         S3C2410_ADCREG(0x14)
  19 #define S3C2443_ADCMUX          S3C2410_ADCREG(0x18)
  20 #define S3C64XX_ADCCLRINT       S3C2410_ADCREG(0x18)
  21 #define S5P_ADCMUX              S3C2410_ADCREG(0x1C)
  22 #define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
  23
  24
  25 /* ADCCON Register Bits */
  26 #define S3C64XX_ADCCON_RESSEL           (1<<16)
  27 #define S3C2410_ADCCON_ECFLG            (1<<15)
  28 #define S3C2410_ADCCON_PRSCEN           (1<<14)
  29 #define S3C2410_ADCCON_PRSCVL(x)        (((x)&0xFF)<<6)
  30 #define S3C2410_ADCCON_PRSCVLMASK       (0xFF<<6)
  31 #define S3C2410_ADCCON_SELMUX(x)        (((x)&0x7)<<3)
  32 #define S3C2410_ADCCON_MUXMASK          (0x7<<3)
  33 #define S3C2416_ADCCON_RESSEL           (1 << 3)
  34 #define S3C2410_ADCCON_STDBM            (1<<2)
  35 #define S3C2410_ADCCON_READ_START       (1<<1)
  36 #define S3C2410_ADCCON_ENABLE_START     (1<<0)
  37 #define S3C2410_ADCCON_STARTMASK        (0x3<<0)
  38
  39
  40 /* ADCTSC Register Bits */
  41 #define S3C2443_ADCTSC_UD_SEN           (1 << 8)
  42 #define S3C2410_ADCTSC_YM_SEN           (1<<7)
  43 #define S3C2410_ADCTSC_YP_SEN           (1<<6)
  44 #define S3C2410_ADCTSC_XM_SEN           (1<<5)
  45 #define S3C2410_ADCTSC_XP_SEN           (1<<4)
  46 #define S3C2410_ADCTSC_PULL_UP_DISABLE  (1<<3)
  47 #define S3C2410_ADCTSC_AUTO_PST         (1<<2)
  48 #define S3C2410_ADCTSC_XY_PST(x)        (((x)&0x3)<<0)
  49
  50 /* ADCDAT0 Bits */
  51 #define S3C2410_ADCDAT0_UPDOWN          (1<<15)
  52 #define S3C2410_ADCDAT0_AUTO_PST        (1<<14)
  53 #define S3C2410_ADCDAT0_XY_PST          (0x3<<12)
  54 #define S3C2410_ADCDAT0_XPDATA_MASK     (0x03FF)
  55
  56 /* ADCDAT1 Bits */
  57 #define S3C2410_ADCDAT1_UPDOWN          (1<<15)
  58 #define S3C2410_ADCDAT1_AUTO_PST        (1<<14)
  59 #define S3C2410_ADCDAT1_XY_PST          (0x3<<12)
  60 #define S3C2410_ADCDAT1_YPDATA_MASK     (0x03FF)
  61
  62 #endif /* __ASM_ARCH_REGS_ADC_H */
  63
  64