| blob | 02692fbe2db5c599cf5945c42fb217b712d0b212 |
1 # SPDX-License-Identifier: GPL-2.0
2 comment "Processor Type"
4 # Select CPU types depending on the architecture selected. This selects
5 # which CPUs we support in the kernel image, and the compiler instruction
6 # optimiser behaviour.
8 # ARM7TDMI
9 config CPU_ARM7TDMI
10 bool
11 depends on !MMU
12 select CPU_32v4T
13 select CPU_ABRT_LV4T
14 select CPU_CACHE_V4
15 select CPU_PABRT_LEGACY
16 help
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
20 Say Y if you want support for the ARM7TDMI processor.
21 Otherwise, say N.
23 # ARM720T
24 config CPU_ARM720T
25 bool
26 select CPU_32v4T
27 select CPU_ABRT_LV4T
28 select CPU_CACHE_V4
29 select CPU_CACHE_VIVT
30 select CPU_COPY_V4WT if MMU
31 select CPU_CP15_MMU
32 select CPU_PABRT_LEGACY
33 select CPU_THUMB_CAPABLE
34 select CPU_TLB_V4WT if MMU
35 help
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
37 MMU built around an ARM7TDMI core.
39 Say Y if you want support for the ARM720T processor.
40 Otherwise, say N.
42 # ARM740T
43 config CPU_ARM740T
44 bool
45 depends on !MMU
46 select CPU_32v4T
47 select CPU_ABRT_LV4T
48 select CPU_CACHE_V4
49 select CPU_CP15_MPU
50 select CPU_PABRT_LEGACY
51 select CPU_THUMB_CAPABLE
52 help
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
55 an ARM7TDMI core.
57 Say Y if you want support for the ARM740T processor.
58 Otherwise, say N.
60 # ARM9TDMI
61 config CPU_ARM9TDMI
62 bool
63 depends on !MMU
64 select CPU_32v4T
65 select CPU_ABRT_NOMMU
66 select CPU_CACHE_V4
67 select CPU_PABRT_LEGACY
68 help
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
72 Say Y if you want support for the ARM9TDMI processor.
73 Otherwise, say N.
75 # ARM920T
76 config CPU_ARM920T
77 bool
78 select CPU_32v4T
79 select CPU_ABRT_EV4T
80 select CPU_CACHE_V4WT
81 select CPU_CACHE_VIVT
82 select CPU_COPY_V4WB if MMU
83 select CPU_CP15_MMU
84 select CPU_PABRT_LEGACY
85 select CPU_THUMB_CAPABLE
86 select CPU_TLB_V4WBI if MMU
87 help
88 The ARM920T is licensed to be produced by numerous vendors,
89 and is used in the Cirrus EP93xx and the Samsung S3C2410.
91 Say Y if you want support for the ARM920T processor.
92 Otherwise, say N.
94 # ARM922T
95 config CPU_ARM922T
96 bool
97 select CPU_32v4T
98 select CPU_ABRT_EV4T
99 select CPU_CACHE_V4WT
100 select CPU_CACHE_VIVT
101 select CPU_COPY_V4WB if MMU
102 select CPU_CP15_MMU
103 select CPU_PABRT_LEGACY
104 select CPU_THUMB_CAPABLE
105 select CPU_TLB_V4WBI if MMU
106 help
107 The ARM922T is a version of the ARM920T, but with smaller
108 instruction and data caches. It is used in Altera's
109 Excalibur XA device family and the ARM Integrator.
111 Say Y if you want support for the ARM922T processor.
112 Otherwise, say N.
114 # ARM925T
115 config CPU_ARM925T
116 bool
117 select CPU_32v4T
118 select CPU_ABRT_EV4T
119 select CPU_CACHE_V4WT
120 select CPU_CACHE_VIVT
121 select CPU_COPY_V4WB if MMU
122 select CPU_CP15_MMU
123 select CPU_PABRT_LEGACY
124 select CPU_THUMB_CAPABLE
125 select CPU_TLB_V4WBI if MMU
126 help
127 The ARM925T is a mix between the ARM920T and ARM926T, but with
128 different instruction and data caches. It is used in TI's OMAP
129 device family.
131 Say Y if you want support for the ARM925T processor.
132 Otherwise, say N.
134 # ARM926T
135 config CPU_ARM926T
136 bool
137 select CPU_32v5
138 select CPU_ABRT_EV5TJ
139 select CPU_CACHE_VIVT
140 select CPU_COPY_V4WB if MMU
141 select CPU_CP15_MMU
142 select CPU_PABRT_LEGACY
143 select CPU_THUMB_CAPABLE
144 select CPU_TLB_V4WBI if MMU
145 help
146 This is a variant of the ARM920. It has slightly different
147 instruction sequences for cache and TLB operations. Curiously,
148 there is no documentation on it at the ARM corporate website.
150 Say Y if you want support for the ARM926T processor.
151 Otherwise, say N.
153 # FA526
154 config CPU_FA526
155 bool
156 select CPU_32v4
157 select CPU_ABRT_EV4
158 select CPU_CACHE_FA
159 select CPU_CACHE_VIVT
160 select CPU_COPY_FA if MMU
161 select CPU_CP15_MMU
162 select CPU_PABRT_LEGACY
163 select CPU_TLB_FA if MMU
164 help
165 The FA526 is a version of the ARMv4 compatible processor with
166 Branch Target Buffer, Unified TLB and cache line size 16.
168 Say Y if you want support for the FA526 processor.
169 Otherwise, say N.
171 # ARM940T
172 config CPU_ARM940T
173 bool
174 depends on !MMU
175 select CPU_32v4T
176 select CPU_ABRT_NOMMU
177 select CPU_CACHE_VIVT
178 select CPU_CP15_MPU
179 select CPU_PABRT_LEGACY
180 select CPU_THUMB_CAPABLE
181 help
182 ARM940T is a member of the ARM9TDMI family of general-
183 purpose microprocessors with MPU and separate 4KB
184 instruction and 4KB data cases, each with a 4-word line
185 length.
187 Say Y if you want support for the ARM940T processor.
188 Otherwise, say N.
190 # ARM946E-S
191 config CPU_ARM946E
192 bool
193 depends on !MMU
194 select CPU_32v5
195 select CPU_ABRT_NOMMU
196 select CPU_CACHE_VIVT
197 select CPU_CP15_MPU
198 select CPU_PABRT_LEGACY
199 select CPU_THUMB_CAPABLE
200 help
201 ARM946E-S is a member of the ARM9E-S family of high-
202 performance, 32-bit system-on-chip processor solutions.
203 The TCM and ARMv5TE 32-bit instruction set is supported.
205 Say Y if you want support for the ARM946E-S processor.
206 Otherwise, say N.
208 # ARM1020 - needs validating
209 config CPU_ARM1020
210 bool
211 select CPU_32v5
212 select CPU_ABRT_EV4T
213 select CPU_CACHE_V4WT
214 select CPU_CACHE_VIVT
215 select CPU_COPY_V4WB if MMU
216 select CPU_CP15_MMU
217 select CPU_PABRT_LEGACY
218 select CPU_THUMB_CAPABLE
219 select CPU_TLB_V4WBI if MMU
220 help
221 The ARM1020 is the 32K cached version of the ARM10 processor,
222 with an addition of a floating-point unit.
224 Say Y if you want support for the ARM1020 processor.
225 Otherwise, say N.
227 # ARM1020E - needs validating
228 config CPU_ARM1020E
229 bool
230 depends on n
231 select CPU_32v5
232 select CPU_ABRT_EV4T
233 select CPU_CACHE_V4WT
234 select CPU_CACHE_VIVT
235 select CPU_COPY_V4WB if MMU
236 select CPU_CP15_MMU
237 select CPU_PABRT_LEGACY
238 select CPU_THUMB_CAPABLE
239 select CPU_TLB_V4WBI if MMU
241 # ARM1022E
242 config CPU_ARM1022
243 bool
244 select CPU_32v5
245 select CPU_ABRT_EV4T
246 select CPU_CACHE_VIVT
247 select CPU_COPY_V4WB if MMU # can probably do better
248 select CPU_CP15_MMU
249 select CPU_PABRT_LEGACY
250 select CPU_THUMB_CAPABLE
251 select CPU_TLB_V4WBI if MMU
252 help
253 The ARM1022E is an implementation of the ARMv5TE architecture
254 based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
255 embedded trace macrocell, and a floating-point unit.
257 Say Y if you want support for the ARM1022E processor.
258 Otherwise, say N.
260 # ARM1026EJ-S
261 config CPU_ARM1026
262 bool
263 select CPU_32v5
264 select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
265 select CPU_CACHE_VIVT
266 select CPU_COPY_V4WB if MMU # can probably do better
267 select CPU_CP15_MMU
268 select CPU_PABRT_LEGACY
269 select CPU_THUMB_CAPABLE
270 select CPU_TLB_V4WBI if MMU
271 help
272 The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
273 based upon the ARM10 integer core.
275 Say Y if you want support for the ARM1026EJ-S processor.
276 Otherwise, say N.
278 # SA110
279 config CPU_SA110
280 bool
281 select CPU_32v3 if ARCH_RPC
282 select CPU_32v4 if !ARCH_RPC
283 select CPU_ABRT_EV4
284 select CPU_CACHE_V4WB
285 select CPU_CACHE_VIVT
286 select CPU_COPY_V4WB if MMU
287 select CPU_CP15_MMU
288 select CPU_PABRT_LEGACY
289 select CPU_TLB_V4WB if MMU
290 help
291 The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
292 is available at five speeds ranging from 100 MHz to 233 MHz.
293 More information is available at
294 <http://developer.intel.com/design/strong/sa110.htm>.
296 Say Y if you want support for the SA-110 processor.
297 Otherwise, say N.
299 # SA1100
300 config CPU_SA1100
301 bool
302 select CPU_32v4
303 select CPU_ABRT_EV4
304 select CPU_CACHE_V4WB
305 select CPU_CACHE_VIVT
306 select CPU_CP15_MMU
307 select CPU_PABRT_LEGACY
308 select CPU_TLB_V4WB if MMU
310 # XScale
311 config CPU_XSCALE
312 bool
313 select CPU_32v5
314 select CPU_ABRT_EV5T
315 select CPU_CACHE_VIVT
316 select CPU_CP15_MMU
317 select CPU_PABRT_LEGACY
318 select CPU_THUMB_CAPABLE
319 select CPU_TLB_V4WBI if MMU
321 # XScale Core Version 3
322 config CPU_XSC3
323 bool
324 select CPU_32v5
325 select CPU_ABRT_EV5T
326 select CPU_CACHE_VIVT
327 select CPU_CP15_MMU
328 select CPU_PABRT_LEGACY
329 select CPU_THUMB_CAPABLE
330 select CPU_TLB_V4WBI if MMU
331 select IO_36
333 # Marvell PJ1 (Mohawk)
334 config CPU_MOHAWK
335 bool
336 select CPU_32v5
337 select CPU_ABRT_EV5T
338 select CPU_CACHE_VIVT
339 select CPU_COPY_V4WB if MMU
340 select CPU_CP15_MMU
341 select CPU_PABRT_LEGACY
342 select CPU_THUMB_CAPABLE
343 select CPU_TLB_V4WBI if MMU
345 # Feroceon
346 config CPU_FEROCEON
347 bool
348 select CPU_32v5
349 select CPU_ABRT_EV5T
350 select CPU_CACHE_VIVT
351 select CPU_COPY_FEROCEON if MMU
352 select CPU_CP15_MMU
353 select CPU_PABRT_LEGACY
354 select CPU_THUMB_CAPABLE
355 select CPU_TLB_FEROCEON if MMU
357 config CPU_FEROCEON_OLD_ID
358 bool "Accept early Feroceon cores with an ARM926 ID"
359 depends on CPU_FEROCEON && !CPU_ARM926T
360 default y
361 help
362 This enables the usage of some old Feroceon cores
363 for which the CPU ID is equal to the ARM926 ID.
364 Relevant for Feroceon-1850 and early Feroceon-2850.
366 # Marvell PJ4
367 config CPU_PJ4
368 bool
369 select ARM_THUMBEE
370 select CPU_V7
372 config CPU_PJ4B
373 bool
374 select CPU_V7
376 # ARMv6
377 config CPU_V6
378 bool
379 select CPU_32v6
380 select CPU_ABRT_EV6
381 select CPU_CACHE_V6
382 select CPU_CACHE_VIPT
383 select CPU_COPY_V6 if MMU
384 select CPU_CP15_MMU
385 select CPU_HAS_ASID if MMU
386 select CPU_PABRT_V6
387 select CPU_THUMB_CAPABLE
388 select CPU_TLB_V6 if MMU
390 # ARMv6k
391 config CPU_V6K
392 bool
393 select CPU_32v6
394 select CPU_32v6K
395 select CPU_ABRT_EV6
396 select CPU_CACHE_V6
397 select CPU_CACHE_VIPT
398 select CPU_COPY_V6 if MMU
399 select CPU_CP15_MMU
400 select CPU_HAS_ASID if MMU
401 select CPU_PABRT_V6
402 select CPU_THUMB_CAPABLE
403 select CPU_TLB_V6 if MMU
405 # ARMv7
406 config CPU_V7
407 bool
408 select CPU_32v6K
409 select CPU_32v7
410 select CPU_ABRT_EV7
411 select CPU_CACHE_V7
412 select CPU_CACHE_VIPT
413 select CPU_COPY_V6 if MMU
414 select CPU_CP15_MMU if MMU
415 select CPU_CP15_MPU if !MMU
416 select CPU_HAS_ASID if MMU
417 select CPU_PABRT_V7
418 select CPU_SPECTRE if MMU
419 select CPU_THUMB_CAPABLE
420 select CPU_TLB_V7 if MMU
422 # ARMv7M
423 config CPU_V7M
424 bool
425 select CPU_32v7M
426 select CPU_ABRT_NOMMU
427 select CPU_CACHE_V7M
428 select CPU_CACHE_NOP
429 select CPU_PABRT_LEGACY
430 select CPU_THUMBONLY
432 config CPU_THUMBONLY
433 bool
434 select CPU_THUMB_CAPABLE
435 # There are no CPUs available with MMU that don't implement an ARM ISA:
436 depends on !MMU
437 help
438 Select this if your CPU doesn't support the 32 bit ARM instructions.
440 config CPU_THUMB_CAPABLE
441 bool
442 help
443 Select this if your CPU can support Thumb mode.
445 # Figure out what processor architecture version we should be using.
446 # This defines the compiler instruction set which depends on the machine type.
447 config CPU_32v3
448 bool
449 select CPU_USE_DOMAINS if MMU
450 select NEED_KUSER_HELPERS
451 select TLS_REG_EMUL if SMP || !MMU
452 select CPU_NO_EFFICIENT_FFS
454 config CPU_32v4
455 bool
456 select CPU_USE_DOMAINS if MMU
457 select NEED_KUSER_HELPERS
458 select TLS_REG_EMUL if SMP || !MMU
459 select CPU_NO_EFFICIENT_FFS
461 config CPU_32v4T
462 bool
463 select CPU_USE_DOMAINS if MMU
464 select NEED_KUSER_HELPERS
465 select TLS_REG_EMUL if SMP || !MMU
466 select CPU_NO_EFFICIENT_FFS
468 config CPU_32v5
469 bool
470 select CPU_USE_DOMAINS if MMU
471 select NEED_KUSER_HELPERS
472 select TLS_REG_EMUL if SMP || !MMU
474 config CPU_32v6
475 bool
476 select TLS_REG_EMUL if !CPU_32v6K && !MMU
478 config CPU_32v6K
479 bool
481 config CPU_32v7
482 bool
484 config CPU_32v7M
485 bool
487 # The abort model
488 config CPU_ABRT_NOMMU
489 bool
491 config CPU_ABRT_EV4
492 bool
494 config CPU_ABRT_EV4T
495 bool
497 config CPU_ABRT_LV4T
498 bool
500 config CPU_ABRT_EV5T
501 bool
503 config CPU_ABRT_EV5TJ
504 bool
506 config CPU_ABRT_EV6
507 bool
509 config CPU_ABRT_EV7
510 bool
512 config CPU_PABRT_LEGACY
513 bool
515 config CPU_PABRT_V6
516 bool
518 config CPU_PABRT_V7
519 bool
521 # The cache model
522 config CPU_CACHE_V4
523 bool
525 config CPU_CACHE_V4WT
526 bool
528 config CPU_CACHE_V4WB
529 bool
531 config CPU_CACHE_V6
532 bool
534 config CPU_CACHE_V7
535 bool
537 config CPU_CACHE_NOP
538 bool
540 config CPU_CACHE_VIVT
541 bool
543 config CPU_CACHE_VIPT
544 bool
546 config CPU_CACHE_FA
547 bool
549 config CPU_CACHE_V7M
550 bool
552 if MMU
553 # The copy-page model
554 config CPU_COPY_V4WT
555 bool
557 config CPU_COPY_V4WB
558 bool
560 config CPU_COPY_FEROCEON
561 bool
563 config CPU_COPY_FA
564 bool
566 config CPU_COPY_V6
567 bool
569 # This selects the TLB model
570 config CPU_TLB_V4WT
571 bool
572 help
573 ARM Architecture Version 4 TLB with writethrough cache.
575 config CPU_TLB_V4WB
576 bool
577 help
578 ARM Architecture Version 4 TLB with writeback cache.
580 config CPU_TLB_V4WBI
581 bool
582 help
583 ARM Architecture Version 4 TLB with writeback cache and invalidate
584 instruction cache entry.
586 config CPU_TLB_FEROCEON
587 bool
588 help
589 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
591 config CPU_TLB_FA
592 bool
593 help
594 Faraday ARM FA526 architecture, unified TLB with writeback cache
595 and invalidate instruction cache entry. Branch target buffer is
596 also supported.
598 config CPU_TLB_V6
599 bool
601 config CPU_TLB_V7
602 bool
604 config VERIFY_PERMISSION_FAULT
605 bool
606 endif
608 config CPU_HAS_ASID
609 bool
610 help
611 This indicates whether the CPU has the ASID register; used to
612 tag TLB and possibly cache entries.
614 config CPU_CP15
615 bool
616 help
617 Processor has the CP15 register.
619 config CPU_CP15_MMU
620 bool
621 select CPU_CP15
622 help
623 Processor has the CP15 register, which has MMU related registers.
625 config CPU_CP15_MPU
626 bool
627 select CPU_CP15
628 help
629 Processor has the CP15 register, which has MPU related registers.
631 config CPU_USE_DOMAINS
632 bool
633 help
634 This option enables or disables the use of domain switching
635 via the set_fs() function.
637 config CPU_V7M_NUM_IRQ
638 int "Number of external interrupts connected to the NVIC"
639 depends on CPU_V7M
640 default 90 if ARCH_STM32
641 default 38 if ARCH_EFM32
642 default 112 if SOC_VF610
643 default 240
644 help
645 This option indicates the number of interrupts connected to the NVIC.
646 The value can be larger than the real number of interrupts supported
647 by the system, but must not be lower.
648 The default value is 240, corresponding to the maximum number of
649 interrupts supported by the NVIC on Cortex-M family.
651 If unsure, keep default value.
653 #
654 # CPU supports 36-bit I/O
655 #
656 config IO_36
657 bool
659 comment "Processor Features"
661 config ARM_LPAE
662 bool "Support for the Large Physical Address Extension"
663 depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
664 !CPU_32v4 && !CPU_32v3
665 select PHYS_ADDR_T_64BIT
666 select SWIOTLB
667 help
668 Say Y if you have an ARMv7 processor supporting the LPAE page
669 table format and you would like to access memory beyond the
670 4GB limit. The resulting kernel image will not run on
671 processors without the LPA extension.
673 If unsure, say N.
675 config ARM_PV_FIXUP
676 def_bool y
677 depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
679 config ARM_THUMB
680 bool "Support Thumb user binaries" if !CPU_THUMBONLY && EXPERT
681 depends on CPU_THUMB_CAPABLE
682 default y
683 help
684 Say Y if you want to include kernel support for running user space
685 Thumb binaries.
687 The Thumb instruction set is a compressed form of the standard ARM
688 instruction set resulting in smaller binaries at the expense of
689 slightly less efficient code.
691 If this option is disabled, and you run userspace that switches to
692 Thumb mode, signal handling will not work correctly, resulting in
693 segmentation faults or illegal instruction aborts.
695 If you don't know what this all is, saying Y is a safe choice.
697 config ARM_THUMBEE
698 bool "Enable ThumbEE CPU extension"
699 depends on CPU_V7
700 help
701 Say Y here if you have a CPU with the ThumbEE extension and code to
702 make use of it. Say N for code that can run on CPUs without ThumbEE.
704 config ARM_VIRT_EXT
705 bool
706 default y if CPU_V7
707 help
708 Enable the kernel to make use of the ARM Virtualization
709 Extensions to install hypervisors without run-time firmware
710 assistance.
712 A compliant bootloader is required in order to make maximum
713 use of this feature. Refer to Documentation/arm/booting.rst for
714 details.
716 config SWP_EMULATE
717 bool "Emulate SWP/SWPB instructions" if !SMP
718 depends on CPU_V7
719 default y if SMP
720 select HAVE_PROC_CPU if PROC_FS
721 help
722 ARMv6 architecture deprecates use of the SWP/SWPB instructions.
723 ARMv7 multiprocessing extensions introduce the ability to disable
724 these instructions, triggering an undefined instruction exception
725 when executed. Say Y here to enable software emulation of these
726 instructions for userspace (not kernel) using LDREX/STREX.
727 Also creates /proc/cpu/swp_emulation for statistics.
729 In some older versions of glibc [<=2.8] SWP is used during futex
730 trylock() operations with the assumption that the code will not
731 be preempted. This invalid assumption may be more likely to fail
732 with SWP emulation enabled, leading to deadlock of the user
733 application.
735 NOTE: when accessing uncached shared regions, LDREX/STREX rely
736 on an external transaction monitoring block called a global
737 monitor to maintain update atomicity. If your system does not
738 implement a global monitor, this option can cause programs that
739 perform SWP operations to uncached memory to deadlock.
741 If unsure, say Y.
743 config CPU_BIG_ENDIAN
744 bool "Build big-endian kernel"
745 depends on ARCH_SUPPORTS_BIG_ENDIAN
746 depends on !LD_IS_LLD
747 help
748 Say Y if you plan on running a kernel in big-endian mode.
749 Note that your board must be properly built and your board
750 port must properly enable any big-endian related features
751 of your chipset/board/processor.
753 config CPU_ENDIAN_BE8
754 bool
755 depends on CPU_BIG_ENDIAN
756 default CPU_V6 || CPU_V6K || CPU_V7
757 help
758 Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
760 config CPU_ENDIAN_BE32
761 bool
762 depends on CPU_BIG_ENDIAN
763 default !CPU_ENDIAN_BE8
764 help
765 Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
767 config CPU_HIGH_VECTOR
768 depends on !MMU && CPU_CP15 && !CPU_ARM740T
769 bool "Select the High exception vector"
770 help
771 Say Y here to select high exception vector(0xFFFF0000~).
772 The exception vector can vary depending on the platform
773 design in nommu mode. If your platform needs to select
774 high exception vector, say Y.
775 Otherwise or if you are unsure, say N, and the low exception
776 vector (0x00000000~) will be used.
778 config CPU_ICACHE_DISABLE
779 bool "Disable I-Cache (I-bit)"
780 depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
781 help
782 Say Y here to disable the processor instruction cache. Unless
783 you have a reason not to or are unsure, say N.
785 config CPU_ICACHE_MISMATCH_WORKAROUND
786 bool "Workaround for I-Cache line size mismatch between CPU cores"
787 depends on SMP && CPU_V7
788 help
789 Some big.LITTLE systems have I-Cache line size mismatch between
790 LITTLE and big cores. Say Y here to enable a workaround for
791 proper I-Cache support on such systems. If unsure, say N.
793 config CPU_DCACHE_DISABLE
794 bool "Disable D-Cache (C-bit)"
795 depends on (CPU_CP15 && !SMP) || CPU_V7M
796 help
797 Say Y here to disable the processor data cache. Unless
798 you have a reason not to or are unsure, say N.
800 config CPU_DCACHE_SIZE
801 hex
802 depends on CPU_ARM740T || CPU_ARM946E
803 default 0x00001000 if CPU_ARM740T
804 default 0x00002000 # default size for ARM946E-S
805 help
806 Some cores are synthesizable to have various sized cache. For
807 ARM946E-S case, it can vary from 0KB to 1MB.
808 To support such cache operations, it is efficient to know the size
809 before compile time.
810 If your SoC is configured to have a different size, define the value
811 here with proper conditions.
813 config CPU_DCACHE_WRITETHROUGH
814 bool "Force write through D-cache"
815 depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
816 default y if CPU_ARM925T
817 help
818 Say Y here to use the data cache in writethrough mode. Unless you
819 specifically require this or are unsure, say N.
821 config CPU_CACHE_ROUND_ROBIN
822 bool "Round robin I and D cache replacement algorithm"
823 depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
824 help
825 Say Y here to use the predictable round-robin cache replacement
826 policy. Unless you specifically require this or are unsure, say N.
828 config CPU_BPREDICT_DISABLE
829 bool "Disable branch prediction"
830 depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
831 help
832 Say Y here to disable branch prediction. If unsure, say N.
834 config CPU_SPECTRE
835 bool
837 config HARDEN_BRANCH_PREDICTOR
838 bool "Harden the branch predictor against aliasing attacks" if EXPERT
839 depends on CPU_SPECTRE
840 default y
841 help
842 Speculation attacks against some high-performance processors rely
843 on being able to manipulate the branch predictor for a victim
844 context by executing aliasing branches in the attacker context.
845 Such attacks can be partially mitigated against by clearing
846 internal branch predictor state and limiting the prediction
847 logic in some situations.
849 This config option will take CPU-specific actions to harden
850 the branch predictor against aliasing attacks and may rely on
851 specific instruction sequences or control bits being set by
852 the system firmware.
854 If unsure, say Y.
856 config TLS_REG_EMUL
857 bool
858 select NEED_KUSER_HELPERS
859 help
860 An SMP system using a pre-ARMv6 processor (there are apparently
861 a few prototypes like that in existence) and therefore access to
862 that required register must be emulated.
864 config NEED_KUSER_HELPERS
865 bool
867 config KUSER_HELPERS
868 bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
869 depends on MMU
870 default y
871 help
872 Warning: disabling this option may break user programs.
874 Provide kuser helpers in the vector page. The kernel provides
875 helper code to userspace in read only form at a fixed location
876 in the high vector page to allow userspace to be independent of
877 the CPU type fitted to the system. This permits binaries to be
878 run on ARMv4 through to ARMv7 without modification.
880 See Documentation/arm/kernel_user_helpers.rst for details.
882 However, the fixed address nature of these helpers can be used
883 by ROP (return orientated programming) authors when creating
884 exploits.
886 If all of the binaries and libraries which run on your platform
887 are built specifically for your platform, and make no use of
888 these helpers, then you can turn this option off to hinder
889 such exploits. However, in that case, if a binary or library
890 relying on those helpers is run, it will receive a SIGILL signal,
891 which will terminate the program.
893 Say N here only if you are absolutely certain that you do not
894 need these helpers; otherwise, the safe option is to say Y.
896 config VDSO
897 bool "Enable VDSO for acceleration of some system calls"
898 depends on AEABI && MMU && CPU_V7
899 default y if ARM_ARCH_TIMER
900 select HAVE_GENERIC_VDSO
901 select GENERIC_TIME_VSYSCALL
902 select GENERIC_VDSO_32
903 select GENERIC_GETTIMEOFDAY
904 help
905 Place in the process address space an ELF shared object
906 providing fast implementations of gettimeofday and
907 clock_gettime. Systems that implement the ARM architected
908 timer will receive maximum benefit.
910 You must have glibc 2.22 or later for programs to seamlessly
911 take advantage of this.
913 config DMA_CACHE_RWFO
914 bool "Enable read/write for ownership DMA cache maintenance"
915 depends on CPU_V6K && SMP
916 default y
917 help
918 The Snoop Control Unit on ARM11MPCore does not detect the
919 cache maintenance operations and the dma_{map,unmap}_area()
920 functions may leave stale cache entries on other CPUs. By
921 enabling this option, Read or Write For Ownership in the ARMv6
922 DMA cache maintenance functions is performed. These LDR/STR
923 instructions change the cache line state to shared or modified
924 so that the cache operation has the desired effect.
926 Note that the workaround is only valid on processors that do
927 not perform speculative loads into the D-cache. For such
928 processors, if cache maintenance operations are not broadcast
929 in hardware, other workarounds are needed (e.g. cache
930 maintenance broadcasting in software via FIQ).
932 config OUTER_CACHE
933 bool
935 config OUTER_CACHE_SYNC
936 bool
937 select ARM_HEAVY_MB
938 help
939 The outer cache has a outer_cache_fns.sync function pointer
940 that can be used to drain the write buffer of the outer cache.
942 config CACHE_B15_RAC
943 bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
944 depends on ARCH_BRCMSTB
945 default y
946 help
947 This option enables the Broadcom Brahma-B15 read-ahead cache
948 controller. If disabled, the read-ahead cache remains off.
950 config CACHE_FEROCEON_L2
951 bool "Enable the Feroceon L2 cache controller"
952 depends on ARCH_MV78XX0 || ARCH_MVEBU
953 default y
954 select OUTER_CACHE
955 help
956 This option enables the Feroceon L2 cache controller.
958 config CACHE_FEROCEON_L2_WRITETHROUGH
959 bool "Force Feroceon L2 cache write through"
960 depends on CACHE_FEROCEON_L2
961 help
962 Say Y here to use the Feroceon L2 cache in writethrough mode.
963 Unless you specifically require this, say N for writeback mode.
965 config MIGHT_HAVE_CACHE_L2X0
966 bool
967 help
968 This option should be selected by machines which have a L2x0
969 or PL310 cache controller, but where its use is optional.
971 The only effect of this option is to make CACHE_L2X0 and
972 related options available to the user for configuration.
974 Boards or SoCs which always require the cache controller
975 support to be present should select CACHE_L2X0 directly
976 instead of this option, thus preventing the user from
977 inadvertently configuring a broken kernel.
979 config CACHE_L2X0
980 bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
981 default MIGHT_HAVE_CACHE_L2X0
982 select OUTER_CACHE
983 select OUTER_CACHE_SYNC
984 help
985 This option enables the L2x0 PrimeCell.
987 config CACHE_L2X0_PMU
988 bool "L2x0 performance monitor support" if CACHE_L2X0
989 depends on PERF_EVENTS
990 help
991 This option enables support for the performance monitoring features
992 of the L220 and PL310 outer cache controllers.
994 if CACHE_L2X0
996 config PL310_ERRATA_588369
997 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
998 help
999 The PL310 L2 cache controller implements three types of Clean &
1000 Invalidate maintenance operations: by Physical Address
1001 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1002 They are architecturally defined to behave as the execution of a
1003 clean operation followed immediately by an invalidate operation,
1004 both performing to the same memory location. This functionality
1005 is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
1006 as clean lines are not invalidated as a result of these operations.
1008 config PL310_ERRATA_727915
1009 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1010 help
1011 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1012 operation (offset 0x7FC). This operation runs in background so that
1013 PL310 can handle normal accesses while it is in progress. Under very
1014 rare circumstances, due to this erratum, write data can be lost when
1015 PL310 treats a cacheable write transaction during a Clean &
1016 Invalidate by Way operation. Revisions prior to r3p1 are affected by
1017 this errata (fixed in r3p1).
1019 config PL310_ERRATA_753970
1020 bool "PL310 errata: cache sync operation may be faulty"
1021 help
1022 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1024 Under some condition the effect of cache sync operation on
1025 the store buffer still remains when the operation completes.
1026 This means that the store buffer is always asked to drain and
1027 this prevents it from merging any further writes. The workaround
1028 is to replace the normal offset of cache sync operation (0x730)
1029 by another offset targeting an unmapped PL310 register 0x740.
1030 This has the same effect as the cache sync operation: store buffer
1031 drain and waiting for all buffers empty.
1033 config PL310_ERRATA_769419
1034 bool "PL310 errata: no automatic Store Buffer drain"
1035 help
1036 On revisions of the PL310 prior to r3p2, the Store Buffer does
1037 not automatically drain. This can cause normal, non-cacheable
1038 writes to be retained when the memory system is idle, leading
1039 to suboptimal I/O performance for drivers using coherent DMA.
1040 This option adds a write barrier to the cpu_idle loop so that,
1041 on systems with an outer cache, the store buffer is drained
1042 explicitly.
1044 endif
1046 config CACHE_TAUROS2
1047 bool "Enable the Tauros2 L2 cache controller"
1048 depends on (CPU_MOHAWK || CPU_PJ4)
1049 default y
1050 select OUTER_CACHE
1051 help
1052 This option enables the Tauros2 L2 cache controller (as
1053 found on PJ1/PJ4).
1055 config CACHE_UNIPHIER
1056 bool "Enable the UniPhier outer cache controller"
1057 depends on ARCH_UNIPHIER
1058 select ARM_L1_CACHE_SHIFT_7
1059 select OUTER_CACHE
1060 select OUTER_CACHE_SYNC
1061 help
1062 This option enables the UniPhier outer cache (system cache)
1063 controller.
1065 config CACHE_XSC3L2
1066 bool "Enable the L2 cache on XScale3"
1067 depends on CPU_XSC3
1068 default y
1069 select OUTER_CACHE
1070 help
1071 This option enables the L2 cache on XScale3.
1073 config ARM_L1_CACHE_SHIFT_6
1074 bool
1075 default y if CPU_V7
1076 help
1077 Setting ARM L1 cache line size to 64 Bytes.
1079 config ARM_L1_CACHE_SHIFT_7
1080 bool
1081 help
1082 Setting ARM L1 cache line size to 128 Bytes.
1084 config ARM_L1_CACHE_SHIFT
1085 int
1086 default 7 if ARM_L1_CACHE_SHIFT_7
1087 default 6 if ARM_L1_CACHE_SHIFT_6
1088 default 5
1090 config ARM_DMA_MEM_BUFFERABLE
1091 bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K || CPU_V7M) && !CPU_V7
1092 default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
1093 help
1094 Historically, the kernel has used strongly ordered mappings to
1095 provide DMA coherent memory. With the advent of ARMv7, mapping
1096 memory with differing types results in unpredictable behaviour,
1097 so on these CPUs, this option is forced on.
1099 Multiple mappings with differing attributes is also unpredictable
1100 on ARMv6 CPUs, but since they do not have aggressive speculative
1101 prefetch, no harm appears to occur.
1103 However, drivers may be missing the necessary barriers for ARMv6,
1104 and therefore turning this on may result in unpredictable driver
1105 behaviour. Therefore, we offer this as an option.
1107 On some of the beefier ARMv7-M machines (with DMA and write
1108 buffers) you likely want this enabled, while those that
1109 didn't need it until now also won't need it in the future.
1111 You are recommended say 'Y' here and debug any affected drivers.
1113 config ARM_HEAVY_MB
1114 bool
1116 config ARCH_SUPPORTS_BIG_ENDIAN
1117 bool
1118 help
1119 This option specifies the architecture can support big endian
1120 operation.
1122 config DEBUG_ALIGN_RODATA
1123 bool "Make rodata strictly non-executable"
1124 depends on STRICT_KERNEL_RWX
1125 default y
1126 help
1127 If this is set, rodata will be made explicitly non-executable. This
1128 provides protection on the rare chance that attackers might find and
1129 use ROP gadgets that exist in the rodata section. This adds an
1130 additional section-aligned split of rodata from kernel text so it
1131 can be made explicitly non-executable. This padding may waste memory
1132 space to gain the additional protection.