arch/arm64/boot/dts/actions/s700.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2017 Andreas Färber
   4  */
   5
   6 #include <dt-bindings/clock/actions,s700-cmu.h>
   7 #include <dt-bindings/interrupt-controller/arm-gic.h>
   8 #include <dt-bindings/power/owl-s700-powergate.h>
   9 #include <dt-bindings/reset/actions,s700-reset.h>
  10
  11 / {
  12         compatible = "actions,s700";
  13         interrupt-parent = <&gic>;
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <2>;
  19                 #size-cells = <0>;
  20
  21                 cpu0: cpu@0 {
  22                         device_type = "cpu";
  23                         compatible = "arm,cortex-a53";
  24                         reg = <0x0 0x0>;
  25                         enable-method = "psci";
  26                 };
  27
  28                 cpu1: cpu@1 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a53";
  31                         reg = <0x0 0x1>;
  32                         enable-method = "psci";
  33                 };
  34
  35                 cpu2: cpu@2 {
  36                         device_type = "cpu";
  37                         compatible = "arm,cortex-a53";
  38                         reg = <0x0 0x2>;
  39                         enable-method = "psci";
  40                 };
  41
  42                 cpu3: cpu@3 {
  43                         device_type = "cpu";
  44                         compatible = "arm,cortex-a53";
  45                         reg = <0x0 0x3>;
  46                         enable-method = "psci";
  47                 };
  48         };
  49
  50         reserved-memory {
  51                 #address-cells = <2>;
  52                 #size-cells = <2>;
  53                 ranges;
  54
  55                 secmon@1f000000 {
  56                         reg = <0x0 0x1f000000 0x0 0x1000000>;
  57                         no-map;
  58                 };
  59         };
  60
  61         psci {
  62                 compatible = "arm,psci-0.2";
  63                 method = "smc";
  64         };
  65
  66         arm-pmu {
  67                 compatible = "arm,cortex-a53-pmu";
  68                 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
  69                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
  70                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
  71                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
  72                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv8-timer";
  77                 interrupts = <GIC_PPI 13
  78                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 14
  80                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 11
  82                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  83                              <GIC_PPI 10
  84                         (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  85         };
  86
  87         hosc: hosc {
  88                 compatible = "fixed-clock";
  89                 clock-frequency = <24000000>;
  90                 #clock-cells = <0>;
  91         };
  92
  93         losc: losc {
  94                 compatible = "fixed-clock";
  95                 clock-frequency = <32768>;
  96                 #clock-cells = <0>;
  97         };
  98
  99         soc {
 100                 compatible = "simple-bus";
 101                 #address-cells = <2>;
 102                 #size-cells = <2>;
 103                 ranges;
 104
 105                 gic: interrupt-controller@e00f1000 {
 106                         compatible = "arm,gic-400";
 107                         reg = <0x0 0xe00f1000 0x0 0x1000>,
 108                               <0x0 0xe00f2000 0x0 0x2000>,
 109                               <0x0 0xe00f4000 0x0 0x2000>,
 110                               <0x0 0xe00f6000 0x0 0x2000>;
 111                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 112                         interrupt-controller;
 113                         #interrupt-cells = <3>;
 114                 };
 115
 116                 uart0: serial@e0120000 {
 117                         compatible = "actions,s900-uart", "actions,owl-uart";
 118                         reg = <0x0 0xe0120000 0x0 0x2000>;
 119                         clocks = <&cmu CLK_UART0>;
 120                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 121                         status = "disabled";
 122                 };
 123
 124                 uart1: serial@e0122000 {
 125                         compatible = "actions,s900-uart", "actions,owl-uart";
 126                         reg = <0x0 0xe0122000 0x0 0x2000>;
 127                         clocks = <&cmu CLK_UART1>;
 128                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 129                         status = "disabled";
 130                 };
 131
 132                 uart2: serial@e0124000 {
 133                         compatible = "actions,s900-uart", "actions,owl-uart";
 134                         reg = <0x0 0xe0124000 0x0 0x2000>;
 135                         clocks = <&cmu CLK_UART2>;
 136                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 137                         status = "disabled";
 138                 };
 139
 140                 uart3: serial@e0126000 {
 141                         compatible = "actions,s900-uart", "actions,owl-uart";
 142                         reg = <0x0 0xe0126000 0x0 0x2000>;
 143                         clocks = <&cmu CLK_UART3>;
 144                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 145                         status = "disabled";
 146                 };
 147
 148                 uart4: serial@e0128000 {
 149                         compatible = "actions,s900-uart", "actions,owl-uart";
 150                         reg = <0x0 0xe0128000 0x0 0x2000>;
 151                         clocks = <&cmu CLK_UART4>;
 152                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 153                         status = "disabled";
 154                 };
 155
 156                 uart5: serial@e012a000 {
 157                         compatible = "actions,s900-uart", "actions,owl-uart";
 158                         reg = <0x0 0xe012a000 0x0 0x2000>;
 159                         clocks = <&cmu CLK_UART5>;
 160                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 161                         status = "disabled";
 162                 };
 163
 164                 uart6: serial@e012c000 {
 165                         compatible = "actions,s900-uart", "actions,owl-uart";
 166                         reg = <0x0 0xe012c000 0x0 0x2000>;
 167                         clocks = <&cmu CLK_UART6>;
 168                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 169                         status = "disabled";
 170                 };
 171
 172                 cmu: clock-controller@e0168000 {
 173                         compatible = "actions,s700-cmu";
 174                         reg = <0x0 0xe0168000 0x0 0x1000>;
 175                         clocks = <&hosc>, <&losc>;
 176                         #clock-cells = <1>;
 177                         #reset-cells = <1>;
 178                 };
 179
 180                 i2c0: i2c@e0170000 {
 181                         compatible = "actions,s700-i2c";
 182                         reg = <0 0xe0170000 0 0x1000>;
 183                         clocks = <&cmu CLK_I2C0>;
 184                         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 185                         #address-cells = <1>;
 186                         #size-cells = <0>;
 187                         status = "disabled";
 188                 };
 189
 190                 i2c1: i2c@e0174000 {
 191                         compatible = "actions,s700-i2c";
 192                         reg = <0 0xe0174000 0 0x1000>;
 193                         clocks = <&cmu CLK_I2C1>;
 194                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 195                         #address-cells = <1>;
 196                         #size-cells = <0>;
 197                         status = "disabled";
 198                 };
 199
 200                 i2c2: i2c@e0178000 {
 201                         compatible = "actions,s700-i2c";
 202                         reg = <0 0xe0178000 0 0x1000>;
 203                         clocks = <&cmu CLK_I2C2>;
 204                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         status = "disabled";
 208                 };
 209
 210                 i2c3: i2c@e017c000 {
 211                         compatible = "actions,s700-i2c";
 212                         reg = <0 0xe017c000 0 0x1000>;
 213                         clocks = <&cmu CLK_I2C3>;
 214                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 215                         #address-cells = <1>;
 216                         #size-cells = <0>;
 217                         status = "disabled";
 218                 };
 219
 220                 sps: power-controller@e01b0100 {
 221                         compatible = "actions,s700-sps";
 222                         reg = <0x0 0xe01b0100 0x0 0x100>;
 223                         #power-domain-cells = <1>;
 224                 };
 225
 226                 timer: timer@e024c000 {
 227                         compatible = "actions,s700-timer";
 228                         reg = <0x0 0xe024c000 0x0 0x4000>;
 229                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 230                         interrupt-names = "timer1";
 231                 };
 232
 233                 pinctrl: pinctrl@e01b0000 {
 234                         compatible = "actions,s700-pinctrl";
 235                         reg = <0x0 0xe01b0000 0x0 0x100>;
 236                         clocks = <&cmu CLK_GPIO>;
 237                         gpio-controller;
 238                         gpio-ranges = <&pinctrl 0 0 136>;
 239                         #gpio-cells = <2>;
 240                         interrupt-controller;
 241                         #interrupt-cells = <2>;
 242                         interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
 243                                      <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
 244                                      <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 245                                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 246                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 247                 };
 248
 249                 dma: dma-controller@e0230000 {
 250                         compatible = "actions,s700-dma";
 251                         reg = <0x0 0xe0230000 0x0 0x1000>;
 252                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 253                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 254                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 255                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 256                         #dma-cells = <1>;
 257                         dma-channels = <10>;
 258                         dma-requests = <44>;
 259                         clocks = <&cmu CLK_DMAC>;
 260                         power-domains = <&sps S700_PD_DMA>;
 261                 };
 262         };
 263 };