1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2017 Jagan Teki <jteki@openedev.com>
6 #include "sun50i-a64.dtsi"
7 #include "sun50i-a64-cpu-opp.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
12 model = "FriendlyARM NanoPi A64";
13 compatible = "friendlyarm,nanopi-a64", "allwinner,sun50i-a64";
21 stdout-path = "serial0:115200n8";
25 compatible = "hdmi-connector";
29 hdmi_con_in: endpoint {
30 remote-endpoint = <&hdmi_out_con>;
36 compatible = "gpio-leds";
39 label = "nanopi-a64:blue:status";
40 gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
44 wifi_pwrseq: wifi_pwrseq {
45 compatible = "mmc-pwrseq-simple";
47 clock-names = "ext_clock";
48 reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
53 cpu-supply = <®_dcdc2>;
57 cpu-supply = <®_dcdc2>;
61 cpu-supply = <®_dcdc2>;
65 cpu-supply = <®_dcdc2>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&rgmii_pins>;
84 phy-handle = <&ext_rgmii_phy>;
85 phy-supply = <®_dcdc1>;
90 hvcc-supply = <®_dldo1>;
95 hdmi_out_con: endpoint {
96 remote-endpoint = <&hdmi_con_in>;
100 /* i2c1 connected with gpio headers like pine64, bananapi */
106 ext_rgmii_phy: ethernet-phy@1 {
107 compatible = "ethernet-phy-ieee802.3-c22";
113 pinctrl-names = "default";
114 pinctrl-0 = <&mmc0_pins>;
115 vmmc-supply = <®_dcdc1>;
116 cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
123 pinctrl-names = "default";
124 pinctrl-0 = <&mmc1_pins>;
125 vmmc-supply = <®_dcdc1>;
126 vqmmc-supply = <®_dldo4>;
127 mmc-pwrseq = <&wifi_pwrseq>;
134 interrupt-parent = <&r_pio>;
135 interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
136 interrupt-names = "host-wake";
152 compatible = "x-powers,axp803";
154 interrupt-parent = <&r_intc>;
155 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
159 #include "axp803.dtsi"
167 regulator-min-microvolt = <1800000>;
168 regulator-max-microvolt = <3300000>;
169 regulator-name = "vcc-pl";
174 regulator-min-microvolt = <3000000>;
175 regulator-max-microvolt = <3000000>;
176 regulator-name = "vcc-pll-avcc";
181 regulator-min-microvolt = <3300000>;
182 regulator-max-microvolt = <3300000>;
183 regulator-name = "vcc-3v3";
188 regulator-min-microvolt = <1040000>;
189 regulator-max-microvolt = <1300000>;
190 regulator-name = "vdd-cpux";
193 /* DCDC3 is polyphased with DCDC2 */
197 regulator-min-microvolt = <1500000>;
198 regulator-max-microvolt = <1500000>;
199 regulator-name = "vcc-dram";
204 regulator-min-microvolt = <1100000>;
205 regulator-max-microvolt = <1100000>;
206 regulator-name = "vdd-sys";
211 regulator-min-microvolt = <3300000>;
212 regulator-max-microvolt = <3300000>;
213 regulator-name = "vcc-hdmi-dsi";
218 regulator-min-microvolt = <3000000>;
219 regulator-max-microvolt = <3000000>;
220 regulator-name = "vcc-pg-wifi-io";
224 regulator-min-microvolt = <1800000>;
225 regulator-max-microvolt = <1800000>;
226 regulator-name = "cpvdd";
230 regulator-min-microvolt = <1200000>;
231 regulator-max-microvolt = <1200000>;
232 regulator-name = "vcc-1v2-hsic";
236 * The A64 chip cannot work without this regulator off, although
237 * it seems to be only driving the AR100 core.
238 * Maybe we don't still know well about CPUs domain.
242 regulator-min-microvolt = <1100000>;
243 regulator-max-microvolt = <1100000>;
244 regulator-name = "vdd-cpus";
248 regulator-name = "vcc-rtc";
252 vcc-hdmi-supply = <®_dldo1>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&uart0_pb_pins>;