WIP FPC-III support
[linux/fpc-iii.git] / arch / arm64 / boot / dts / arm / juno.dts
blobf00cffbd032c50a28e6473078d794f8f9f8cd320
1 /*
2  * ARM Ltd. Juno Platform
3  *
4  * Copyright (c) 2013-2014 ARM Ltd.
5  *
6  * This file is licensed under a dual GPLv2 or BSD license.
7  */
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "juno-base.dtsi"
14 / {
15         model = "ARM Juno development board (r0)";
16         compatible = "arm,juno", "arm,vexpress";
17         interrupt-parent = <&gic>;
18         #address-cells = <2>;
19         #size-cells = <2>;
21         aliases {
22                 serial0 = &soc_uart0;
23         };
25         chosen {
26                 stdout-path = "serial0:115200n8";
27         };
29         psci {
30                 compatible = "arm,psci-0.2";
31                 method = "smc";
32         };
34         cpus {
35                 #address-cells = <2>;
36                 #size-cells = <0>;
38                 cpu-map {
39                         cluster0 {
40                                 core0 {
41                                         cpu = <&A57_0>;
42                                 };
43                                 core1 {
44                                         cpu = <&A57_1>;
45                                 };
46                         };
48                         cluster1 {
49                                 core0 {
50                                         cpu = <&A53_0>;
51                                 };
52                                 core1 {
53                                         cpu = <&A53_1>;
54                                 };
55                                 core2 {
56                                         cpu = <&A53_2>;
57                                 };
58                                 core3 {
59                                         cpu = <&A53_3>;
60                                 };
61                         };
62                 };
64                 idle-states {
65                         entry-method = "psci";
67                         CPU_SLEEP_0: cpu-sleep-0 {
68                                 compatible = "arm,idle-state";
69                                 arm,psci-suspend-param = <0x0010000>;
70                                 local-timer-stop;
71                                 entry-latency-us = <300>;
72                                 exit-latency-us = <1200>;
73                                 min-residency-us = <2000>;
74                         };
76                         CLUSTER_SLEEP_0: cluster-sleep-0 {
77                                 compatible = "arm,idle-state";
78                                 arm,psci-suspend-param = <0x1010000>;
79                                 local-timer-stop;
80                                 entry-latency-us = <400>;
81                                 exit-latency-us = <1200>;
82                                 min-residency-us = <2500>;
83                         };
84                 };
86                 A57_0: cpu@0 {
87                         compatible = "arm,cortex-a57";
88                         reg = <0x0 0x0>;
89                         device_type = "cpu";
90                         enable-method = "psci";
91                         i-cache-size = <0xc000>;
92                         i-cache-line-size = <64>;
93                         i-cache-sets = <256>;
94                         d-cache-size = <0x8000>;
95                         d-cache-line-size = <64>;
96                         d-cache-sets = <256>;
97                         next-level-cache = <&A57_L2>;
98                         clocks = <&scpi_dvfs 0>;
99                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
100                         capacity-dmips-mhz = <1024>;
101                         dynamic-power-coefficient = <530>;
102                 };
104                 A57_1: cpu@1 {
105                         compatible = "arm,cortex-a57";
106                         reg = <0x0 0x1>;
107                         device_type = "cpu";
108                         enable-method = "psci";
109                         i-cache-size = <0xc000>;
110                         i-cache-line-size = <64>;
111                         i-cache-sets = <256>;
112                         d-cache-size = <0x8000>;
113                         d-cache-line-size = <64>;
114                         d-cache-sets = <256>;
115                         next-level-cache = <&A57_L2>;
116                         clocks = <&scpi_dvfs 0>;
117                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
118                         capacity-dmips-mhz = <1024>;
119                         dynamic-power-coefficient = <530>;
120                 };
122                 A53_0: cpu@100 {
123                         compatible = "arm,cortex-a53";
124                         reg = <0x0 0x100>;
125                         device_type = "cpu";
126                         enable-method = "psci";
127                         i-cache-size = <0x8000>;
128                         i-cache-line-size = <64>;
129                         i-cache-sets = <256>;
130                         d-cache-size = <0x8000>;
131                         d-cache-line-size = <64>;
132                         d-cache-sets = <128>;
133                         next-level-cache = <&A53_L2>;
134                         clocks = <&scpi_dvfs 1>;
135                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
136                         capacity-dmips-mhz = <578>;
137                         dynamic-power-coefficient = <140>;
138                 };
140                 A53_1: cpu@101 {
141                         compatible = "arm,cortex-a53";
142                         reg = <0x0 0x101>;
143                         device_type = "cpu";
144                         enable-method = "psci";
145                         i-cache-size = <0x8000>;
146                         i-cache-line-size = <64>;
147                         i-cache-sets = <256>;
148                         d-cache-size = <0x8000>;
149                         d-cache-line-size = <64>;
150                         d-cache-sets = <128>;
151                         next-level-cache = <&A53_L2>;
152                         clocks = <&scpi_dvfs 1>;
153                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
154                         capacity-dmips-mhz = <578>;
155                         dynamic-power-coefficient = <140>;
156                 };
158                 A53_2: cpu@102 {
159                         compatible = "arm,cortex-a53";
160                         reg = <0x0 0x102>;
161                         device_type = "cpu";
162                         enable-method = "psci";
163                         i-cache-size = <0x8000>;
164                         i-cache-line-size = <64>;
165                         i-cache-sets = <256>;
166                         d-cache-size = <0x8000>;
167                         d-cache-line-size = <64>;
168                         d-cache-sets = <128>;
169                         next-level-cache = <&A53_L2>;
170                         clocks = <&scpi_dvfs 1>;
171                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
172                         capacity-dmips-mhz = <578>;
173                         dynamic-power-coefficient = <140>;
174                 };
176                 A53_3: cpu@103 {
177                         compatible = "arm,cortex-a53";
178                         reg = <0x0 0x103>;
179                         device_type = "cpu";
180                         enable-method = "psci";
181                         i-cache-size = <0x8000>;
182                         i-cache-line-size = <64>;
183                         i-cache-sets = <256>;
184                         d-cache-size = <0x8000>;
185                         d-cache-line-size = <64>;
186                         d-cache-sets = <128>;
187                         next-level-cache = <&A53_L2>;
188                         clocks = <&scpi_dvfs 1>;
189                         cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
190                         capacity-dmips-mhz = <578>;
191                         dynamic-power-coefficient = <140>;
192                 };
194                 A57_L2: l2-cache0 {
195                         compatible = "cache";
196                         cache-size = <0x200000>;
197                         cache-line-size = <64>;
198                         cache-sets = <2048>;
199                 };
201                 A53_L2: l2-cache1 {
202                         compatible = "cache";
203                         cache-size = <0x100000>;
204                         cache-line-size = <64>;
205                         cache-sets = <1024>;
206                 };
207         };
209         pmu-a57 {
210                 compatible = "arm,cortex-a57-pmu";
211                 interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>,
212                              <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>;
213                 interrupt-affinity = <&A57_0>,
214                                      <&A57_1>;
215         };
217         pmu-a53 {
218                 compatible = "arm,cortex-a53-pmu";
219                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
220                              <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
221                              <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
222                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
223                 interrupt-affinity = <&A53_0>,
224                                      <&A53_1>,
225                                      <&A53_2>,
226                                      <&A53_3>;
227         };
230 &etm0 {
231         cpu = <&A57_0>;
234 &etm1 {
235         cpu = <&A57_1>;
238 &etm2 {
239         cpu = <&A53_0>;
242 &etm3 {
243         cpu = <&A53_1>;
246 &etm4 {
247         cpu = <&A53_2>;
250 &etm5 {
251         cpu = <&A53_3>;
254 &etf0_out_port {
255         remote-endpoint = <&replicator_in_port0>;
258 &replicator_in_port0 {
259         remote-endpoint = <&etf0_out_port>;
262 &stm_out_port {
263         remote-endpoint = <&main_funnel_in_port2>;
266 &main_funnel_in_ports {
267         port@2 {
268                 reg = <2>;
269                 main_funnel_in_port2: endpoint {
270                         remote-endpoint = <&stm_out_port>;
271                 };
272         };
275 &cpu_debug0 {
276         cpu = <&A57_0>;
279 &cpu_debug1 {
280         cpu = <&A57_1>;
283 &cpu_debug2 {
284         cpu = <&A53_0>;
287 &cpu_debug3 {
288         cpu = <&A53_1>;
291 &cpu_debug4 {
292         cpu = <&A53_2>;
295 &cpu_debug5 {
296         cpu = <&A53_3>;