| blob | 60ff19fa53b40fb0eab33454886f5a8a203949a5 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
4 *
5 * Copyright 2018-2020 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 / {
15 compatible = "fsl,ls1028a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
20 aliases {
21 rtc1 = &ftm_alarm0;
22 };
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
28 cpu0: cpu@0 {
29 device_type = "cpu";
30 compatible = "arm,cortex-a72";
31 reg = <0x0>;
32 enable-method = "psci";
33 clocks = <&clockgen 1 0>;
34 next-level-cache = <&l2>;
35 cpu-idle-states = <&CPU_PW20>;
36 #cooling-cells = <2>;
37 };
39 cpu1: cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,cortex-a72";
42 reg = <0x1>;
43 enable-method = "psci";
44 clocks = <&clockgen 1 0>;
45 next-level-cache = <&l2>;
46 cpu-idle-states = <&CPU_PW20>;
47 #cooling-cells = <2>;
48 };
50 l2: l2-cache {
51 compatible = "cache";
52 };
53 };
55 idle-states {
56 /*
57 * PSCI node is not added default, U-boot will add missing
58 * parts if it determines to use PSCI.
59 */
60 entry-method = "psci";
62 CPU_PW20: cpu-pw20 {
63 compatible = "arm,idle-state";
64 idle-state-name = "PW20";
65 arm,psci-suspend-param = <0x0>;
66 entry-latency-us = <2000>;
67 exit-latency-us = <2000>;
68 min-residency-us = <6000>;
69 };
70 };
72 sysclk: clock-sysclk {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <100000000>;
76 clock-output-names = "sysclk";
77 };
79 osc_27m: clock-osc-27m {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <27000000>;
83 clock-output-names = "phy_27m";
84 };
86 dpclk: clock-controller@f1f0000 {
87 compatible = "fsl,ls1028a-plldig";
88 reg = <0x0 0xf1f0000 0x0 0xffff>;
89 #clock-cells = <0>;
90 clocks = <&osc_27m>;
91 };
93 firmware {
94 optee {
95 compatible = "linaro,optee-tz";
96 method = "smc";
97 status = "disabled";
98 };
99 };
101 reboot {
102 compatible ="syscon-reboot";
103 regmap = <&rst>;
104 offset = <0xb0>;
105 mask = <0x02>;
106 };
108 timer {
109 compatible = "arm,armv8-timer";
110 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
111 IRQ_TYPE_LEVEL_LOW)>,
112 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
113 IRQ_TYPE_LEVEL_LOW)>,
114 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
115 IRQ_TYPE_LEVEL_LOW)>,
116 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
117 IRQ_TYPE_LEVEL_LOW)>;
118 };
120 pmu {
121 compatible = "arm,cortex-a72-pmu";
122 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
123 };
125 gic: interrupt-controller@6000000 {
126 compatible= "arm,gic-v3";
127 #address-cells = <2>;
128 #size-cells = <2>;
129 ranges;
130 reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */
131 <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */
132 #interrupt-cells= <3>;
133 interrupt-controller;
134 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
135 IRQ_TYPE_LEVEL_LOW)>;
136 its: gic-its@6020000 {
137 compatible = "arm,gic-v3-its";
138 msi-controller;
139 reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */
140 };
141 };
143 thermal-zones {
144 ddr-controller {
145 polling-delay-passive = <1000>;
146 polling-delay = <5000>;
147 thermal-sensors = <&tmu 0>;
149 trips {
150 ddr-ctrler-alert {
151 temperature = <85000>;
152 hysteresis = <2000>;
153 type = "passive";
154 };
156 ddr-ctrler-crit {
157 temperature = <95000>;
158 hysteresis = <2000>;
159 type = "critical";
160 };
161 };
162 };
164 core-cluster {
165 polling-delay-passive = <1000>;
166 polling-delay = <5000>;
167 thermal-sensors = <&tmu 1>;
169 trips {
170 core_cluster_alert: core-cluster-alert {
171 temperature = <85000>;
172 hysteresis = <2000>;
173 type = "passive";
174 };
176 core_cluster_crit: core-cluster-crit {
177 temperature = <95000>;
178 hysteresis = <2000>;
179 type = "critical";
180 };
181 };
183 cooling-maps {
184 map0 {
185 trip = <&core_cluster_alert>;
186 cooling-device =
187 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
188 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
189 };
190 };
191 };
192 };
194 soc: soc {
195 compatible = "simple-bus";
196 #address-cells = <2>;
197 #size-cells = <2>;
198 ranges;
200 ddr: memory-controller@1080000 {
201 compatible = "fsl,qoriq-memory-controller";
202 reg = <0x0 0x1080000 0x0 0x1000>;
203 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
204 big-endian;
205 };
207 dcfg: syscon@1e00000 {
208 compatible = "fsl,ls1028a-dcfg", "syscon";
209 reg = <0x0 0x1e00000 0x0 0x10000>;
210 little-endian;
211 };
213 rst: syscon@1e60000 {
214 compatible = "syscon";
215 reg = <0x0 0x1e60000 0x0 0x10000>;
216 little-endian;
217 };
219 scfg: syscon@1fc0000 {
220 compatible = "fsl,ls1028a-scfg", "syscon";
221 reg = <0x0 0x1fc0000 0x0 0x10000>;
222 big-endian;
223 };
225 clockgen: clock-controller@1300000 {
226 compatible = "fsl,ls1028a-clockgen";
227 reg = <0x0 0x1300000 0x0 0xa0000>;
228 #clock-cells = <2>;
229 clocks = <&sysclk>;
230 };
232 i2c0: i2c@2000000 {
233 compatible = "fsl,vf610-i2c";
234 #address-cells = <1>;
235 #size-cells = <0>;
236 reg = <0x0 0x2000000 0x0 0x10000>;
237 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clockgen 4 3>;
239 status = "disabled";
240 };
242 i2c1: i2c@2010000 {
243 compatible = "fsl,vf610-i2c";
244 #address-cells = <1>;
245 #size-cells = <0>;
246 reg = <0x0 0x2010000 0x0 0x10000>;
247 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clockgen 4 3>;
249 status = "disabled";
250 };
252 i2c2: i2c@2020000 {
253 compatible = "fsl,vf610-i2c";
254 #address-cells = <1>;
255 #size-cells = <0>;
256 reg = <0x0 0x2020000 0x0 0x10000>;
257 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&clockgen 4 3>;
259 status = "disabled";
260 };
262 i2c3: i2c@2030000 {
263 compatible = "fsl,vf610-i2c";
264 #address-cells = <1>;
265 #size-cells = <0>;
266 reg = <0x0 0x2030000 0x0 0x10000>;
267 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&clockgen 4 3>;
269 status = "disabled";
270 };
272 i2c4: i2c@2040000 {
273 compatible = "fsl,vf610-i2c";
274 #address-cells = <1>;
275 #size-cells = <0>;
276 reg = <0x0 0x2040000 0x0 0x10000>;
277 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&clockgen 4 3>;
279 status = "disabled";
280 };
282 i2c5: i2c@2050000 {
283 compatible = "fsl,vf610-i2c";
284 #address-cells = <1>;
285 #size-cells = <0>;
286 reg = <0x0 0x2050000 0x0 0x10000>;
287 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&clockgen 4 3>;
289 status = "disabled";
290 };
292 i2c6: i2c@2060000 {
293 compatible = "fsl,vf610-i2c";
294 #address-cells = <1>;
295 #size-cells = <0>;
296 reg = <0x0 0x2060000 0x0 0x10000>;
297 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&clockgen 4 3>;
299 status = "disabled";
300 };
302 i2c7: i2c@2070000 {
303 compatible = "fsl,vf610-i2c";
304 #address-cells = <1>;
305 #size-cells = <0>;
306 reg = <0x0 0x2070000 0x0 0x10000>;
307 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&clockgen 4 3>;
309 status = "disabled";
310 };
312 fspi: spi@20c0000 {
313 compatible = "nxp,lx2160a-fspi";
314 #address-cells = <1>;
315 #size-cells = <0>;
316 reg = <0x0 0x20c0000 0x0 0x10000>,
317 <0x0 0x20000000 0x0 0x10000000>;
318 reg-names = "fspi_base", "fspi_mmap";
319 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
320 clocks = <&clockgen 2 0>, <&clockgen 2 0>;
321 clock-names = "fspi_en", "fspi";
322 status = "disabled";
323 };
325 dspi0: spi@2100000 {
326 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
327 #address-cells = <1>;
328 #size-cells = <0>;
329 reg = <0x0 0x2100000 0x0 0x10000>;
330 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
331 clock-names = "dspi";
332 clocks = <&clockgen 4 1>;
333 dmas = <&edma0 0 62>, <&edma0 0 60>;
334 dma-names = "tx", "rx";
335 spi-num-chipselects = <4>;
336 little-endian;
337 status = "disabled";
338 };
340 dspi1: spi@2110000 {
341 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 reg = <0x0 0x2110000 0x0 0x10000>;
345 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
346 clock-names = "dspi";
347 clocks = <&clockgen 4 1>;
348 dmas = <&edma0 0 58>, <&edma0 0 56>;
349 dma-names = "tx", "rx";
350 spi-num-chipselects = <4>;
351 little-endian;
352 status = "disabled";
353 };
355 dspi2: spi@2120000 {
356 compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";
357 #address-cells = <1>;
358 #size-cells = <0>;
359 reg = <0x0 0x2120000 0x0 0x10000>;
360 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
361 clock-names = "dspi";
362 clocks = <&clockgen 4 1>;
363 dmas = <&edma0 0 54>, <&edma0 0 2>;
364 dma-names = "tx", "rx";
365 spi-num-chipselects = <3>;
366 little-endian;
367 status = "disabled";
368 };
370 esdhc: mmc@2140000 {
371 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
372 reg = <0x0 0x2140000 0x0 0x10000>;
373 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
374 clock-frequency = <0>; /* fixed up by bootloader */
375 clocks = <&clockgen 2 1>;
376 voltage-ranges = <1800 1800 3300 3300>;
377 sdhci,auto-cmd12;
378 little-endian;
379 bus-width = <4>;
380 status = "disabled";
381 };
383 esdhc1: mmc@2150000 {
384 compatible = "fsl,ls1028a-esdhc", "fsl,esdhc";
385 reg = <0x0 0x2150000 0x0 0x10000>;
386 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
387 clock-frequency = <0>; /* fixed up by bootloader */
388 clocks = <&clockgen 2 1>;
389 voltage-ranges = <1800 1800 3300 3300>;
390 sdhci,auto-cmd12;
391 broken-cd;
392 little-endian;
393 bus-width = <4>;
394 status = "disabled";
395 };
397 can0: can@2180000 {
398 compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
399 reg = <0x0 0x2180000 0x0 0x10000>;
400 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
401 clocks = <&sysclk>, <&clockgen 4 1>;
402 clock-names = "ipg", "per";
403 status = "disabled";
404 };
406 can1: can@2190000 {
407 compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan";
408 reg = <0x0 0x2190000 0x0 0x10000>;
409 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&sysclk>, <&clockgen 4 1>;
411 clock-names = "ipg", "per";
412 status = "disabled";
413 };
415 duart0: serial@21c0500 {
416 compatible = "fsl,ns16550", "ns16550a";
417 reg = <0x00 0x21c0500 0x0 0x100>;
418 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
419 clocks = <&clockgen 4 1>;
420 status = "disabled";
421 };
423 duart1: serial@21c0600 {
424 compatible = "fsl,ns16550", "ns16550a";
425 reg = <0x00 0x21c0600 0x0 0x100>;
426 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
427 clocks = <&clockgen 4 1>;
428 status = "disabled";
429 };
432 lpuart0: serial@2260000 {
433 compatible = "fsl,ls1028a-lpuart";
434 reg = <0x0 0x2260000 0x0 0x1000>;
435 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clockgen 4 1>;
437 clock-names = "ipg";
438 dma-names = "rx","tx";
439 dmas = <&edma0 1 32>,
440 <&edma0 1 33>;
441 status = "disabled";
442 };
444 lpuart1: serial@2270000 {
445 compatible = "fsl,ls1028a-lpuart";
446 reg = <0x0 0x2270000 0x0 0x1000>;
447 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&clockgen 4 1>;
449 clock-names = "ipg";
450 dma-names = "rx","tx";
451 dmas = <&edma0 1 30>,
452 <&edma0 1 31>;
453 status = "disabled";
454 };
456 lpuart2: serial@2280000 {
457 compatible = "fsl,ls1028a-lpuart";
458 reg = <0x0 0x2280000 0x0 0x1000>;
459 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&clockgen 4 1>;
461 clock-names = "ipg";
462 dma-names = "rx","tx";
463 dmas = <&edma0 1 28>,
464 <&edma0 1 29>;
465 status = "disabled";
466 };
468 lpuart3: serial@2290000 {
469 compatible = "fsl,ls1028a-lpuart";
470 reg = <0x0 0x2290000 0x0 0x1000>;
471 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&clockgen 4 1>;
473 clock-names = "ipg";
474 dma-names = "rx","tx";
475 dmas = <&edma0 1 26>,
476 <&edma0 1 27>;
477 status = "disabled";
478 };
480 lpuart4: serial@22a0000 {
481 compatible = "fsl,ls1028a-lpuart";
482 reg = <0x0 0x22a0000 0x0 0x1000>;
483 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clockgen 4 1>;
485 clock-names = "ipg";
486 dma-names = "rx","tx";
487 dmas = <&edma0 1 24>,
488 <&edma0 1 25>;
489 status = "disabled";
490 };
492 lpuart5: serial@22b0000 {
493 compatible = "fsl,ls1028a-lpuart";
494 reg = <0x0 0x22b0000 0x0 0x1000>;
495 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&clockgen 4 1>;
497 clock-names = "ipg";
498 dma-names = "rx","tx";
499 dmas = <&edma0 1 22>,
500 <&edma0 1 23>;
501 status = "disabled";
502 };
504 edma0: dma-controller@22c0000 {
505 #dma-cells = <2>;
506 compatible = "fsl,ls1028a-edma", "fsl,vf610-edma";
507 reg = <0x0 0x22c0000 0x0 0x10000>,
508 <0x0 0x22d0000 0x0 0x10000>,
509 <0x0 0x22e0000 0x0 0x10000>;
510 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
512 interrupt-names = "edma-tx", "edma-err";
513 dma-channels = <32>;
514 clock-names = "dmamux0", "dmamux1";
515 clocks = <&clockgen 4 1>,
516 <&clockgen 4 1>;
517 };
519 gpio1: gpio@2300000 {
520 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
521 reg = <0x0 0x2300000 0x0 0x10000>;
522 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
523 gpio-controller;
524 #gpio-cells = <2>;
525 interrupt-controller;
526 #interrupt-cells = <2>;
527 little-endian;
528 };
530 gpio2: gpio@2310000 {
531 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
532 reg = <0x0 0x2310000 0x0 0x10000>;
533 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
534 gpio-controller;
535 #gpio-cells = <2>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 little-endian;
539 };
541 gpio3: gpio@2320000 {
542 compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio";
543 reg = <0x0 0x2320000 0x0 0x10000>;
544 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
545 gpio-controller;
546 #gpio-cells = <2>;
547 interrupt-controller;
548 #interrupt-cells = <2>;
549 little-endian;
550 };
552 usb0: usb@3100000 {
553 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
554 reg = <0x0 0x3100000 0x0 0x10000>;
555 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
556 dr_mode = "host";
557 snps,dis_rxdet_inp3_quirk;
558 snps,quirk-frame-length-adjustment = <0x20>;
559 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
560 };
562 usb1: usb@3110000 {
563 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
564 reg = <0x0 0x3110000 0x0 0x10000>;
565 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
566 dr_mode = "host";
567 snps,dis_rxdet_inp3_quirk;
568 snps,quirk-frame-length-adjustment = <0x20>;
569 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
570 };
572 sata: sata@3200000 {
573 compatible = "fsl,ls1028a-ahci";
574 reg = <0x0 0x3200000 0x0 0x10000>,
575 <0x7 0x100520 0x0 0x4>;
576 reg-names = "ahci", "sata-ecc";
577 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clockgen 4 1>;
579 status = "disabled";
580 };
582 pcie1: pcie@3400000 {
583 compatible = "fsl,ls1028a-pcie";
584 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
585 0x80 0x00000000 0x0 0x00002000>; /* configuration space */
586 reg-names = "regs", "config";
587 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
588 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
589 interrupt-names = "pme", "aer";
590 #address-cells = <3>;
591 #size-cells = <2>;
592 device_type = "pci";
593 dma-coherent;
594 num-viewport = <8>;
595 bus-range = <0x0 0xff>;
596 ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */
597 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
598 msi-parent = <&its>;
599 #interrupt-cells = <1>;
600 interrupt-map-mask = <0 0 0 7>;
601 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
602 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
603 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
604 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
605 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
606 status = "disabled";
607 };
609 pcie2: pcie@3500000 {
610 compatible = "fsl,ls1028a-pcie";
611 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
612 0x88 0x00000000 0x0 0x00002000>; /* configuration space */
613 reg-names = "regs", "config";
614 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
616 interrupt-names = "pme", "aer";
617 #address-cells = <3>;
618 #size-cells = <2>;
619 device_type = "pci";
620 dma-coherent;
621 num-viewport = <8>;
622 bus-range = <0x0 0xff>;
623 ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */
624 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
625 msi-parent = <&its>;
626 #interrupt-cells = <1>;
627 interrupt-map-mask = <0 0 0 7>;
628 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
629 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
630 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
631 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
632 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
633 status = "disabled";
634 };
636 smmu: iommu@5000000 {
637 compatible = "arm,mmu-500";
638 reg = <0 0x5000000 0 0x800000>;
639 #global-interrupts = <8>;
640 #iommu-cells = <1>;
641 stream-match-mask = <0x7c00>;
642 /* global secure fault */
643 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
644 /* combined secure interrupt */
645 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
646 /* global non-secure fault */
647 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
648 /* combined non-secure interrupt */
649 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
650 /* performance counter interrupts 0-7 */
651 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
653 /* per context interrupt, 64 interrupts */
654 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
686 };
688 crypto: crypto@8000000 {
689 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
690 fsl,sec-era = <10>;
691 #address-cells = <1>;
692 #size-cells = <1>;
693 ranges = <0x0 0x00 0x8000000 0x100000>;
694 reg = <0x00 0x8000000 0x0 0x100000>;
695 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
696 dma-coherent;
698 sec_jr0: jr@10000 {
699 compatible = "fsl,sec-v5.0-job-ring",
700 "fsl,sec-v4.0-job-ring";
701 reg = <0x10000 0x10000>;
702 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
703 };
705 sec_jr1: jr@20000 {
706 compatible = "fsl,sec-v5.0-job-ring",
707 "fsl,sec-v4.0-job-ring";
708 reg = <0x20000 0x10000>;
709 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
710 };
712 sec_jr2: jr@30000 {
713 compatible = "fsl,sec-v5.0-job-ring",
714 "fsl,sec-v4.0-job-ring";
715 reg = <0x30000 0x10000>;
716 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
717 };
719 sec_jr3: jr@40000 {
720 compatible = "fsl,sec-v5.0-job-ring",
721 "fsl,sec-v4.0-job-ring";
722 reg = <0x40000 0x10000>;
723 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
724 };
725 };
727 qdma: dma-controller@8380000 {
728 compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma";
729 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
730 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
731 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
732 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
737 interrupt-names = "qdma-error", "qdma-queue0",
738 "qdma-queue1", "qdma-queue2", "qdma-queue3";
739 dma-channels = <8>;
740 block-number = <1>;
741 block-offset = <0x10000>;
742 fsl,dma-queues = <2>;
743 status-sizes = <64>;
744 queue-sizes = <64 64>;
745 };
747 cluster1_core0_watchdog: watchdog@c000000 {
748 compatible = "arm,sp805", "arm,primecell";
749 reg = <0x0 0xc000000 0x0 0x1000>;
750 clocks = <&clockgen 4 15>, <&clockgen 4 15>;
751 clock-names = "wdog_clk", "apb_pclk";
752 };
754 cluster1_core1_watchdog: watchdog@c010000 {
755 compatible = "arm,sp805", "arm,primecell";
756 reg = <0x0 0xc010000 0x0 0x1000>;
757 clocks = <&clockgen 4 15>, <&clockgen 4 15>;
758 clock-names = "wdog_clk", "apb_pclk";
759 };
761 sai1: audio-controller@f100000 {
762 #sound-dai-cells = <0>;
763 compatible = "fsl,vf610-sai";
764 reg = <0x0 0xf100000 0x0 0x10000>;
765 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
766 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
767 <&clockgen 4 1>, <&clockgen 4 1>;
768 clock-names = "bus", "mclk1", "mclk2", "mclk3";
769 dma-names = "tx", "rx";
770 dmas = <&edma0 1 4>,
771 <&edma0 1 3>;
772 fsl,sai-asynchronous;
773 status = "disabled";
774 };
776 sai2: audio-controller@f110000 {
777 #sound-dai-cells = <0>;
778 compatible = "fsl,vf610-sai";
779 reg = <0x0 0xf110000 0x0 0x10000>;
780 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
782 <&clockgen 4 1>, <&clockgen 4 1>;
783 clock-names = "bus", "mclk1", "mclk2", "mclk3";
784 dma-names = "tx", "rx";
785 dmas = <&edma0 1 6>,
786 <&edma0 1 5>;
787 fsl,sai-asynchronous;
788 status = "disabled";
789 };
791 sai3: audio-controller@f120000 {
792 #sound-dai-cells = <0>;
793 compatible = "fsl,vf610-sai";
794 reg = <0x0 0xf120000 0x0 0x10000>;
795 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
797 <&clockgen 4 1>, <&clockgen 4 1>;
798 clock-names = "bus", "mclk1", "mclk2", "mclk3";
799 dma-names = "tx", "rx";
800 dmas = <&edma0 1 8>,
801 <&edma0 1 7>;
802 fsl,sai-asynchronous;
803 status = "disabled";
804 };
806 sai4: audio-controller@f130000 {
807 #sound-dai-cells = <0>;
808 compatible = "fsl,vf610-sai";
809 reg = <0x0 0xf130000 0x0 0x10000>;
810 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
811 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
812 <&clockgen 4 1>, <&clockgen 4 1>;
813 clock-names = "bus", "mclk1", "mclk2", "mclk3";
814 dma-names = "tx", "rx";
815 dmas = <&edma0 1 10>,
816 <&edma0 1 9>;
817 fsl,sai-asynchronous;
818 status = "disabled";
819 };
821 sai5: audio-controller@f140000 {
822 #sound-dai-cells = <0>;
823 compatible = "fsl,vf610-sai";
824 reg = <0x0 0xf140000 0x0 0x10000>;
825 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
826 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
827 <&clockgen 4 1>, <&clockgen 4 1>;
828 clock-names = "bus", "mclk1", "mclk2", "mclk3";
829 dma-names = "tx", "rx";
830 dmas = <&edma0 1 12>,
831 <&edma0 1 11>;
832 fsl,sai-asynchronous;
833 status = "disabled";
834 };
836 sai6: audio-controller@f150000 {
837 #sound-dai-cells = <0>;
838 compatible = "fsl,vf610-sai";
839 reg = <0x0 0xf150000 0x0 0x10000>;
840 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
842 <&clockgen 4 1>, <&clockgen 4 1>;
843 clock-names = "bus", "mclk1", "mclk2", "mclk3";
844 dma-names = "tx", "rx";
845 dmas = <&edma0 1 14>,
846 <&edma0 1 13>;
847 fsl,sai-asynchronous;
848 status = "disabled";
849 };
851 tmu: tmu@1f80000 {
852 compatible = "fsl,qoriq-tmu";
853 reg = <0x0 0x1f80000 0x0 0x10000>;
854 interrupts = <0 23 0x4>;
855 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
856 fsl,tmu-calibration = <0x00000000 0x00000024
857 0x00000001 0x0000002b
858 0x00000002 0x00000031
859 0x00000003 0x00000038
860 0x00000004 0x0000003f
861 0x00000005 0x00000045
862 0x00000006 0x0000004c
863 0x00000007 0x00000053
864 0x00000008 0x00000059
865 0x00000009 0x00000060
866 0x0000000a 0x00000066
867 0x0000000b 0x0000006d
869 0x00010000 0x0000001c
870 0x00010001 0x00000024
871 0x00010002 0x0000002c
872 0x00010003 0x00000035
873 0x00010004 0x0000003d
874 0x00010005 0x00000045
875 0x00010006 0x0000004d
876 0x00010007 0x00000055
877 0x00010008 0x0000005e
878 0x00010009 0x00000066
879 0x0001000a 0x0000006e
881 0x00020000 0x00000018
882 0x00020001 0x00000022
883 0x00020002 0x0000002d
884 0x00020003 0x00000038
885 0x00020004 0x00000043
886 0x00020005 0x0000004d
887 0x00020006 0x00000058
888 0x00020007 0x00000063
889 0x00020008 0x0000006e
891 0x00030000 0x00000010
892 0x00030001 0x0000001c
893 0x00030002 0x00000029
894 0x00030003 0x00000036
895 0x00030004 0x00000042
896 0x00030005 0x0000004f
897 0x00030006 0x0000005b
898 0x00030007 0x00000068>;
899 little-endian;
900 #thermal-sensor-cells = <1>;
901 };
903 pcie@1f0000000 { /* Integrated Endpoint Root Complex */
904 compatible = "pci-host-ecam-generic";
905 reg = <0x01 0xf0000000 0x0 0x100000>;
906 #address-cells = <3>;
907 #size-cells = <2>;
908 msi-parent = <&its>;
909 device_type = "pci";
910 bus-range = <0x0 0x0>;
911 dma-coherent;
912 msi-map = <0 &its 0x17 0xe>;
913 iommu-map = <0 &smmu 0x17 0xe>;
914 /* PF0-6 BAR0 - non-prefetchable memory */
915 ranges = <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000
916 /* PF0-6 BAR2 - prefetchable memory */
917 0xc2000000 0x0 0x00000000 0x1 0xf8160000 0x0 0x070000
918 /* PF0: VF0-1 BAR0 - non-prefetchable memory */
919 0x82000000 0x0 0x00000000 0x1 0xf81d0000 0x0 0x020000
920 /* PF0: VF0-1 BAR2 - prefetchable memory */
921 0xc2000000 0x0 0x00000000 0x1 0xf81f0000 0x0 0x020000
922 /* PF1: VF0-1 BAR0 - non-prefetchable memory */
923 0x82000000 0x0 0x00000000 0x1 0xf8210000 0x0 0x020000
924 /* PF1: VF0-1 BAR2 - prefetchable memory */
925 0xc2000000 0x0 0x00000000 0x1 0xf8230000 0x0 0x020000
926 /* BAR4 (PF5) - non-prefetchable memory */
927 0x82000000 0x0 0x00000000 0x1 0xfc000000 0x0 0x400000>;
929 enetc_port0: ethernet@0,0 {
930 compatible = "fsl,enetc";
931 reg = <0x000000 0 0 0 0>;
932 status = "disabled";
933 };
935 enetc_port1: ethernet@0,1 {
936 compatible = "fsl,enetc";
937 reg = <0x000100 0 0 0 0>;
938 status = "disabled";
939 };
941 enetc_port2: ethernet@0,2 {
942 compatible = "fsl,enetc";
943 reg = <0x000200 0 0 0 0>;
944 phy-mode = "internal";
945 status = "disabled";
947 fixed-link {
948 speed = <1000>;
949 full-duplex;
950 };
951 };
953 enetc_mdio_pf3: mdio@0,3 {
954 compatible = "fsl,enetc-mdio";
955 reg = <0x000300 0 0 0 0>;
956 #address-cells = <1>;
957 #size-cells = <0>;
958 };
960 ethernet@0,4 {
961 compatible = "fsl,enetc-ptp";
962 reg = <0x000400 0 0 0 0>;
963 clocks = <&clockgen 2 3>;
964 little-endian;
965 fsl,extts-fifo;
966 };
968 mscc_felix: ethernet-switch@0,5 {
969 reg = <0x000500 0 0 0 0>;
970 /* IEP INT_B */
971 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
972 status = "disabled";
974 ports {
975 #address-cells = <1>;
976 #size-cells = <0>;
978 /* External ports */
979 mscc_felix_port0: port@0 {
980 reg = <0>;
981 status = "disabled";
982 };
984 mscc_felix_port1: port@1 {
985 reg = <1>;
986 status = "disabled";
987 };
989 mscc_felix_port2: port@2 {
990 reg = <2>;
991 status = "disabled";
992 };
994 mscc_felix_port3: port@3 {
995 reg = <3>;
996 status = "disabled";
997 };
999 /* Internal ports */
1000 mscc_felix_port4: port@4 {
1001 reg = <4>;
1002 phy-mode = "internal";
1003 status = "disabled";
1005 fixed-link {
1006 speed = <2500>;
1007 full-duplex;
1008 };
1009 };
1011 mscc_felix_port5: port@5 {
1012 reg = <5>;
1013 phy-mode = "internal";
1014 status = "disabled";
1016 fixed-link {
1017 speed = <1000>;
1018 full-duplex;
1019 };
1020 };
1021 };
1022 };
1024 enetc_port3: ethernet@0,6 {
1025 compatible = "fsl,enetc";
1026 reg = <0x000600 0 0 0 0>;
1027 phy-mode = "internal";
1028 status = "disabled";
1030 fixed-link {
1031 speed = <1000>;
1032 full-duplex;
1033 };
1034 };
1035 };
1037 rcpm: power-controller@1e34040 {
1038 compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
1039 reg = <0x0 0x1e34040 0x0 0x1c>;
1040 #fsl,rcpm-wakeup-cells = <7>;
1041 little-endian;
1042 };
1044 ftm_alarm0: timer@2800000 {
1045 compatible = "fsl,ls1028a-ftm-alarm";
1046 reg = <0x0 0x2800000 0x0 0x10000>;
1047 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1048 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1049 };
1050 };
1052 malidp0: display@f080000 {
1053 compatible = "arm,mali-dp500";
1054 reg = <0x0 0xf080000 0x0 0x10000>;
1055 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1056 <0 223 IRQ_TYPE_LEVEL_HIGH>;
1057 interrupt-names = "DE", "SE";
1058 clocks = <&dpclk>, <&clockgen 2 2>, <&clockgen 2 2>,
1059 <&clockgen 2 2>;
1060 clock-names = "pxlclk", "mclk", "aclk", "pclk";
1061 arm,malidp-output-port-lines = /bits/ 8 <8 8 8>;
1062 arm,malidp-arqos-value = <0xd000d000>;
1064 port {
1065 dp0_out: endpoint {
1067 };
1068 };
1069 };
1070 };