1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
5 * Copyright 2016 Freescale Semiconductor, Inc.
7 * Mingkai Hu <mingkai.hu@nxp.com>
12 #include "fsl-ls1046a.dtsi"
15 model = "LS1046A RDB Board";
16 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
26 stdout-path = "serial0:115200n8";
50 compatible = "ti,ina220";
52 shunt-resistor = <1000>;
56 compatible = "adi,adt7461";
61 compatible = "atmel,24c512";
66 compatible = "atmel,24c512";
75 compatible = "nxp,pcf2129";
83 /* NAND Flashe and CPLD on board */
84 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
85 0x2 0x0 0x0 0x7fb00000 0x00000100>;
89 compatible = "fsl,ifc-nand";
92 reg = <0x0 0x0 0x10000>;
95 cpld: board-control@2,0 {
96 compatible = "fsl,ls1046ardb-cpld";
97 reg = <0x2 0x0 0x0000100>;
104 s25fs512s0: flash@0 {
105 compatible = "jedec,spi-nor";
106 #address-cells = <1>;
108 spi-max-frequency = <50000000>;
109 spi-rx-bus-width = <4>;
110 spi-tx-bus-width = <1>;
114 s25fs512s1: flash@1 {
115 compatible = "jedec,spi-nor";
116 #address-cells = <1>;
118 spi-max-frequency = <50000000>;
119 spi-rx-bus-width = <4>;
120 spi-tx-bus-width = <1>;
129 #include "fsl-ls1046-post.dtsi"
133 phy-handle = <&rgmii_phy1>;
134 phy-connection-type = "rgmii-id";
138 phy-handle = <&rgmii_phy2>;
139 phy-connection-type = "rgmii-id";
143 phy-handle = <&sgmii_phy1>;
144 phy-connection-type = "sgmii";
148 phy-handle = <&sgmii_phy2>;
149 phy-connection-type = "sgmii";
152 ethernet@f0000 { /* 10GEC1 */
153 phy-handle = <&aqr106_phy>;
154 phy-connection-type = "xgmii";
157 ethernet@f2000 { /* 10GEC2 */
158 fixed-link = <0 1 1000 0 0>;
159 phy-connection-type = "xgmii";
163 rgmii_phy1: ethernet-phy@1 {
167 rgmii_phy2: ethernet-phy@2 {
171 sgmii_phy1: ethernet-phy@3 {
175 sgmii_phy2: ethernet-phy@4 {
181 aqr106_phy: ethernet-phy@0 {
182 compatible = "ethernet-phy-ieee802.3-c45";
183 interrupts = <0 131 4>;