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[linux/fpc-iii.git] / arch / arm64 / boot / dts / freescale / fsl-ls1046a-rdb.dts
blobd53ccc56bb639f7e8b638c36a4b0dd9bb2e5f940
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4  *
5  * Copyright 2016 Freescale Semiconductor, Inc.
6  *
7  * Mingkai Hu <mingkai.hu@nxp.com>
8  */
10 /dts-v1/;
12 #include "fsl-ls1046a.dtsi"
14 / {
15         model = "LS1046A RDB Board";
16         compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
18         aliases {
19                 serial0 = &duart0;
20                 serial1 = &duart1;
21                 serial2 = &duart2;
22                 serial3 = &duart3;
23         };
25         chosen {
26                 stdout-path = "serial0:115200n8";
27         };
30 &duart0 {
31         status = "okay";
34 &duart1 {
35         status = "okay";
38 &esdhc {
39         mmc-hs200-1_8v;
40         sd-uhs-sdr104;
41         sd-uhs-sdr50;
42         sd-uhs-sdr25;
43         sd-uhs-sdr12;
46 &i2c0 {
47         status = "okay";
49         ina220@40 {
50                 compatible = "ti,ina220";
51                 reg = <0x40>;
52                 shunt-resistor = <1000>;
53         };
55         temp-sensor@4c {
56                 compatible = "adi,adt7461";
57                 reg = <0x4c>;
58         };
60         eeprom@52 {
61                 compatible = "atmel,24c512";
62                 reg = <0x52>;
63         };
65         eeprom@53 {
66                 compatible = "atmel,24c512";
67                 reg = <0x53>;
68         };
71 &i2c3 {
72         status = "okay";
74         rtc@51 {
75                 compatible = "nxp,pcf2129";
76                 reg = <0x51>;
77         };
80 &ifc {
81         #address-cells = <2>;
82         #size-cells = <1>;
83         /* NAND Flashe and CPLD on board */
84         ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
85                   0x2 0x0 0x0 0x7fb00000 0x00000100>;
86         status = "okay";
88         nand@0,0 {
89                 compatible = "fsl,ifc-nand";
90                 #address-cells = <1>;
91                 #size-cells = <1>;
92                 reg = <0x0 0x0 0x10000>;
93         };
95         cpld: board-control@2,0 {
96                 compatible = "fsl,ls1046ardb-cpld";
97                 reg = <0x2 0x0 0x0000100>;
98         };
101 &qspi {
102         status = "okay";
104         s25fs512s0: flash@0 {
105                 compatible = "jedec,spi-nor";
106                 #address-cells = <1>;
107                 #size-cells = <1>;
108                 spi-max-frequency = <50000000>;
109                 spi-rx-bus-width = <4>;
110                 spi-tx-bus-width = <1>;
111                 reg = <0>;
112         };
114         s25fs512s1: flash@1 {
115                 compatible = "jedec,spi-nor";
116                 #address-cells = <1>;
117                 #size-cells = <1>;
118                 spi-max-frequency = <50000000>;
119                 spi-rx-bus-width = <4>;
120                 spi-tx-bus-width = <1>;
121                 reg = <1>;
122         };
125 &usb1 {
126         dr_mode = "otg";
129 #include "fsl-ls1046-post.dtsi"
131 &fman0 {
132         ethernet@e4000 {
133                 phy-handle = <&rgmii_phy1>;
134                 phy-connection-type = "rgmii-id";
135         };
137         ethernet@e6000 {
138                 phy-handle = <&rgmii_phy2>;
139                 phy-connection-type = "rgmii-id";
140         };
142         ethernet@e8000 {
143                 phy-handle = <&sgmii_phy1>;
144                 phy-connection-type = "sgmii";
145         };
147         ethernet@ea000 {
148                 phy-handle = <&sgmii_phy2>;
149                 phy-connection-type = "sgmii";
150         };
152         ethernet@f0000 { /* 10GEC1 */
153                 phy-handle = <&aqr106_phy>;
154                 phy-connection-type = "xgmii";
155         };
157         ethernet@f2000 { /* 10GEC2 */
158                 fixed-link = <0 1 1000 0 0>;
159                 phy-connection-type = "xgmii";
160         };
162         mdio@fc000 {
163                 rgmii_phy1: ethernet-phy@1 {
164                         reg = <0x1>;
165                 };
167                 rgmii_phy2: ethernet-phy@2 {
168                         reg = <0x2>;
169                 };
171                 sgmii_phy1: ethernet-phy@3 {
172                         reg = <0x3>;
173                 };
175                 sgmii_phy2: ethernet-phy@4 {
176                         reg = <0x4>;
177                 };
178         };
180         mdio@fd000 {
181                 aqr106_phy: ethernet-phy@0 {
182                         compatible = "ethernet-phy-ieee802.3-c45";
183                         interrupts = <0 131 4>;
184                         reg = <0x0>;
185                 };
186         };