1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright 2020 Compass Electronics Group, LLC
8 compatible = "gpio-leds";
12 gpios = <&pca6416_1 4 GPIO_ACTIVE_HIGH>;
13 default-state = "off";
18 gpios = <&pca6416_1 5 GPIO_ACTIVE_HIGH>;
19 default-state = "off";
24 gpios = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
25 default-state = "off";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_led3>;
32 gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
33 linux,default-trigger = "heartbeat";
37 reg_audio: regulator-audio {
38 compatible = "regulator-fixed";
39 regulator-name = "3v3_aud";
40 regulator-min-microvolt = <3300000>;
41 regulator-max-microvolt = <3300000>;
42 gpio = <&pca6416_1 11 GPIO_ACTIVE_HIGH>;
46 reg_usdhc2_vmmc: regulator-usdhc2 {
47 compatible = "regulator-fixed";
48 regulator-name = "VSD_3V3";
49 regulator-min-microvolt = <3300000>;
50 regulator-max-microvolt = <3300000>;
51 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
56 compatible = "fsl,imx-audio-wm8962";
57 model = "wm8962-audio";
59 audio-codec = <&wm8962>;
61 "Headphone Jack", "HPOUTL",
62 "Headphone Jack", "HPOUTR",
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_espi2>;
73 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
77 compatible = "microchip,at25160bn", "atmel,at25";
79 spi-max-frequency = <5000000>;
89 clock-frequency = <400000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_i2c2>;
96 clock-frequency = <400000>;
97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_i2c4>;
101 wm8962: audio-codec@1a {
102 compatible = "wlf,wm8962";
104 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
105 clock-names = "xclk";
106 DCVDD-supply = <®_audio>;
107 DBVDD-supply = <®_audio>;
108 AVDD-supply = <®_audio>;
109 CPVDD-supply = <®_audio>;
110 MICVDD-supply = <®_audio>;
111 PLLVDD-supply = <®_audio>;
112 SPKVDD1-supply = <®_audio>;
113 SPKVDD2-supply = <®_audio>;
115 0x0000 /* 0:Default */
116 0x0000 /* 1:Default */
117 0x0000 /* 2:FN_DMICCLK */
118 0x0000 /* 3:Default */
119 0x0000 /* 4:FN_DMICCDAT */
120 0x0000 /* 5:Default */
125 compatible = "nxp,pcal6416";
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_pcal6414>;
131 interrupt-parent = <&gpio4>;
132 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
136 compatible = "nxp,pcal6416";
140 interrupt-parent = <&gpio4>;
141 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
146 pinctrl-names = "default";
147 pinctrl-0 = <&pinctrl_sai3>;
148 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
149 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
150 assigned-clock-rates = <24576000>;
151 fsl,sai-mclk-direction-output;
159 &uart2 { /* console */
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_uart2>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_uart3>;
168 assigned-clocks = <&clk IMX8MM_CLK_UART3>;
169 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
174 pinctrl-names = "default", "state_100mhz", "state_200mhz";
175 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
176 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
177 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
179 vmmc-supply = <®_usdhc2_vmmc>;
184 pinctrl_espi2: espi2grp {
186 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
187 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
188 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
189 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x41
193 pinctrl_i2c2: i2c2grp {
195 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
196 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
200 pinctrl_i2c4: i2c4grp {
202 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
203 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
207 pinctrl_led3: led3grp {
209 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x41
213 pinctrl_pcal6414: pcal6414-gpiogrp {
215 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
219 pinctrl_sai3: sai3grp {
221 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
222 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
223 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
224 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
225 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
229 pinctrl_uart2: uart2grp {
231 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
232 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
236 pinctrl_uart3: uart3grp {
238 MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
239 MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
243 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
245 MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
246 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
250 pinctrl_usdhc2: usdhc2grp {
252 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
253 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
254 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
255 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
256 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
257 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
258 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
262 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
264 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
265 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
266 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
267 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
268 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
269 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
270 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
274 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
276 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
277 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
278 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
279 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
280 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
281 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
282 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0