WIP FPC-III support
[linux/fpc-iii.git] / arch / arm64 / boot / dts / freescale / imx8mm-beacon-som.dtsi
blobd897913537ca1f940b4cb4df7c0e5e62fe0fb758
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /*
3  * Copyright 2020 Compass Electronics Group, LLC
4  */
6 / {
7         aliases {
8                 rtc0 = &rtc;
9                 rtc1 = &snvs_rtc;
10         };
12         usdhc1_pwrseq: usdhc1_pwrseq {
13                 compatible = "mmc-pwrseq-simple";
14                 pinctrl-names = "default";
15                 pinctrl-0 = <&pinctrl_usdhc1_gpio>;
16                 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
17                 clocks = <&osc_32k>;
18                 clock-names = "ext_clock";
19                 post-power-on-delay-ms = <80>;
20         };
22         memory@40000000 {
23                 device_type = "memory";
24                 reg = <0x0 0x40000000 0 0x80000000>;
25         };
28 &A53_0 {
29         cpu-supply = <&buck2_reg>;
32 &A53_1 {
33         cpu-supply = <&buck2_reg>;
36 &A53_2 {
37         cpu-supply = <&buck2_reg>;
40 &A53_3 {
41         cpu-supply = <&buck2_reg>;
44 &ddrc {
45         operating-points-v2 = <&ddrc_opp_table>;
47         ddrc_opp_table: opp-table {
48                 compatible = "operating-points-v2";
50                 opp-25M {
51                         opp-hz = /bits/ 64 <25000000>;
52                 };
54                 opp-100M {
55                         opp-hz = /bits/ 64 <100000000>;
56                 };
58                 opp-750M {
59                         opp-hz = /bits/ 64 <750000000>;
60                 };
61         };
64 &fec1 {
65         pinctrl-names = "default";
66         pinctrl-0 = <&pinctrl_fec1>;
67         phy-mode = "rgmii-id";
68         phy-handle = <&ethphy0>;
69         fsl,magic-packet;
70         status = "okay";
72         mdio {
73                 #address-cells = <1>;
74                 #size-cells = <0>;
76                 ethphy0: ethernet-phy@0 {
77                         compatible = "ethernet-phy-ieee802.3-c22";
78                         reg = <0>;
79                 };
80         };
83 &flexspi {
84         pinctrl-names = "default";
85         pinctrl-0 = <&pinctrl_flexspi>;
86         status = "okay";
88         flash@0 {
89                 reg = <0>;
90                 #address-cells = <1>;
91                 #size-cells = <1>;
92                 compatible = "jedec,spi-nor";
93                 spi-max-frequency = <80000000>;
94                 spi-tx-bus-width = <4>;
95                 spi-rx-bus-width = <4>;
96         };
99 &i2c1 {
100         clock-frequency = <400000>;
101         pinctrl-names = "default";
102         pinctrl-0 = <&pinctrl_i2c1>;
103         status = "okay";
105         pmic@4b {
106                 compatible = "rohm,bd71847";
107                 reg = <0x4b>;
108                 pinctrl-names = "default";
109                 pinctrl-0 = <&pinctrl_pmic>;
110                 interrupt-parent = <&gpio1>;
111                 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
112                 rohm,reset-snvs-powered;
114                 #clock-cells = <0>;
115                 clocks = <&osc_32k 0>;
116                 clock-output-names = "clk-32k-out";
118                 regulators {
119                         buck1_reg: BUCK1 {
120                                 regulator-name = "buck1";
121                                 regulator-min-microvolt = <700000>;
122                                 regulator-max-microvolt = <1300000>;
123                                 regulator-boot-on;
124                                 regulator-always-on;
125                                 regulator-ramp-delay = <1250>;
126                         };
128                         buck2_reg: BUCK2 {
129                                 regulator-name = "buck2";
130                                 regulator-min-microvolt = <700000>;
131                                 regulator-max-microvolt = <1300000>;
132                                 regulator-boot-on;
133                                 regulator-always-on;
134                                 regulator-ramp-delay = <1250>;
135                                 rohm,dvs-run-voltage = <1000000>;
136                                 rohm,dvs-idle-voltage = <900000>;
137                         };
139                         buck3_reg: BUCK3 {
140                                 // BUCK5 in datasheet
141                                 regulator-name = "buck3";
142                                 regulator-min-microvolt = <700000>;
143                                 regulator-max-microvolt = <1350000>;
144                                 regulator-boot-on;
145                                 regulator-always-on;
146                         };
148                         buck4_reg: BUCK4 {
149                                 // BUCK6 in datasheet
150                                 regulator-name = "buck4";
151                                 regulator-min-microvolt = <3000000>;
152                                 regulator-max-microvolt = <3300000>;
153                                 regulator-boot-on;
154                                 regulator-always-on;
155                         };
157                         buck5_reg: BUCK5 {
158                                 // BUCK7 in datasheet
159                                 regulator-name = "buck5";
160                                 regulator-min-microvolt = <1605000>;
161                                 regulator-max-microvolt = <1995000>;
162                                 regulator-boot-on;
163                                 regulator-always-on;
164                         };
166                         buck6_reg: BUCK6 {
167                                 // BUCK8 in datasheet
168                                 regulator-name = "buck6";
169                                 regulator-min-microvolt = <800000>;
170                                 regulator-max-microvolt = <1400000>;
171                                 regulator-boot-on;
172                                 regulator-always-on;
173                         };
175                         ldo1_reg: LDO1 {
176                                 regulator-name = "ldo1";
177                                 regulator-min-microvolt = <1600000>;
178                                 regulator-max-microvolt = <3300000>;
179                                 regulator-boot-on;
180                                 regulator-always-on;
181                         };
183                         ldo2_reg: LDO2 {
184                                 regulator-name = "ldo2";
185                                 regulator-min-microvolt = <800000>;
186                                 regulator-max-microvolt = <900000>;
187                                 regulator-boot-on;
188                                 regulator-always-on;
189                         };
191                         ldo3_reg: LDO3 {
192                                 regulator-name = "ldo3";
193                                 regulator-min-microvolt = <1800000>;
194                                 regulator-max-microvolt = <3300000>;
195                                 regulator-boot-on;
196                                 regulator-always-on;
197                         };
199                         ldo4_reg: LDO4 {
200                                 regulator-name = "ldo4";
201                                 regulator-min-microvolt = <900000>;
202                                 regulator-max-microvolt = <1800000>;
203                                 regulator-boot-on;
204                                 regulator-always-on;
205                         };
207                         ldo6_reg: LDO6 {
208                                 regulator-name = "ldo6";
209                                 regulator-min-microvolt = <900000>;
210                                 regulator-max-microvolt = <1800000>;
211                                 regulator-boot-on;
212                                 regulator-always-on;
213                         };
214                 };
215         };
218 &i2c3 {
219         clock-frequency = <400000>;
220         pinctrl-names = "default";
221         pinctrl-0 = <&pinctrl_i2c3>;
222         status = "okay";
224         eeprom@50 {
225                 compatible = "microchip,24c64", "atmel,24c64";
226                 pagesize = <32>;
227                 read-only;      /* Manufacturing EEPROM programmed at factory */
228                 reg = <0x50>;
229         };
231         rtc: rtc@51 {
232                 compatible = "nxp,pcf85263";
233                 reg = <0x51>;
234         };
237 &uart1 {
238         pinctrl-names = "default";
239         pinctrl-0 = <&pinctrl_uart1>;
240         assigned-clocks = <&clk IMX8MM_CLK_UART1>;
241         assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
242         uart-has-rtscts;
243         status = "okay";
245         bluetooth {
246                 compatible = "brcm,bcm43438-bt";
247                 shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
248                 host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
249                 device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
250                 clocks = <&osc_32k>;
251                 max-speed = <4000000>;
252                 clock-names = "extclk";
253         };
256 &usdhc1 {
257         #address-cells = <1>;
258         #size-cells = <0>;
259         pinctrl-names = "default";
260         pinctrl-0 = <&pinctrl_usdhc1>;
261         bus-width = <4>;
262         non-removable;
263         cap-power-off-card;
264         pm-ignore-notify;
265         keep-power-in-suspend;
266         mmc-pwrseq = <&usdhc1_pwrseq>;
267         status = "okay";
269         brcmf: bcrmf@1 {
270                 reg = <1>;
271                 compatible = "brcm,bcm4329-fmac";
272                 pinctrl-names = "default";
273                 pinctrl-0 = <&pinctrl_wlan>;
274                 interrupt-parent = <&gpio2>;
275                 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
276                 interrupt-names = "host-wake";
277         };
280 &usdhc3 {
281         pinctrl-names = "default", "state_100mhz", "state_200mhz";
282         pinctrl-0 = <&pinctrl_usdhc3>;
283         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
284         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
285         bus-width = <8>;
286         non-removable;
287         status = "okay";
290 &wdog1 {
291         pinctrl-names = "default";
292         pinctrl-0 = <&pinctrl_wdog>;
293         fsl,ext-reset-output;
294         status = "okay";
297 &iomuxc {
298         pinctrl_fec1: fec1grp {
299                 fsl,pins = <
300                         MX8MM_IOMUXC_ENET_MDC_ENET1_MDC         0x3
301                         MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO       0x3
302                         MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3   0x1f
303                         MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2   0x1f
304                         MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1   0x1f
305                         MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0   0x1f
306                         MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3   0x91
307                         MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2   0x91
308                         MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1   0x91
309                         MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0   0x91
310                         MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC   0x1f
311                         MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC   0x91
312                         MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
313                         MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
314                         MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22        0x19
315                 >;
316         };
318         pinctrl_i2c1: i2c1grp {
319                 fsl,pins = <
320                         MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL          0x400001c3
321                         MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA          0x400001c3
322                 >;
323         };
325         pinctrl_i2c3: i2c3grp {
326                 fsl,pins = <
327                         MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL          0x400001c3
328                         MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA          0x400001c3
329                 >;
330         };
332         pinctrl_flexspi: flexspigrp {
333                 fsl,pins = <
334                         MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
335                         MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
336                         MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
337                         MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
338                         MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
339                         MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
340                 >;
341         };
343         pinctrl_pmic: pmicirqgrp {
344                 fsl,pins = <
345                         MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3       0x141
346                 >;
347         };
349         pinctrl_uart1: uart1grp {
350                 fsl,pins = <
351                         MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
352                         MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
353                         MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B  0x140
354                         MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B  0x140
355                         MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6        0x19
356                         MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7        0x19
357                         MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8        0x19
358                         MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K      0x141
359                 >;
360         };
362         pinctrl_usdhc1_gpio: usdhc1gpiogrp {
363                 fsl,pins = <
364                         MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10     0x41
365                 >;
366         };
368         pinctrl_usdhc1: usdhc1grp {
369                 fsl,pins = <
370                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x190
371                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d0
372                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d0
373                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d0
374                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d0
375                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d0
376                 >;
377         };
379         pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
380                 fsl,pins = <
381                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x194
382                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d4
383                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d4
384                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d4
385                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d4
386                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d4
387                 >;
388         };
390         pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
391                 fsl,pins = <
392                         MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK         0x196
393                         MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD         0x1d6
394                         MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0     0x1d6
395                         MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1     0x1d6
396                         MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2     0x1d6
397                         MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3     0x1d6
398                 >;
399         };
401         pinctrl_usdhc3: usdhc3grp {
402                 fsl,pins = <
403                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
404                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
405                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
406                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
407                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
408                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
409                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
410                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
411                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
412                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
413                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
414                 >;
415         };
417         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
418                 fsl,pins = <
419                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
420                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
421                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
422                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
423                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
424                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
425                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
426                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
427                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
428                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
429                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
430                 >;
431         };
433         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
434                 fsl,pins = <
435                         MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
436                         MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
437                         MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
438                         MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
439                         MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
440                         MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
441                         MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
442                         MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
443                         MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
444                         MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
445                         MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
446                 >;
447         };
449         pinctrl_wdog: wdoggrp {
450                 fsl,pins = <
451                         MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B            0x166
452                 >;
453         };
455         pinctrl_wlan: wlangrp {
456                 fsl,pins = <
457                         MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9                0x111
458                 >;
459         };