1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/usb/pd.h>
17 device_type = "memory";
18 reg = <0x0 0x40000000 0 0x80000000>;
22 compatible = "gpio-leds";
23 pinctrl-names = "default";
24 pinctrl-0 = <&pinctrl_gpio_led>;
28 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
33 reg_usdhc2_vmmc: regulator-usdhc2 {
34 compatible = "regulator-fixed";
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
37 regulator-name = "VSD_3V3";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
45 compatible = "gpio-ir-receiver";
46 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
47 pinctrl-names = "default";
48 pinctrl-0 = <&pinctrl_ir>;
49 linux,autosuspend-period = <125>;
53 #sound-dai-cells = <0>;
54 compatible = "wlf,wm8524";
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_gpio_wlf>;
57 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
61 compatible = "simple-audio-card";
62 simple-audio-card,name = "wm8524-audio";
63 simple-audio-card,format = "i2s";
64 simple-audio-card,frame-master = <&cpudai>;
65 simple-audio-card,bitclock-master = <&cpudai>;
66 simple-audio-card,widgets =
67 "Line", "Left Line Out Jack",
68 "Line", "Right Line Out Jack";
69 simple-audio-card,routing =
70 "Left Line Out Jack", "LINEVOUTL",
71 "Right Line Out Jack", "LINEVOUTR";
73 cpudai: simple-audio-card,cpu {
75 dai-tdm-slot-num = <2>;
76 dai-tdm-slot-width = <32>;
79 simple-audio-card,codec {
80 sound-dai = <&wm8524>;
81 clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
87 cpu-supply = <&buck2_reg>;
91 cpu-supply = <&buck2_reg>;
95 cpu-supply = <&buck2_reg>;
99 cpu-supply = <&buck2_reg>;
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_fec1>;
105 phy-mode = "rgmii-id";
106 phy-handle = <ðphy0>;
111 #address-cells = <1>;
114 ethphy0: ethernet-phy@0 {
115 compatible = "ethernet-phy-ieee802.3-c22";
117 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
118 reset-assert-us = <10000>;
124 clock-frequency = <400000>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&pinctrl_i2c1>;
130 compatible = "rohm,bd71847";
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pmic>;
134 interrupt-parent = <&gpio1>;
135 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
136 rohm,reset-snvs-powered;
139 clocks = <&osc_32k 0>;
140 clock-output-names = "clk-32k-out";
144 regulator-name = "buck1";
145 regulator-min-microvolt = <700000>;
146 regulator-max-microvolt = <1300000>;
149 regulator-ramp-delay = <1250>;
153 regulator-name = "buck2";
154 regulator-min-microvolt = <700000>;
155 regulator-max-microvolt = <1300000>;
158 regulator-ramp-delay = <1250>;
159 rohm,dvs-run-voltage = <1000000>;
160 rohm,dvs-idle-voltage = <900000>;
164 // BUCK5 in datasheet
165 regulator-name = "buck3";
166 regulator-min-microvolt = <700000>;
167 regulator-max-microvolt = <1350000>;
173 // BUCK6 in datasheet
174 regulator-name = "buck4";
175 regulator-min-microvolt = <3000000>;
176 regulator-max-microvolt = <3300000>;
182 // BUCK7 in datasheet
183 regulator-name = "buck5";
184 regulator-min-microvolt = <1605000>;
185 regulator-max-microvolt = <1995000>;
191 // BUCK8 in datasheet
192 regulator-name = "buck6";
193 regulator-min-microvolt = <800000>;
194 regulator-max-microvolt = <1400000>;
200 regulator-name = "ldo1";
201 regulator-min-microvolt = <1600000>;
202 regulator-max-microvolt = <3300000>;
208 regulator-name = "ldo2";
209 regulator-min-microvolt = <800000>;
210 regulator-max-microvolt = <900000>;
216 regulator-name = "ldo3";
217 regulator-min-microvolt = <1800000>;
218 regulator-max-microvolt = <3300000>;
224 regulator-name = "ldo4";
225 regulator-min-microvolt = <900000>;
226 regulator-max-microvolt = <1800000>;
232 regulator-name = "ldo6";
233 regulator-min-microvolt = <900000>;
234 regulator-max-microvolt = <1800000>;
243 clock-frequency = <400000>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c2>;
249 compatible = "nxp,ptn5110";
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_typec1>;
253 interrupt-parent = <&gpio2>;
258 typec1_dr_sw: endpoint {
259 remote-endpoint = <&usb1_drd_sw>;
263 typec1_con: connector {
264 compatible = "usb-c-connector";
268 try-power-role = "sink";
269 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
270 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
271 PDO_VAR(5000, 20000, 3000)>;
272 op-sink-microwatt = <15000000>;
279 clock-frequency = <400000>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_i2c3>;
285 compatible = "ti,tca6416";
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_sai3>;
295 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
296 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
297 assigned-clock-rates = <24576000>;
305 &uart2 { /* console */
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_uart2>;
317 samsung,picophy-pre-emp-curr-control = <3>;
318 samsung,picophy-dc-vol-level-adjust = <7>;
322 usb1_drd_sw: endpoint {
323 remote-endpoint = <&typec1_dr_sw>;
329 assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
330 assigned-clock-rates = <200000000>;
331 pinctrl-names = "default", "state_100mhz", "state_200mhz";
332 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
333 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
334 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
335 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
337 vmmc-supply = <®_usdhc2_vmmc>;
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_wdog>;
344 fsl,ext-reset-output;
349 pinctrl_fec1: fec1grp {
351 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
352 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
353 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
354 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
355 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
356 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
357 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
358 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
359 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
360 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
361 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
362 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
363 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
364 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
365 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
369 pinctrl_gpio_led: gpioledgrp {
371 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
377 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
381 pinctrl_gpio_wlf: gpiowlfgrp {
383 MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
387 pinctrl_i2c1: i2c1grp {
389 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
390 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
394 pinctrl_i2c2: i2c2grp {
396 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
397 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
401 pinctrl_i2c3: i2c3grp {
403 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
404 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
408 pinctrl_pmic: pmicirqgrp {
410 MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
414 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
416 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
420 pinctrl_sai3: sai3grp {
422 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
423 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
424 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
425 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
429 pinctrl_typec1: typec1grp {
431 MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
435 pinctrl_uart2: uart2grp {
437 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
438 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
442 pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
444 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
448 pinctrl_usdhc2: usdhc2grp {
450 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
451 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
452 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
453 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
454 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
455 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
456 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
460 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
462 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
463 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
464 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
465 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
466 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
467 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
468 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
472 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
474 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
475 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
476 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
477 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
478 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
479 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
480 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
484 pinctrl_wdog: wdoggrp {
486 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166