arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019-2020 Variscite Ltd.
   4  * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
   5  */
   6
   7 /dts-v1/;
   8
   9 #include "imx8mn-var-som.dtsi"
  10
  11 / {
  12         model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
  13         compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
  14
  15         reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
  16                 compatible = "regulator-fixed";
  17                 pinctrl-names = "default";
  18                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  19                 regulator-name = "VSD_3V3";
  20                 regulator-min-microvolt = <3300000>;
  21                 regulator-max-microvolt = <3300000>;
  22                 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
  23                 enable-active-high;
  24         };
  25
  26         gpio-keys {
  27                 compatible = "gpio-keys";
  28
  29                 back {
  30                         label = "Back";
  31                         gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
  32                         linux,code = <KEY_BACK>;
  33                 };
  34
  35                 home {
  36                         label = "Home";
  37                         gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
  38                         linux,code = <KEY_HOME>;
  39                 };
  40
  41                 menu {
  42                         label = "Menu";
  43                         gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
  44                         linux,code = <KEY_MENU>;
  45                 };
  46         };
  47
  48         leds {
  49                 compatible = "gpio-leds";
  50
  51                 led {
  52                         label = "Heartbeat";
  53                         gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
  54                         linux,default-trigger = "heartbeat";
  55                 };
  56         };
  57 };
  58
  59 &ethphy {
  60         reset-gpios = <&pca9534 5 GPIO_ACTIVE_HIGH>;
  61 };
  62
  63 &i2c2 {
  64         clock-frequency = <400000>;
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_i2c2>;
  67         status = "okay";
  68
  69         pca9534: gpio@20 {
  70                 compatible = "nxp,pca9534";
  71                 reg = <0x20>;
  72                 gpio-controller;
  73                 pinctrl-names = "default";
  74                 pinctrl-0 = <&pinctrl_pca9534>;
  75                 interrupt-parent = <&gpio1>;
  76                 interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
  77                 #gpio-cells = <2>;
  78                 wakeup-source;
  79
  80                 /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
  81                 usb3-sata-sel-hog {
  82                         gpio-hog;
  83                         gpios = <4 GPIO_ACTIVE_HIGH>;
  84                         output-low;
  85                         line-name = "usb3_sata_sel";
  86                 };
  87
  88                 som-vselect-hog {
  89                         gpio-hog;
  90                         gpios = <6 GPIO_ACTIVE_HIGH>;
  91                         output-low;
  92                         line-name = "som_vselect";
  93                 };
  94
  95                 enet-sel-hog {
  96                         gpio-hog;
  97                         gpios = <7 GPIO_ACTIVE_HIGH>;
  98                         output-low;
  99                         line-name = "enet_sel";
 100                 };
 101         };
 102
 103         extcon_usbotg1: typec@3d {
 104                 compatible = "nxp,ptn5150";
 105                 reg = <0x3d>;
 106                 interrupt-parent = <&gpio1>;
 107                 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 108                 pinctrl-names = "default";
 109                 pinctrl-0 = <&pinctrl_ptn5150>;
 110                 status = "okay";
 111         };
 112 };
 113
 114 &i2c3 {
 115         /* Capacitive touch controller */
 116         ft5x06_ts: touchscreen@38 {
 117                 compatible = "edt,edt-ft5406";
 118                 reg = <0x38>;
 119                 pinctrl-names = "default";
 120                 pinctrl-0 = <&pinctrl_captouch>;
 121                 interrupt-parent = <&gpio5>;
 122                 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 123
 124                 touchscreen-size-x = <800>;
 125                 touchscreen-size-y = <480>;
 126                 touchscreen-inverted-x;
 127                 touchscreen-inverted-y;
 128         };
 129
 130         rtc@68 {
 131                 compatible = "dallas,ds1337";
 132                 reg = <0x68>;
 133         };
 134 };
 135
 136 /* Header */
 137 &uart1 {
 138         pinctrl-names = "default";
 139         pinctrl-0 = <&pinctrl_uart1>;
 140         status = "okay";
 141 };
 142
 143 /* Header */
 144 &uart3 {
 145         pinctrl-names = "default";
 146         pinctrl-0 = <&pinctrl_uart3>;
 147         status = "okay";
 148 };
 149
 150 &usbotg1 {
 151         disable-over-current;
 152         extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
 153 };
 154
 155 &pinctrl_fec1 {
 156         fsl,pins = <
 157                 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC                 0x3
 158                 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO               0x3
 159                 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3           0x1f
 160                 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2           0x1f
 161                 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1           0x1f
 162                 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0           0x1f
 163                 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3           0x91
 164                 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2           0x91
 165                 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1           0x91
 166                 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0           0x91
 167                 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC           0x1f
 168                 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC           0x91
 169                 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL     0x91
 170                 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL     0x1f
 171                 /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
 172         >;
 173 };
 174
 175 &pinctrl_fec1_sleep {
 176         fsl,pins = <
 177                 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16                0x120
 178                 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17               0x120
 179                 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18                0x120
 180                 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19                0x120
 181                 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20                0x120
 182                 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21                0x120
 183                 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29                0x120
 184                 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28                0x120
 185                 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27                0x120
 186                 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26                0x120
 187                 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23                0x120
 188                 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25                0x120
 189                 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24             0x120
 190                 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22             0x120
 191                 /* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
 192         >;
 193 };
 194
 195 &iomuxc {
 196         pinctrl_captouch: captouchgrp {
 197                 fsl,pins = <
 198                         MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4         0x16
 199                 >;
 200         };
 201
 202         pinctrl_i2c2: i2c2grp {
 203                 fsl,pins = <
 204                         MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL          0x400001c3
 205                         MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA          0x400001c3
 206                 >;
 207         };
 208
 209         pinctrl_pca9534: pca9534grp {
 210                 fsl,pins = <
 211                         MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7       0x16
 212                 >;
 213         };
 214
 215         pinctrl_ptn5150: ptn5150grp {
 216                 fsl,pins = <
 217                         MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11      0x16
 218                 >;
 219         };
 220
 221         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 222                 fsl,pins = <
 223                         MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22        0x41
 224                 >;
 225         };
 226
 227         pinctrl_uart1: uart1grp {
 228                 fsl,pins = <
 229                         MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX     0x140
 230                         MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX     0x140
 231                 >;
 232         };
 233
 234         pinctrl_uart3: uart3grp {
 235                 fsl,pins = <
 236                         MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX     0x140
 237                         MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX     0x140
 238                 >;
 239         };
 240 };