| blob | ee1790230490d418d603aaa19da047b231631000 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mn-pinfunc.h"
14 / {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
19 aliases {
20 ethernet0 = &fec1;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 mmc0 = &usdhc1;
31 mmc1 = &usdhc2;
32 mmc2 = &usdhc3;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 spi0 = &ecspi1;
38 spi1 = &ecspi2;
39 spi2 = &ecspi3;
40 };
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
46 idle-states {
47 entry-method = "psci";
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
63 clock-latency = <61036>;
64 clocks = <&clk IMX8MN_CLK_ARM>;
65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
67 operating-points-v2 = <&a53_opp_table>;
68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
70 cpu-idle-states = <&cpu_pd_wait>;
71 #cooling-cells = <2>;
72 };
74 A53_1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
78 clock-latency = <61036>;
79 clocks = <&clk IMX8MN_CLK_ARM>;
80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
82 operating-points-v2 = <&a53_opp_table>;
83 cpu-idle-states = <&cpu_pd_wait>;
84 #cooling-cells = <2>;
85 };
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
91 clock-latency = <61036>;
92 clocks = <&clk IMX8MN_CLK_ARM>;
93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
95 operating-points-v2 = <&a53_opp_table>;
96 cpu-idle-states = <&cpu_pd_wait>;
97 #cooling-cells = <2>;
98 };
100 A53_3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x3>;
104 clock-latency = <61036>;
105 clocks = <&clk IMX8MN_CLK_ARM>;
106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
108 operating-points-v2 = <&a53_opp_table>;
109 cpu-idle-states = <&cpu_pd_wait>;
110 #cooling-cells = <2>;
111 };
113 A53_L2: l2-cache0 {
114 compatible = "cache";
115 };
116 };
118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <850000>;
125 opp-supported-hw = <0xb00>, <0x7>;
126 clock-latency-ns = <150000>;
127 opp-suspend;
128 };
130 opp-1400000000 {
131 opp-hz = /bits/ 64 <1400000000>;
132 opp-microvolt = <950000>;
133 opp-supported-hw = <0x300>, <0x7>;
134 clock-latency-ns = <150000>;
135 opp-suspend;
136 };
138 opp-1500000000 {
139 opp-hz = /bits/ 64 <1500000000>;
140 opp-microvolt = <1000000>;
141 opp-supported-hw = <0x100>, <0x3>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
144 };
145 };
147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
152 };
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
159 };
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
166 };
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
173 };
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
180 };
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
187 };
189 pmu {
190 compatible = "arm,cortex-a53-pmu";
191 interrupts = <GIC_PPI 7
192 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
193 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
194 };
196 psci {
197 compatible = "arm,psci-1.0";
198 method = "smc";
199 };
201 thermal-zones {
202 cpu-thermal {
203 polling-delay-passive = <250>;
204 polling-delay = <2000>;
205 thermal-sensors = <&tmu>;
206 trips {
207 cpu_alert0: trip0 {
208 temperature = <85000>;
209 hysteresis = <2000>;
210 type = "passive";
211 };
213 cpu_crit0: trip1 {
214 temperature = <95000>;
215 hysteresis = <2000>;
216 type = "critical";
217 };
218 };
220 cooling-maps {
221 map0 {
222 trip = <&cpu_alert0>;
223 cooling-device =
224 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
225 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
226 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
227 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
228 };
229 };
230 };
231 };
233 timer {
234 compatible = "arm,armv8-timer";
235 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
236 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
237 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
238 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
239 clock-frequency = <8000000>;
240 arm,no-tick-in-suspend;
241 };
243 soc@0 {
244 compatible = "simple-bus";
245 #address-cells = <1>;
246 #size-cells = <1>;
247 ranges = <0x0 0x0 0x0 0x3e000000>;
249 aips1: bus@30000000 {
250 compatible = "fsl,aips-bus", "simple-bus";
251 reg = <0x30000000 0x400000>;
252 #address-cells = <1>;
253 #size-cells = <1>;
254 ranges;
256 spba: bus@30000000 {
257 compatible = "fsl,spba-bus", "simple-bus";
258 #address-cells = <1>;
259 #size-cells = <1>;
260 reg = <0x30000000 0x100000>;
261 ranges;
263 sai2: sai@30020000 {
264 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
265 reg = <0x30020000 0x10000>;
266 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
267 clocks = <&clk IMX8MN_CLK_SAI2_IPG>,
268 <&clk IMX8MN_CLK_DUMMY>,
269 <&clk IMX8MN_CLK_SAI2_ROOT>,
270 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
271 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
272 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
273 dma-names = "rx", "tx";
274 status = "disabled";
275 };
277 sai3: sai@30030000 {
278 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
279 reg = <0x30030000 0x10000>;
280 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
281 clocks = <&clk IMX8MN_CLK_SAI3_IPG>,
282 <&clk IMX8MN_CLK_DUMMY>,
283 <&clk IMX8MN_CLK_SAI3_ROOT>,
284 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
285 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
286 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
287 dma-names = "rx", "tx";
288 status = "disabled";
289 };
291 sai5: sai@30050000 {
292 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
293 reg = <0x30050000 0x10000>;
294 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&clk IMX8MN_CLK_SAI5_IPG>,
296 <&clk IMX8MN_CLK_DUMMY>,
297 <&clk IMX8MN_CLK_SAI5_ROOT>,
298 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
299 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
300 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
301 dma-names = "rx", "tx";
302 fsl,shared-interrupt;
303 fsl,dataline = <0 0xf 0xf>;
304 status = "disabled";
305 };
307 sai6: sai@30060000 {
308 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
309 reg = <0x30060000 0x10000>;
310 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
311 clocks = <&clk IMX8MN_CLK_SAI6_IPG>,
312 <&clk IMX8MN_CLK_DUMMY>,
313 <&clk IMX8MN_CLK_SAI6_ROOT>,
314 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
315 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
316 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
317 dma-names = "rx", "tx";
318 status = "disabled";
319 };
321 micfil: audio-controller@30080000 {
322 compatible = "fsl,imx8mm-micfil";
323 reg = <0x30080000 0x10000>;
324 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&clk IMX8MN_CLK_PDM_IPG>,
329 <&clk IMX8MN_CLK_PDM_ROOT>,
330 <&clk IMX8MN_AUDIO_PLL1_OUT>,
331 <&clk IMX8MN_AUDIO_PLL2_OUT>,
332 <&clk IMX8MN_CLK_EXT3>;
333 clock-names = "ipg_clk", "ipg_clk_app",
334 "pll8k", "pll11k", "clkext3";
335 dmas = <&sdma2 24 25 0x80000000>;
336 dma-names = "rx";
337 status = "disabled";
338 };
340 spdif1: spdif@30090000 {
341 compatible = "fsl,imx35-spdif";
342 reg = <0x30090000 0x10000>;
343 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&clk IMX8MN_CLK_AUDIO_AHB>, /* core */
345 <&clk IMX8MN_CLK_24M>, /* rxtx0 */
346 <&clk IMX8MN_CLK_SPDIF1>, /* rxtx1 */
347 <&clk IMX8MN_CLK_DUMMY>, /* rxtx2 */
348 <&clk IMX8MN_CLK_DUMMY>, /* rxtx3 */
349 <&clk IMX8MN_CLK_DUMMY>, /* rxtx4 */
350 <&clk IMX8MN_CLK_AUDIO_AHB>, /* rxtx5 */
351 <&clk IMX8MN_CLK_DUMMY>, /* rxtx6 */
352 <&clk IMX8MN_CLK_DUMMY>, /* rxtx7 */
353 <&clk IMX8MN_CLK_DUMMY>; /* spba */
354 clock-names = "core", "rxtx0",
355 "rxtx1", "rxtx2",
356 "rxtx3", "rxtx4",
357 "rxtx5", "rxtx6",
358 "rxtx7", "spba";
359 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
360 dma-names = "rx", "tx";
361 status = "disabled";
362 };
364 sai7: sai@300b0000 {
365 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
366 reg = <0x300b0000 0x10000>;
367 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clk IMX8MN_CLK_SAI7_IPG>,
369 <&clk IMX8MN_CLK_DUMMY>,
370 <&clk IMX8MN_CLK_SAI7_ROOT>,
371 <&clk IMX8MN_CLK_DUMMY>, <&clk IMX8MN_CLK_DUMMY>;
372 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
373 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
374 dma-names = "rx", "tx";
375 status = "disabled";
376 };
378 easrc: easrc@300c0000 {
379 compatible = "fsl,imx8mn-easrc";
380 reg = <0x300c0000 0x10000>;
381 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&clk IMX8MN_CLK_ASRC_ROOT>;
383 clock-names = "mem";
384 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
385 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
386 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
387 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
388 dma-names = "ctx0_rx", "ctx0_tx",
389 "ctx1_rx", "ctx1_tx",
390 "ctx2_rx", "ctx2_tx",
391 "ctx3_rx", "ctx3_tx";
392 firmware-name = "imx/easrc/easrc-imx8mn.bin";
393 fsl,asrc-rate = <8000>;
394 fsl,asrc-format = <2>;
395 status = "disabled";
396 };
397 };
399 gpio1: gpio@30200000 {
400 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
401 reg = <0x30200000 0x10000>;
402 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&clk IMX8MN_CLK_GPIO1_ROOT>;
405 gpio-controller;
406 #gpio-cells = <2>;
407 interrupt-controller;
408 #interrupt-cells = <2>;
409 gpio-ranges = <&iomuxc 0 10 30>;
410 };
412 gpio2: gpio@30210000 {
413 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
414 reg = <0x30210000 0x10000>;
415 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
417 clocks = <&clk IMX8MN_CLK_GPIO2_ROOT>;
418 gpio-controller;
419 #gpio-cells = <2>;
420 interrupt-controller;
421 #interrupt-cells = <2>;
422 gpio-ranges = <&iomuxc 0 40 21>;
423 };
425 gpio3: gpio@30220000 {
426 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
427 reg = <0x30220000 0x10000>;
428 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clk IMX8MN_CLK_GPIO3_ROOT>;
431 gpio-controller;
432 #gpio-cells = <2>;
433 interrupt-controller;
434 #interrupt-cells = <2>;
435 gpio-ranges = <&iomuxc 0 61 26>;
436 };
438 gpio4: gpio@30230000 {
439 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
440 reg = <0x30230000 0x10000>;
441 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&clk IMX8MN_CLK_GPIO4_ROOT>;
444 gpio-controller;
445 #gpio-cells = <2>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 gpio-ranges = <&iomuxc 21 108 11>;
449 };
451 gpio5: gpio@30240000 {
452 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
453 reg = <0x30240000 0x10000>;
454 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&clk IMX8MN_CLK_GPIO5_ROOT>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupt-controller;
460 #interrupt-cells = <2>;
461 gpio-ranges = <&iomuxc 0 119 30>;
462 };
464 tmu: tmu@30260000 {
465 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
466 reg = <0x30260000 0x10000>;
467 clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
468 #thermal-sensor-cells = <0>;
469 };
471 wdog1: watchdog@30280000 {
472 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
473 reg = <0x30280000 0x10000>;
474 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk IMX8MN_CLK_WDOG1_ROOT>;
476 status = "disabled";
477 };
479 wdog2: watchdog@30290000 {
480 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
481 reg = <0x30290000 0x10000>;
482 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
483 clocks = <&clk IMX8MN_CLK_WDOG2_ROOT>;
484 status = "disabled";
485 };
487 wdog3: watchdog@302a0000 {
488 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
489 reg = <0x302a0000 0x10000>;
490 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&clk IMX8MN_CLK_WDOG3_ROOT>;
492 status = "disabled";
493 };
495 sdma3: dma-controller@302b0000 {
496 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
497 reg = <0x302b0000 0x10000>;
498 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clk IMX8MN_CLK_SDMA3_ROOT>,
500 <&clk IMX8MN_CLK_SDMA3_ROOT>;
501 clock-names = "ipg", "ahb";
502 #dma-cells = <3>;
503 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
504 };
506 sdma2: dma-controller@302c0000 {
507 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
508 reg = <0x302c0000 0x10000>;
509 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&clk IMX8MN_CLK_SDMA2_ROOT>,
511 <&clk IMX8MN_CLK_SDMA2_ROOT>;
512 clock-names = "ipg", "ahb";
513 #dma-cells = <3>;
514 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
515 };
517 iomuxc: pinctrl@30330000 {
518 compatible = "fsl,imx8mn-iomuxc";
519 reg = <0x30330000 0x10000>;
520 };
522 gpr: iomuxc-gpr@30340000 {
523 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
524 reg = <0x30340000 0x10000>;
525 };
527 ocotp: efuse@30350000 {
528 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
529 reg = <0x30350000 0x10000>;
530 clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
531 #address-cells = <1>;
532 #size-cells = <1>;
534 cpu_speed_grade: speed-grade@10 {
535 reg = <0x10 4>;
536 };
537 };
539 anatop: anatop@30360000 {
540 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop",
541 "syscon";
542 reg = <0x30360000 0x10000>;
543 };
545 snvs: snvs@30370000 {
546 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
547 reg = <0x30370000 0x10000>;
549 snvs_rtc: snvs-rtc-lp {
550 compatible = "fsl,sec-v4.0-mon-rtc-lp";
551 regmap = <&snvs>;
552 offset = <0x34>;
553 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
556 clock-names = "snvs-rtc";
557 };
559 snvs_pwrkey: snvs-powerkey {
560 compatible = "fsl,sec-v4.0-pwrkey";
561 regmap = <&snvs>;
562 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&clk IMX8MN_CLK_SNVS_ROOT>;
564 clock-names = "snvs-pwrkey";
565 linux,keycode = <KEY_POWER>;
566 wakeup-source;
567 status = "disabled";
568 };
569 };
571 clk: clock-controller@30380000 {
572 compatible = "fsl,imx8mn-ccm";
573 reg = <0x30380000 0x10000>;
574 #clock-cells = <1>;
575 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
576 <&clk_ext3>, <&clk_ext4>;
577 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
578 "clk_ext3", "clk_ext4";
579 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
580 <&clk IMX8MN_CLK_A53_CORE>,
581 <&clk IMX8MN_CLK_NOC>,
582 <&clk IMX8MN_CLK_AUDIO_AHB>,
583 <&clk IMX8MN_CLK_IPG_AUDIO_ROOT>,
584 <&clk IMX8MN_SYS_PLL3>;
585 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
586 <&clk IMX8MN_ARM_PLL_OUT>,
587 <&clk IMX8MN_SYS_PLL3_OUT>,
588 <&clk IMX8MN_SYS_PLL1_800M>;
589 assigned-clock-rates = <0>, <0>, <0>,
590 <400000000>,
591 <400000000>,
592 <600000000>;
593 };
595 src: reset-controller@30390000 {
596 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
597 reg = <0x30390000 0x10000>;
598 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
599 #reset-cells = <1>;
600 };
601 };
603 aips2: bus@30400000 {
604 compatible = "fsl,aips-bus", "simple-bus";
605 reg = <0x30400000 0x400000>;
606 #address-cells = <1>;
607 #size-cells = <1>;
608 ranges;
610 pwm1: pwm@30660000 {
611 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
612 reg = <0x30660000 0x10000>;
613 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&clk IMX8MN_CLK_PWM1_ROOT>,
615 <&clk IMX8MN_CLK_PWM1_ROOT>;
616 clock-names = "ipg", "per";
617 #pwm-cells = <2>;
618 status = "disabled";
619 };
621 pwm2: pwm@30670000 {
622 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
623 reg = <0x30670000 0x10000>;
624 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clk IMX8MN_CLK_PWM2_ROOT>,
626 <&clk IMX8MN_CLK_PWM2_ROOT>;
627 clock-names = "ipg", "per";
628 #pwm-cells = <2>;
629 status = "disabled";
630 };
632 pwm3: pwm@30680000 {
633 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
634 reg = <0x30680000 0x10000>;
635 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
636 clocks = <&clk IMX8MN_CLK_PWM3_ROOT>,
637 <&clk IMX8MN_CLK_PWM3_ROOT>;
638 clock-names = "ipg", "per";
639 #pwm-cells = <2>;
640 status = "disabled";
641 };
643 pwm4: pwm@30690000 {
644 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
645 reg = <0x30690000 0x10000>;
646 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
647 clocks = <&clk IMX8MN_CLK_PWM4_ROOT>,
648 <&clk IMX8MN_CLK_PWM4_ROOT>;
649 clock-names = "ipg", "per";
650 #pwm-cells = <2>;
651 status = "disabled";
652 };
654 system_counter: timer@306a0000 {
655 compatible = "nxp,sysctr-timer";
656 reg = <0x306a0000 0x20000>;
657 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&osc_24m>;
659 clock-names = "per";
660 };
661 };
663 aips3: bus@30800000 {
664 compatible = "fsl,aips-bus", "simple-bus";
665 reg = <0x30800000 0x400000>;
666 #address-cells = <1>;
667 #size-cells = <1>;
668 ranges;
670 ecspi1: spi@30820000 {
671 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
672 #address-cells = <1>;
673 #size-cells = <0>;
674 reg = <0x30820000 0x10000>;
675 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&clk IMX8MN_CLK_ECSPI1_ROOT>,
677 <&clk IMX8MN_CLK_ECSPI1_ROOT>;
678 clock-names = "ipg", "per";
679 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
680 dma-names = "rx", "tx";
681 status = "disabled";
682 };
684 ecspi2: spi@30830000 {
685 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
686 #address-cells = <1>;
687 #size-cells = <0>;
688 reg = <0x30830000 0x10000>;
689 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&clk IMX8MN_CLK_ECSPI2_ROOT>,
691 <&clk IMX8MN_CLK_ECSPI2_ROOT>;
692 clock-names = "ipg", "per";
693 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
694 dma-names = "rx", "tx";
695 status = "disabled";
696 };
698 ecspi3: spi@30840000 {
699 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
700 #address-cells = <1>;
701 #size-cells = <0>;
702 reg = <0x30840000 0x10000>;
703 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clk IMX8MN_CLK_ECSPI3_ROOT>,
705 <&clk IMX8MN_CLK_ECSPI3_ROOT>;
706 clock-names = "ipg", "per";
707 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
708 dma-names = "rx", "tx";
709 status = "disabled";
710 };
712 uart1: serial@30860000 {
713 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
714 reg = <0x30860000 0x10000>;
715 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&clk IMX8MN_CLK_UART1_ROOT>,
717 <&clk IMX8MN_CLK_UART1_ROOT>;
718 clock-names = "ipg", "per";
719 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
720 dma-names = "rx", "tx";
721 status = "disabled";
722 };
724 uart3: serial@30880000 {
725 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
726 reg = <0x30880000 0x10000>;
727 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
728 clocks = <&clk IMX8MN_CLK_UART3_ROOT>,
729 <&clk IMX8MN_CLK_UART3_ROOT>;
730 clock-names = "ipg", "per";
731 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
732 dma-names = "rx", "tx";
733 status = "disabled";
734 };
736 uart2: serial@30890000 {
737 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
738 reg = <0x30890000 0x10000>;
739 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clk IMX8MN_CLK_UART2_ROOT>,
741 <&clk IMX8MN_CLK_UART2_ROOT>;
742 clock-names = "ipg", "per";
743 status = "disabled";
744 };
746 crypto: crypto@30900000 {
747 compatible = "fsl,sec-v4.0";
748 #address-cells = <1>;
749 #size-cells = <1>;
750 reg = <0x30900000 0x40000>;
751 ranges = <0 0x30900000 0x40000>;
752 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clk IMX8MN_CLK_AHB>,
754 <&clk IMX8MN_CLK_IPG_ROOT>;
755 clock-names = "aclk", "ipg";
757 sec_jr0: jr@1000 {
758 compatible = "fsl,sec-v4.0-job-ring";
759 reg = <0x1000 0x1000>;
760 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
761 };
763 sec_jr1: jr@2000 {
764 compatible = "fsl,sec-v4.0-job-ring";
765 reg = <0x2000 0x1000>;
766 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
767 };
769 sec_jr2: jr@3000 {
770 compatible = "fsl,sec-v4.0-job-ring";
771 reg = <0x3000 0x1000>;
772 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
773 };
774 };
776 i2c1: i2c@30a20000 {
777 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
778 #address-cells = <1>;
779 #size-cells = <0>;
780 reg = <0x30a20000 0x10000>;
781 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&clk IMX8MN_CLK_I2C1_ROOT>;
783 status = "disabled";
784 };
786 i2c2: i2c@30a30000 {
787 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
788 #address-cells = <1>;
789 #size-cells = <0>;
790 reg = <0x30a30000 0x10000>;
791 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&clk IMX8MN_CLK_I2C2_ROOT>;
793 status = "disabled";
794 };
796 i2c3: i2c@30a40000 {
797 #address-cells = <1>;
798 #size-cells = <0>;
799 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
800 reg = <0x30a40000 0x10000>;
801 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&clk IMX8MN_CLK_I2C3_ROOT>;
803 status = "disabled";
804 };
806 i2c4: i2c@30a50000 {
807 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
808 #address-cells = <1>;
809 #size-cells = <0>;
810 reg = <0x30a50000 0x10000>;
811 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&clk IMX8MN_CLK_I2C4_ROOT>;
813 status = "disabled";
814 };
816 uart4: serial@30a60000 {
817 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
818 reg = <0x30a60000 0x10000>;
819 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
820 clocks = <&clk IMX8MN_CLK_UART4_ROOT>,
821 <&clk IMX8MN_CLK_UART4_ROOT>;
822 clock-names = "ipg", "per";
823 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
824 dma-names = "rx", "tx";
825 status = "disabled";
826 };
828 mu: mailbox@30aa0000 {
829 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
830 reg = <0x30aa0000 0x10000>;
831 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&clk IMX8MN_CLK_MU_ROOT>;
833 #mbox-cells = <2>;
834 };
836 usdhc1: mmc@30b40000 {
837 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
838 reg = <0x30b40000 0x10000>;
839 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
841 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
842 <&clk IMX8MN_CLK_USDHC1_ROOT>;
843 clock-names = "ipg", "ahb", "per";
844 fsl,tuning-start-tap = <20>;
845 fsl,tuning-step= <2>;
846 bus-width = <4>;
847 status = "disabled";
848 };
850 usdhc2: mmc@30b50000 {
851 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
852 reg = <0x30b50000 0x10000>;
853 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
855 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
856 <&clk IMX8MN_CLK_USDHC2_ROOT>;
857 clock-names = "ipg", "ahb", "per";
858 fsl,tuning-start-tap = <20>;
859 fsl,tuning-step= <2>;
860 bus-width = <4>;
861 status = "disabled";
862 };
864 usdhc3: mmc@30b60000 {
865 compatible = "fsl,imx8mn-usdhc", "fsl,imx7d-usdhc";
866 reg = <0x30b60000 0x10000>;
867 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
868 clocks = <&clk IMX8MN_CLK_IPG_ROOT>,
869 <&clk IMX8MN_CLK_NAND_USDHC_BUS>,
870 <&clk IMX8MN_CLK_USDHC3_ROOT>;
871 clock-names = "ipg", "ahb", "per";
872 fsl,tuning-start-tap = <20>;
873 fsl,tuning-step= <2>;
874 bus-width = <4>;
875 status = "disabled";
876 };
878 sdma1: dma-controller@30bd0000 {
879 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
880 reg = <0x30bd0000 0x10000>;
881 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&clk IMX8MN_CLK_SDMA1_ROOT>,
883 <&clk IMX8MN_CLK_AHB>;
884 clock-names = "ipg", "ahb";
885 #dma-cells = <3>;
886 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
887 };
889 fec1: ethernet@30be0000 {
890 compatible = "fsl,imx8mn-fec", "fsl,imx6sx-fec";
891 reg = <0x30be0000 0x10000>;
892 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
893 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
894 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
895 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
896 clocks = <&clk IMX8MN_CLK_ENET1_ROOT>,
897 <&clk IMX8MN_CLK_ENET1_ROOT>,
898 <&clk IMX8MN_CLK_ENET_TIMER>,
899 <&clk IMX8MN_CLK_ENET_REF>,
900 <&clk IMX8MN_CLK_ENET_PHY_REF>;
901 clock-names = "ipg", "ahb", "ptp",
902 "enet_clk_ref", "enet_out";
903 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
904 <&clk IMX8MN_CLK_ENET_TIMER>,
905 <&clk IMX8MN_CLK_ENET_REF>,
906 <&clk IMX8MN_CLK_ENET_TIMER>;
907 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
908 <&clk IMX8MN_SYS_PLL2_100M>,
909 <&clk IMX8MN_SYS_PLL2_125M>;
910 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
911 fsl,num-tx-queues = <3>;
912 fsl,num-rx-queues = <3>;
913 status = "disabled";
914 };
916 };
918 aips4: bus@32c00000 {
919 compatible = "fsl,aips-bus", "simple-bus";
920 reg = <0x32c00000 0x400000>;
921 #address-cells = <1>;
922 #size-cells = <1>;
923 ranges;
925 usbotg1: usb@32e40000 {
926 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb";
927 reg = <0x32e40000 0x200>;
928 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
929 clocks = <&clk IMX8MN_CLK_USB1_CTRL_ROOT>;
930 clock-names = "usb1_ctrl_root_clk";
931 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
932 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
933 fsl,usbphy = <&usbphynop1>;
934 fsl,usbmisc = <&usbmisc1 0>;
935 status = "disabled";
936 };
938 usbmisc1: usbmisc@32e40200 {
939 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc";
940 #index-cells = <1>;
941 reg = <0x32e40200 0x200>;
942 };
943 };
945 dma_apbh: dma-controller@33000000 {
946 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
947 reg = <0x33000000 0x2000>;
948 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
952 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
953 #dma-cells = <1>;
954 dma-channels = <4>;
955 clocks = <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
956 };
958 gpmi: nand-controller@33002000 {
959 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
960 #address-cells = <1>;
961 #size-cells = <1>;
962 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
963 reg-names = "gpmi-nand", "bch";
964 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
965 interrupt-names = "bch";
966 clocks = <&clk IMX8MN_CLK_NAND_ROOT>,
967 <&clk IMX8MN_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
968 clock-names = "gpmi_io", "gpmi_bch_apb";
969 dmas = <&dma_apbh 0>;
970 dma-names = "rx-tx";
971 status = "disabled";
972 };
974 gic: interrupt-controller@38800000 {
975 compatible = "arm,gic-v3";
976 reg = <0x38800000 0x10000>,
977 <0x38880000 0xc0000>;
978 #interrupt-cells = <3>;
979 interrupt-controller;
980 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
981 };
983 ddrc: memory-controller@3d400000 {
984 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
985 reg = <0x3d400000 0x400000>;
986 clock-names = "core", "pll", "alt", "apb";
987 clocks = <&clk IMX8MN_CLK_DRAM_CORE>,
988 <&clk IMX8MN_DRAM_PLL>,
989 <&clk IMX8MN_CLK_DRAM_ALT>,
990 <&clk IMX8MN_CLK_DRAM_APB>;
991 };
993 ddr-pmu@3d800000 {
994 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
995 reg = <0x3d800000 0x400000>;
996 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
997 };
998 };
1000 usbphynop1: usbphynop1 {
1001 compatible = "usb-nop-xceiv";
1002 clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1003 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1004 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1005 clock-names = "main_clk";
1006 };
1007 };