arch/arm64/boot/dts/freescale/imx8mp-evk.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright 2019 NXP
   4  */
   5
   6 /dts-v1/;
   7
   8 #include "imx8mp.dtsi"
   9
  10 / {
  11         model = "NXP i.MX8MPlus EVK board";
  12         compatible = "fsl,imx8mp-evk", "fsl,imx8mp";
  13
  14         chosen {
  15                 stdout-path = &uart2;
  16         };
  17
  18         gpio-leds {
  19                 compatible = "gpio-leds";
  20                 pinctrl-names = "default";
  21                 pinctrl-0 = <&pinctrl_gpio_led>;
  22
  23                 status {
  24                         label = "yellow:status";
  25                         gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
  26                         default-state = "on";
  27                 };
  28         };
  29
  30         memory@40000000 {
  31                 device_type = "memory";
  32                 reg = <0x0 0x40000000 0 0xc0000000>,
  33                       <0x1 0x00000000 0 0xc0000000>;
  34         };
  35
  36         reg_can1_stby: regulator-can1-stby {
  37                 compatible = "regulator-fixed";
  38                 regulator-name = "can1-stby";
  39                 pinctrl-names = "default";
  40                 pinctrl-0 = <&pinctrl_flexcan1_reg>;
  41                 regulator-min-microvolt = <3300000>;
  42                 regulator-max-microvolt = <3300000>;
  43                 gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>;
  44                 enable-active-high;
  45         };
  46
  47         reg_can2_stby: regulator-can2-stby {
  48                 compatible = "regulator-fixed";
  49                 regulator-name = "can2-stby";
  50                 pinctrl-names = "default";
  51                 pinctrl-0 = <&pinctrl_flexcan2_reg>;
  52                 regulator-min-microvolt = <3300000>;
  53                 regulator-max-microvolt = <3300000>;
  54                 gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
  55                 enable-active-high;
  56         };
  57
  58         reg_usdhc2_vmmc: regulator-usdhc2 {
  59                 compatible = "regulator-fixed";
  60                 pinctrl-names = "default";
  61                 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
  62                 regulator-name = "VSD_3V3";
  63                 regulator-min-microvolt = <3300000>;
  64                 regulator-max-microvolt = <3300000>;
  65                 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  66                 enable-active-high;
  67         };
  68 };
  69
  70 &flexcan1 {
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_flexcan1>;
  73         xceiver-supply = <&reg_can1_stby>;
  74         status = "okay";
  75 };
  76
  77 &flexcan2 {
  78         pinctrl-names = "default";
  79         pinctrl-0 = <&pinctrl_flexcan2>;
  80         xceiver-supply = <&reg_can2_stby>;
  81         status = "disabled";/* can2 pin conflict with pdm */
  82 };
  83
  84 &fec {
  85         pinctrl-names = "default";
  86         pinctrl-0 = <&pinctrl_fec>;
  87         phy-mode = "rgmii-id";
  88         phy-handle = <&ethphy1>;
  89         fsl,magic-packet;
  90         status = "okay";
  91
  92         mdio {
  93                 #address-cells = <1>;
  94                 #size-cells = <0>;
  95
  96                 ethphy1: ethernet-phy@1 {
  97                         compatible = "ethernet-phy-ieee802.3-c22";
  98                         reg = <1>;
  99                         eee-broken-1000t;
 100                         reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 101                 };
 102         };
 103 };
 104
 105 &i2c3 {
 106         clock-frequency = <400000>;
 107         pinctrl-names = "default";
 108         pinctrl-0 = <&pinctrl_i2c3>;
 109         status = "okay";
 110
 111         pca6416: gpio@20 {
 112                 compatible = "ti,tca6416";
 113                 reg = <0x20>;
 114                 gpio-controller;
 115                 #gpio-cells = <2>;
 116         };
 117 };
 118
 119 &snvs_pwrkey {
 120         status = "okay";
 121 };
 122
 123 &uart2 {
 124         /* console */
 125         pinctrl-names = "default";
 126         pinctrl-0 = <&pinctrl_uart2>;
 127         status = "okay";
 128 };
 129
 130 &usdhc2 {
 131         assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
 132         assigned-clock-rates = <400000000>;
 133         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 134         pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
 135         pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
 136         pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
 137         cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
 138         vmmc-supply = <&reg_usdhc2_vmmc>;
 139         bus-width = <4>;
 140         status = "okay";
 141 };
 142
 143 &usdhc3 {
 144         assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
 145         assigned-clock-rates = <400000000>;
 146         pinctrl-names = "default", "state_100mhz", "state_200mhz";
 147         pinctrl-0 = <&pinctrl_usdhc3>;
 148         pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
 149         pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 150         bus-width = <8>;
 151         non-removable;
 152         status = "okay";
 153 };
 154
 155 &wdog1 {
 156         pinctrl-names = "default";
 157         pinctrl-0 = <&pinctrl_wdog>;
 158         fsl,ext-reset-output;
 159         status = "okay";
 160 };
 161
 162 &iomuxc {
 163         pinctrl_fec: fecgrp {
 164                 fsl,pins = <
 165                         MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC               0x3
 166                         MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO              0x3
 167                         MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0         0x91
 168                         MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1         0x91
 169                         MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2         0x91
 170                         MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3         0x91
 171                         MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC          0x91
 172                         MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL      0x91
 173                         MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0         0x1f
 174                         MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1         0x1f
 175                         MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2         0x1f
 176                         MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3         0x1f
 177                         MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL      0x1f
 178                         MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC         0x1f
 179                         MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02              0x19
 180                 >;
 181         };
 182
 183         pinctrl_flexcan1: flexcan1grp {
 184                 fsl,pins = <
 185                         MX8MP_IOMUXC_SPDIF_RX__CAN1_RX          0x154
 186                         MX8MP_IOMUXC_SPDIF_TX__CAN1_TX          0x154
 187                 >;
 188         };
 189
 190         pinctrl_flexcan2: flexcan2grp {
 191                 fsl,pins = <
 192                         MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX         0x154
 193                         MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX         0x154
 194                 >;
 195         };
 196
 197         pinctrl_flexcan1_reg: flexcan1reggrp {
 198                 fsl,pins = <
 199                         MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05  0x154   /* CAN1_STBY */
 200                 >;
 201         };
 202
 203         pinctrl_flexcan2_reg: flexcan2reggrp {
 204                 fsl,pins = <
 205                         MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27      0x154   /* CAN2_STBY */
 206                 >;
 207         };
 208
 209         pinctrl_gpio_led: gpioledgrp {
 210                 fsl,pins = <
 211                         MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16   0x19
 212                 >;
 213         };
 214
 215         pinctrl_i2c3: i2c3grp {
 216                 fsl,pins = <
 217                         MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL         0x400001c3
 218                         MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA         0x400001c3
 219                 >;
 220         };
 221
 222         pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 223                 fsl,pins = <
 224                         MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19    0x41
 225                 >;
 226         };
 227
 228         pinctrl_uart2: uart2grp {
 229                 fsl,pins = <
 230                         MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX    0x49
 231                         MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX    0x49
 232                 >;
 233         };
 234
 235         pinctrl_usdhc2: usdhc2grp {
 236                 fsl,pins = <
 237                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x190
 238                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d0
 239                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d0
 240                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d0
 241                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d0
 242                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d0
 243                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 244                 >;
 245         };
 246
 247         pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
 248                 fsl,pins = <
 249                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x194
 250                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d4
 251                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d4
 252                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d4
 253                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d4
 254                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d4
 255                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 256                 >;
 257         };
 258
 259         pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
 260                 fsl,pins = <
 261                         MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK        0x196
 262                         MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD        0x1d6
 263                         MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0    0x1d6
 264                         MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1    0x1d6
 265                         MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2    0x1d6
 266                         MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3    0x1d6
 267                         MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
 268                 >;
 269         };
 270
 271         pinctrl_usdhc2_gpio: usdhc2gpiogrp {
 272                 fsl,pins = <
 273                         MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12       0x1c4
 274                 >;
 275         };
 276
 277         pinctrl_usdhc3: usdhc3grp {
 278                 fsl,pins = <
 279                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x190
 280                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d0
 281                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d0
 282                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d0
 283                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d0
 284                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d0
 285                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d0
 286                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d0
 287                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d0
 288                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d0
 289                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x190
 290                 >;
 291         };
 292
 293         pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 294                 fsl,pins = <
 295                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x194
 296                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d4
 297                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d4
 298                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d4
 299                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d4
 300                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d4
 301                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d4
 302                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d4
 303                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d4
 304                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d4
 305                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x194
 306                 >;
 307         };
 308
 309         pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 310                 fsl,pins = <
 311                         MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK      0x196
 312                         MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD      0x1d6
 313                         MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0  0x1d6
 314                         MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1  0x1d6
 315                         MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2  0x1d6
 316                         MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3  0x1d6
 317                         MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4    0x1d6
 318                         MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5   0x1d6
 319                         MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6   0x1d6
 320                         MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7     0x1d6
 321                         MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE  0x196
 322                 >;
 323         };
 324
 325         pinctrl_wdog: wdoggrp {
 326                 fsl,pins = <
 327                         MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B   0x166
 328                 >;
 329         };
 330 };