| blob | ecccfbb4f5ad6831c5d00af1f56201ad99fe5f9d |
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h>
12 #include "imx8mp-pinfunc.h"
14 / {
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
19 aliases {
20 ethernet0 = &fec;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 i2c4 = &i2c5;
31 i2c5 = &i2c6;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 serial0 = &uart1;
36 serial1 = &uart2;
37 serial2 = &uart3;
38 serial3 = &uart4;
39 };
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
45 A53_0: cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a53";
48 reg = <0x0>;
49 clock-latency = <61036>;
50 clocks = <&clk IMX8MP_CLK_ARM>;
51 enable-method = "psci";
52 next-level-cache = <&A53_L2>;
53 #cooling-cells = <2>;
54 };
56 A53_1: cpu@1 {
57 device_type = "cpu";
58 compatible = "arm,cortex-a53";
59 reg = <0x1>;
60 clock-latency = <61036>;
61 clocks = <&clk IMX8MP_CLK_ARM>;
62 enable-method = "psci";
63 next-level-cache = <&A53_L2>;
64 #cooling-cells = <2>;
65 };
67 A53_2: cpu@2 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a53";
70 reg = <0x2>;
71 clock-latency = <61036>;
72 clocks = <&clk IMX8MP_CLK_ARM>;
73 enable-method = "psci";
74 next-level-cache = <&A53_L2>;
75 #cooling-cells = <2>;
76 };
78 A53_3: cpu@3 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a53";
81 reg = <0x3>;
82 clock-latency = <61036>;
83 clocks = <&clk IMX8MP_CLK_ARM>;
84 enable-method = "psci";
85 next-level-cache = <&A53_L2>;
86 #cooling-cells = <2>;
87 };
89 A53_L2: l2-cache0 {
90 compatible = "cache";
91 };
92 };
94 osc_32k: clock-osc-32k {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <32768>;
98 clock-output-names = "osc_32k";
99 };
101 osc_24m: clock-osc-24m {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <24000000>;
105 clock-output-names = "osc_24m";
106 };
108 clk_ext1: clock-ext1 {
109 compatible = "fixed-clock";
110 #clock-cells = <0>;
111 clock-frequency = <133000000>;
112 clock-output-names = "clk_ext1";
113 };
115 clk_ext2: clock-ext2 {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <133000000>;
119 clock-output-names = "clk_ext2";
120 };
122 clk_ext3: clock-ext3 {
123 compatible = "fixed-clock";
124 #clock-cells = <0>;
125 clock-frequency = <133000000>;
126 clock-output-names = "clk_ext3";
127 };
129 clk_ext4: clock-ext4 {
130 compatible = "fixed-clock";
131 #clock-cells = <0>;
132 clock-frequency= <133000000>;
133 clock-output-names = "clk_ext4";
134 };
136 pmu {
137 compatible = "arm,cortex-a53-pmu";
138 interrupts = <GIC_PPI 7
139 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
140 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
141 };
143 psci {
144 compatible = "arm,psci-1.0";
145 method = "smc";
146 };
148 thermal-zones {
149 cpu-thermal {
150 polling-delay-passive = <250>;
151 polling-delay = <2000>;
152 thermal-sensors = <&tmu 0>;
153 trips {
154 cpu_alert0: trip0 {
155 temperature = <85000>;
156 hysteresis = <2000>;
157 type = "passive";
158 };
160 cpu_crit0: trip1 {
161 temperature = <95000>;
162 hysteresis = <2000>;
163 type = "critical";
164 };
165 };
167 cooling-maps {
168 map0 {
169 trip = <&cpu_alert0>;
170 cooling-device =
171 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
172 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
173 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
174 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
175 };
176 };
177 };
179 soc-thermal {
180 polling-delay-passive = <250>;
181 polling-delay = <2000>;
182 thermal-sensors = <&tmu 1>;
183 trips {
184 soc_alert0: trip0 {
185 temperature = <85000>;
186 hysteresis = <2000>;
187 type = "passive";
188 };
190 soc_crit0: trip1 {
191 temperature = <95000>;
192 hysteresis = <2000>;
193 type = "critical";
194 };
195 };
197 cooling-maps {
198 map0 {
199 trip = <&soc_alert0>;
200 cooling-device =
201 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
202 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
203 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
204 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
205 };
206 };
207 };
208 };
210 timer {
211 compatible = "arm,armv8-timer";
212 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
213 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
214 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
215 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
216 clock-frequency = <8000000>;
217 arm,no-tick-in-suspend;
218 };
220 soc@0 {
221 compatible = "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0x0 0x0 0x0 0x3e000000>;
226 aips1: bus@30000000 {
227 compatible = "fsl,aips-bus", "simple-bus";
228 reg = <0x30000000 0x400000>;
229 #address-cells = <1>;
230 #size-cells = <1>;
231 ranges;
233 gpio1: gpio@30200000 {
234 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
235 reg = <0x30200000 0x10000>;
236 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
239 gpio-controller;
240 #gpio-cells = <2>;
241 interrupt-controller;
242 #interrupt-cells = <2>;
243 gpio-ranges = <&iomuxc 0 5 30>;
244 };
246 gpio2: gpio@30210000 {
247 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
248 reg = <0x30210000 0x10000>;
249 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
251 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
255 #interrupt-cells = <2>;
256 gpio-ranges = <&iomuxc 0 35 21>;
257 };
259 gpio3: gpio@30220000 {
260 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
261 reg = <0x30220000 0x10000>;
262 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
265 gpio-controller;
266 #gpio-cells = <2>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
269 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 0 144 4>;
270 };
272 gpio4: gpio@30230000 {
273 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
274 reg = <0x30230000 0x10000>;
275 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
276 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
278 gpio-controller;
279 #gpio-cells = <2>;
280 interrupt-controller;
281 #interrupt-cells = <2>;
282 gpio-ranges = <&iomuxc 0 82 32>;
283 };
285 gpio5: gpio@30240000 {
286 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
287 reg = <0x30240000 0x10000>;
288 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
291 gpio-controller;
292 #gpio-cells = <2>;
293 interrupt-controller;
294 #interrupt-cells = <2>;
295 gpio-ranges = <&iomuxc 0 114 30>;
296 };
298 tmu: tmu@30260000 {
299 compatible = "fsl,imx8mp-tmu";
300 reg = <0x30260000 0x10000>;
301 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
302 #thermal-sensor-cells = <1>;
303 };
305 wdog1: watchdog@30280000 {
306 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
307 reg = <0x30280000 0x10000>;
308 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
310 status = "disabled";
311 };
313 iomuxc: pinctrl@30330000 {
314 compatible = "fsl,imx8mp-iomuxc";
315 reg = <0x30330000 0x10000>;
316 };
318 gpr: iomuxc-gpr@30340000 {
319 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
320 reg = <0x30340000 0x10000>;
321 };
323 ocotp: efuse@30350000 {
324 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
325 reg = <0x30350000 0x10000>;
326 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
327 /* For nvmem subnodes */
328 #address-cells = <1>;
329 #size-cells = <1>;
331 cpu_speed_grade: speed-grade@10 {
332 reg = <0x10 4>;
333 };
334 };
336 anatop: anatop@30360000 {
337 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
338 "syscon";
339 reg = <0x30360000 0x10000>;
340 };
342 snvs: snvs@30370000 {
343 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
344 reg = <0x30370000 0x10000>;
346 snvs_rtc: snvs-rtc-lp {
347 compatible = "fsl,sec-v4.0-mon-rtc-lp";
348 regmap =<&snvs>;
349 offset = <0x34>;
350 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
353 clock-names = "snvs-rtc";
354 };
356 snvs_pwrkey: snvs-powerkey {
357 compatible = "fsl,sec-v4.0-pwrkey";
358 regmap = <&snvs>;
359 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
361 clock-names = "snvs-pwrkey";
362 linux,keycode = <KEY_POWER>;
363 wakeup-source;
364 status = "disabled";
365 };
366 };
368 clk: clock-controller@30380000 {
369 compatible = "fsl,imx8mp-ccm";
370 reg = <0x30380000 0x10000>;
371 #clock-cells = <1>;
372 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
373 <&clk_ext3>, <&clk_ext4>;
374 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
375 "clk_ext3", "clk_ext4";
376 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
377 <&clk IMX8MP_CLK_A53_CORE>,
378 <&clk IMX8MP_CLK_NOC>,
379 <&clk IMX8MP_CLK_NOC_IO>,
380 <&clk IMX8MP_CLK_GIC>,
381 <&clk IMX8MP_CLK_AUDIO_AHB>,
382 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
383 <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
384 <&clk IMX8MP_AUDIO_PLL1>,
385 <&clk IMX8MP_AUDIO_PLL2>;
386 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
387 <&clk IMX8MP_ARM_PLL_OUT>,
388 <&clk IMX8MP_SYS_PLL2_1000M>,
389 <&clk IMX8MP_SYS_PLL1_800M>,
390 <&clk IMX8MP_SYS_PLL2_500M>,
391 <&clk IMX8MP_SYS_PLL1_800M>,
392 <&clk IMX8MP_SYS_PLL1_800M>;
393 assigned-clock-rates = <0>, <0>,
394 <1000000000>,
395 <800000000>,
396 <500000000>,
397 <400000000>,
398 <800000000>,
399 <400000000>,
400 <393216000>,
401 <361267200>;
402 };
404 src: reset-controller@30390000 {
405 compatible = "fsl,imx8mp-src", "syscon";
406 reg = <0x30390000 0x10000>;
407 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
408 #reset-cells = <1>;
409 };
410 };
412 aips2: bus@30400000 {
413 compatible = "fsl,aips-bus", "simple-bus";
414 reg = <0x30400000 0x400000>;
415 #address-cells = <1>;
416 #size-cells = <1>;
417 ranges;
419 pwm1: pwm@30660000 {
420 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
421 reg = <0x30660000 0x10000>;
422 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
424 <&clk IMX8MP_CLK_PWM1_ROOT>;
425 clock-names = "ipg", "per";
426 #pwm-cells = <2>;
427 status = "disabled";
428 };
430 pwm2: pwm@30670000 {
431 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
432 reg = <0x30670000 0x10000>;
433 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
435 <&clk IMX8MP_CLK_PWM2_ROOT>;
436 clock-names = "ipg", "per";
437 #pwm-cells = <2>;
438 status = "disabled";
439 };
441 pwm3: pwm@30680000 {
442 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
443 reg = <0x30680000 0x10000>;
444 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
446 <&clk IMX8MP_CLK_PWM3_ROOT>;
447 clock-names = "ipg", "per";
448 #pwm-cells = <2>;
449 status = "disabled";
450 };
452 pwm4: pwm@30690000 {
453 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
454 reg = <0x30690000 0x10000>;
455 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
457 <&clk IMX8MP_CLK_PWM4_ROOT>;
458 clock-names = "ipg", "per";
459 #pwm-cells = <2>;
460 status = "disabled";
461 };
463 system_counter: timer@306a0000 {
464 compatible = "nxp,sysctr-timer";
465 reg = <0x306a0000 0x20000>;
466 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&osc_24m>;
468 clock-names = "per";
469 };
470 };
472 aips3: bus@30800000 {
473 compatible = "fsl,aips-bus", "simple-bus";
474 reg = <0x30800000 0x400000>;
475 #address-cells = <1>;
476 #size-cells = <1>;
477 ranges;
479 ecspi1: spi@30820000 {
480 #address-cells = <1>;
481 #size-cells = <0>;
482 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
483 reg = <0x30820000 0x10000>;
484 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
485 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
486 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
487 clock-names = "ipg", "per";
488 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
489 dma-names = "rx", "tx";
490 status = "disabled";
491 };
493 ecspi2: spi@30830000 {
494 #address-cells = <1>;
495 #size-cells = <0>;
496 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
497 reg = <0x30830000 0x10000>;
498 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
499 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
500 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
501 clock-names = "ipg", "per";
502 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
503 dma-names = "rx", "tx";
504 status = "disabled";
505 };
507 ecspi3: spi@30840000 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
511 reg = <0x30840000 0x10000>;
512 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
513 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
514 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
515 clock-names = "ipg", "per";
516 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
517 dma-names = "rx", "tx";
518 status = "disabled";
519 };
521 uart1: serial@30860000 {
522 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
523 reg = <0x30860000 0x10000>;
524 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
526 <&clk IMX8MP_CLK_UART1_ROOT>;
527 clock-names = "ipg", "per";
528 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
529 dma-names = "rx", "tx";
530 status = "disabled";
531 };
533 uart3: serial@30880000 {
534 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
535 reg = <0x30880000 0x10000>;
536 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
538 <&clk IMX8MP_CLK_UART3_ROOT>;
539 clock-names = "ipg", "per";
540 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
541 dma-names = "rx", "tx";
542 status = "disabled";
543 };
545 uart2: serial@30890000 {
546 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
547 reg = <0x30890000 0x10000>;
548 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
550 <&clk IMX8MP_CLK_UART2_ROOT>;
551 clock-names = "ipg", "per";
552 status = "disabled";
553 };
555 flexcan1: can@308c0000 {
556 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
557 reg = <0x308c0000 0x10000>;
558 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
560 <&clk IMX8MP_CLK_CAN1_ROOT>;
561 clock-names = "ipg", "per";
562 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
563 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
564 assigned-clock-rates = <40000000>;
565 fsl,clk-source = /bits/ 8 <0>;
566 fsl,stop-mode = <&gpr 0x10 4>;
567 status = "disabled";
568 };
570 flexcan2: can@308d0000 {
571 compatible = "fsl,imx8mp-flexcan", "fsl,imx6q-flexcan";
572 reg = <0x308d0000 0x10000>;
573 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
575 <&clk IMX8MP_CLK_CAN2_ROOT>;
576 clock-names = "ipg", "per";
577 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
578 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
579 assigned-clock-rates = <40000000>;
580 fsl,clk-source = /bits/ 8 <0>;
581 fsl,stop-mode = <&gpr 0x10 5>;
582 status = "disabled";
583 };
585 crypto: crypto@30900000 {
586 compatible = "fsl,sec-v4.0";
587 #address-cells = <1>;
588 #size-cells = <1>;
589 reg = <0x30900000 0x40000>;
590 ranges = <0 0x30900000 0x40000>;
591 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
592 clocks = <&clk IMX8MP_CLK_AHB>,
593 <&clk IMX8MP_CLK_IPG_ROOT>;
594 clock-names = "aclk", "ipg";
596 sec_jr0: jr@1000 {
597 compatible = "fsl,sec-v4.0-job-ring";
598 reg = <0x1000 0x1000>;
599 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
600 };
602 sec_jr1: jr@2000 {
603 compatible = "fsl,sec-v4.0-job-ring";
604 reg = <0x2000 0x1000>;
605 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
606 };
608 sec_jr2: jr@3000 {
609 compatible = "fsl,sec-v4.0-job-ring";
610 reg = <0x3000 0x1000>;
611 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
612 };
613 };
615 i2c1: i2c@30a20000 {
616 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
617 #address-cells = <1>;
618 #size-cells = <0>;
619 reg = <0x30a20000 0x10000>;
620 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
622 status = "disabled";
623 };
625 i2c2: i2c@30a30000 {
626 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
627 #address-cells = <1>;
628 #size-cells = <0>;
629 reg = <0x30a30000 0x10000>;
630 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
632 status = "disabled";
633 };
635 i2c3: i2c@30a40000 {
636 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
637 #address-cells = <1>;
638 #size-cells = <0>;
639 reg = <0x30a40000 0x10000>;
640 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
641 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
642 status = "disabled";
643 };
645 i2c4: i2c@30a50000 {
646 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
647 #address-cells = <1>;
648 #size-cells = <0>;
649 reg = <0x30a50000 0x10000>;
650 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
652 status = "disabled";
653 };
655 uart4: serial@30a60000 {
656 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
657 reg = <0x30a60000 0x10000>;
658 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
660 <&clk IMX8MP_CLK_UART4_ROOT>;
661 clock-names = "ipg", "per";
662 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
663 dma-names = "rx", "tx";
664 status = "disabled";
665 };
667 mu: mailbox@30aa0000 {
668 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
669 reg = <0x30aa0000 0x10000>;
670 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
672 #mbox-cells = <2>;
673 };
675 i2c5: i2c@30ad0000 {
676 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
677 #address-cells = <1>;
678 #size-cells = <0>;
679 reg = <0x30ad0000 0x10000>;
680 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
682 status = "disabled";
683 };
685 i2c6: i2c@30ae0000 {
686 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
687 #address-cells = <1>;
688 #size-cells = <0>;
689 reg = <0x30ae0000 0x10000>;
690 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
691 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
692 status = "disabled";
693 };
695 usdhc1: mmc@30b40000 {
696 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
697 reg = <0x30b40000 0x10000>;
698 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
699 clocks = <&clk IMX8MP_CLK_DUMMY>,
700 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
701 <&clk IMX8MP_CLK_USDHC1_ROOT>;
702 clock-names = "ipg", "ahb", "per";
703 fsl,tuning-start-tap = <20>;
704 fsl,tuning-step= <2>;
705 bus-width = <4>;
706 status = "disabled";
707 };
709 usdhc2: mmc@30b50000 {
710 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
711 reg = <0x30b50000 0x10000>;
712 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&clk IMX8MP_CLK_DUMMY>,
714 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
715 <&clk IMX8MP_CLK_USDHC2_ROOT>;
716 clock-names = "ipg", "ahb", "per";
717 fsl,tuning-start-tap = <20>;
718 fsl,tuning-step= <2>;
719 bus-width = <4>;
720 status = "disabled";
721 };
723 usdhc3: mmc@30b60000 {
724 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
725 reg = <0x30b60000 0x10000>;
726 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&clk IMX8MP_CLK_DUMMY>,
728 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
729 <&clk IMX8MP_CLK_USDHC3_ROOT>;
730 clock-names = "ipg", "ahb", "per";
731 fsl,tuning-start-tap = <20>;
732 fsl,tuning-step= <2>;
733 bus-width = <4>;
734 status = "disabled";
735 };
737 sdma1: dma-controller@30bd0000 {
738 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
739 reg = <0x30bd0000 0x10000>;
740 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
742 <&clk IMX8MP_CLK_AHB>;
743 clock-names = "ipg", "ahb";
744 #dma-cells = <3>;
745 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
746 };
748 fec: ethernet@30be0000 {
749 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
750 reg = <0x30be0000 0x10000>;
751 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
755 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
756 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
757 <&clk IMX8MP_CLK_ENET_TIMER>,
758 <&clk IMX8MP_CLK_ENET_REF>,
759 <&clk IMX8MP_CLK_ENET_PHY_REF>;
760 clock-names = "ipg", "ahb", "ptp",
761 "enet_clk_ref", "enet_out";
762 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
763 <&clk IMX8MP_CLK_ENET_TIMER>,
764 <&clk IMX8MP_CLK_ENET_REF>,
765 <&clk IMX8MP_CLK_ENET_TIMER>;
766 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
767 <&clk IMX8MP_SYS_PLL2_100M>,
768 <&clk IMX8MP_SYS_PLL2_125M>;
769 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
770 fsl,num-tx-queues = <3>;
771 fsl,num-rx-queues = <3>;
772 status = "disabled";
773 };
774 };
776 gic: interrupt-controller@38800000 {
777 compatible = "arm,gic-v3";
778 reg = <0x38800000 0x10000>,
779 <0x38880000 0xc0000>;
780 #interrupt-cells = <3>;
781 interrupt-controller;
782 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
783 interrupt-parent = <&gic>;
784 };
786 ddr-pmu@3d800000 {
787 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
788 reg = <0x3d800000 0x400000>;
789 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
790 };
791 };
792 };