1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Copyright (C) 2018 Jon Nettleton <jon@solid-run.com>
9 reg_vdd_3v3: regulator-vdd-3v3 {
10 compatible = "regulator-fixed";
12 regulator-name = "vdd_3v3";
13 regulator-min-microvolt = <3300000>;
14 regulator-max-microvolt = <3300000>;
19 pinctrl-names = "default";
20 pinctrl-0 = <&pinctrl_fec1>;
21 phy-mode = "rgmii-id";
22 phy-handle = <ðphy0>;
30 ethphy0: ethernet-phy@4 {
31 compatible = "ethernet-phy-ieee802.3-c22";
33 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
34 reset-assert-us = <2000>;
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_i2c1>;
42 clock-frequency = <400000>;
46 compatible = "fsl,pfuze100";
51 regulator-min-microvolt = <300000>;
52 regulator-max-microvolt = <1875000>;
56 regulator-min-microvolt = <300000>;
57 regulator-max-microvolt = <1875000>;
61 regulator-min-microvolt = <800000>;
62 regulator-max-microvolt = <3300000>;
67 regulator-min-microvolt = <400000>;
68 regulator-max-microvolt = <1975000>;
73 regulator-min-microvolt = <800000>;
74 regulator-max-microvolt = <3300000>;
79 regulator-min-microvolt = <5000000>;
80 regulator-max-microvolt = <5150000>;
84 regulator-min-microvolt = <1000000>;
85 regulator-max-microvolt = <3000000>;
94 regulator-min-microvolt = <800000>;
95 regulator-max-microvolt = <1550000>;
99 regulator-min-microvolt = <800000>;
100 regulator-max-microvolt = <1550000>;
105 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <3300000>;
111 regulator-min-microvolt = <1800000>;
112 regulator-max-microvolt = <3300000>;
117 regulator-min-microvolt = <1800000>;
118 regulator-max-microvolt = <3300000>;
123 regulator-min-microvolt = <1800000>;
124 regulator-max-microvolt = <3300000>;
130 compatible = "atmel,24c01";
137 power-supply = <&sw1a_reg>;
141 power-supply = <&sw1c_reg>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_qspi>;
149 /* SPI flash; not assembled by default */
151 #address-cells = <1>;
154 compatible = "micron,n25q256a", "jedec,spi-nor";
155 spi-max-frequency = <29000000>;
160 &uart1 { /* console */
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_uart1>;
163 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
164 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
165 assigned-clock-rates = <25000000>;
169 &uart4 { /* ublox BT */
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_uart4>;
172 assigned-clocks = <&clk IMX8MQ_CLK_UART4>;
173 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>;
174 assigned-clock-rates = <80000000>;
179 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
180 assigned-clock-rates = <400000000>;
181 pinctrl-names = "default", "state_100mhz", "state_200mhz";
182 pinctrl-0 = <&pinctrl_usdhc1>;
183 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
184 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
191 pinctrl-names = "default";
192 pinctrl-0 = <&pinctrl_wdog>;
193 fsl,ext-reset-output;
198 pinctrl_fec1: fec1grp {
200 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
201 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
202 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
203 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
204 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
205 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
206 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
207 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
208 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
209 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
210 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
211 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
212 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
213 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
214 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
218 pinctrl_i2c1: i2c1grp {
220 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
221 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
225 pinctrl_pcie0: pcie0grp {
227 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x74
228 MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x16
229 MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x16
233 pinctrl_qspi: qspigrp {
235 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
236 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
237 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
238 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
239 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
240 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
245 pinctrl_uart1: uart1grp {
247 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
248 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
249 MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
253 pinctrl_uart4: uart4grp {
255 MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49
256 MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49
257 MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1 0x19
261 pinctrl_usdhc1: usdhc1grp {
263 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
264 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
265 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
266 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
267 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
268 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
269 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
270 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
271 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
272 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
273 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
274 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
278 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
280 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
281 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
282 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
283 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
284 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
285 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
286 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
287 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
288 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
289 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
290 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
291 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
295 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
297 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
298 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
299 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
300 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
301 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
302 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
303 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
304 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
305 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
306 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
307 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
308 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
312 pinctrl_wdog: wdoggrp {
314 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6