WIP FPC-III support
[linux/fpc-iii.git] / arch / arm64 / boot / dts / freescale / imx8qxp-ai_ml.dts
bloba3f8cf1959747c8a7efa730f34e86db44a6777e4
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2018 Einfochips
4  * Copyright 2019 Linaro Ltd.
5  */
7 /dts-v1/;
9 #include "imx8qxp.dtsi"
11 / {
12         model = "Einfochips i.MX8QXP AI_ML";
13         compatible = "einfochips,imx8qxp-ai_ml", "fsl,imx8qxp";
15         aliases {
16                 serial1 = &adma_lpuart1;
17                 serial2 = &adma_lpuart2;
18                 serial3 = &adma_lpuart3;
19         };
21         chosen {
22                 stdout-path = &adma_lpuart2;
23         };
25         memory@80000000 {
26                 device_type = "memory";
27                 reg = <0x00000000 0x80000000 0 0x80000000>;
28         };
30         leds {
31                 compatible = "gpio-leds";
32                 pinctrl-names = "default";
33                 pinctrl-0 = <&pinctrl_leds>;
35                 user-led1 {
36                         label = "green:user1";
37                         gpios = <&lsio_gpio4 16 GPIO_ACTIVE_HIGH>;
38                         linux,default-trigger = "heartbeat";
39                 };
41                 user-led2 {
42                         label = "green:user2";
43                         gpios = <&lsio_gpio0 6 GPIO_ACTIVE_HIGH>;
44                         linux,default-trigger = "none";
45                 };
47                 user-led3 {
48                         label = "green:user3";
49                         gpios = <&lsio_gpio0 7 GPIO_ACTIVE_HIGH>;
50                         linux,default-trigger = "mmc1";
51                         default-state = "off";
52                 };
54                 user-led4 {
55                         label = "green:user4";
56                         gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
57                         panic-indicator;
58                         linux,default-trigger = "none";
59                 };
61                 wlan-active-led {
62                         label = "yellow:wlan";
63                         gpios = <&lsio_gpio4 17 GPIO_ACTIVE_HIGH>;
64                         linux,default-trigger = "phy0tx";
65                         default-state = "off";
66                 };
68                 bt-active-led {
69                         label = "blue:bt";
70                         gpios = <&lsio_gpio4 18 GPIO_ACTIVE_HIGH>;
71                         linux,default-trigger = "hci0-power";
72                         default-state = "off";
73                 };
74         };
76         sdio_pwrseq: sdio-pwrseq {
77                 compatible = "mmc-pwrseq-simple";
78                 pinctrl-names = "default";
79                 pinctrl-0 = <&pinctrl_wifi_reg_on>;
80                 reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_LOW>;
81         };
84 /* BT */
85 &adma_lpuart0 {
86         pinctrl-names = "default";
87         pinctrl-0 = <&pinctrl_lpuart0>;
88         uart-has-rtscts;
89         status = "okay";
92 /* LS-UART0 */
93 &adma_lpuart1 {
94         pinctrl-names = "default";
95         pinctrl-0 = <&pinctrl_lpuart1>;
96         status = "okay";
99 /* Debug */
100 &adma_lpuart2 {
101         pinctrl-names = "default";
102         pinctrl-0 = <&pinctrl_lpuart2>;
103         status = "okay";
106 /* PCI-E UART */
107 &adma_lpuart3 {
108         pinctrl-names = "default";
109         pinctrl-0 = <&pinctrl_lpuart3>;
110         status = "okay";
113 &fec1 {
114         pinctrl-names = "default";
115         pinctrl-0 = <&pinctrl_fec1>;
116         phy-mode = "rgmii-id";
117         phy-handle = <&ethphy0>;
118         fsl,magic-packet;
119         status = "okay";
121         mdio {
122                 #address-cells = <1>;
123                 #size-cells = <0>;
125                 ethphy0: ethernet-phy@0 {
126                         compatible = "ethernet-phy-ieee802.3-c22";
127                         reg = <0>;
128                 };
129         };
132 /* WiFi */
133 &usdhc1 {
134         #address-cells = <1>;
135         #size-cells = <0>;
136         assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>;
137         assigned-clock-rates = <200000000>;
138         pinctrl-names = "default";
139         pinctrl-0 = <&pinctrl_usdhc1>;
140         bus-width = <4>;
141         no-sd;
142         non-removable;
143         mmc-pwrseq = <&sdio_pwrseq>;
144         status = "okay";
146         brcmf: wifi@1 {
147                 reg = <1>;
148                 compatible = "brcm,bcm4329-fmac";
149         };
152 /* SD */
153 &usdhc2 {
154         assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>;
155         assigned-clock-rates = <200000000>;
156         pinctrl-names = "default";
157         pinctrl-0 = <&pinctrl_usdhc2>;
158         bus-width = <4>;
159         cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
160         status = "okay";
163 &iomuxc {
164         pinctrl_fec1: fec1grp {
165                 fsl,pins = <
166                         IMX8QXP_ENET0_MDC_CONN_ENET0_MDC                        0x06000020
167                         IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO                      0x06000020
168                         IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL      0x06000020
169                         IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC            0x06000020
170                         IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0          0x06000020
171                         IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1          0x06000020
172                         IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2          0x06000020
173                         IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3          0x06000020
174                         IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC            0x06000020
175                         IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL      0x06000020
176                         IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0          0x06000020
177                         IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1          0x06000020
178                         IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2          0x06000020
179                         IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3          0x06000020
180                 >;
181         };
183         pinctrl_leds: ledsgrp{
184                 fsl,pins = <
185                         IMX8QXP_ESAI0_TX2_RX3_LSIO_GPIO0_IO06                   0x00000021
186                         IMX8QXP_ESAI0_TX3_RX2_LSIO_GPIO0_IO07                   0x00000021
187                         IMX8QXP_EMMC0_DATA7_LSIO_GPIO4_IO16                     0x00000021
188                         IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21                       0x00000021
189                         IMX8QXP_EMMC0_STROBE_LSIO_GPIO4_IO17                    0x00000021
190                         IMX8QXP_EMMC0_RESET_B_LSIO_GPIO4_IO18                   0x00000021
191                 >;
192         };
194         pinctrl_lpuart0: lpuart0grp {
195                 fsl,pins = <
196                         IMX8QXP_UART0_RX_ADMA_UART0_RX                          0X06000020
197                         IMX8QXP_UART0_TX_ADMA_UART0_TX                          0X06000020
198                         IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B                    0x06000020
199                         IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B                    0x06000020
200                 >;
201         };
203         pinctrl_lpuart1: lpuart1grp {
204                 fsl,pins = <
205                         IMX8QXP_UART1_RX_ADMA_UART1_RX                          0X06000020
206                         IMX8QXP_UART1_TX_ADMA_UART1_TX                          0X06000020
207                 >;
208         };
210         pinctrl_lpuart2: lpuart2grp {
211                 fsl,pins = <
212                         IMX8QXP_UART2_RX_ADMA_UART2_RX                          0X06000020
213                         IMX8QXP_UART2_TX_ADMA_UART2_TX                          0X06000020
214                 >;
215         };
217         pinctrl_lpuart3: lpuart3grp {
218                 fsl,pins = <
219                         IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX                       0X06000020
220                         IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX                       0X06000020
221                 >;
222         };
224         pinctrl_usdhc1: usdhc1grp {
225                 fsl,pins = <
226                         IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK                        0x06000041
227                         IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD                        0x00000021
228                         IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0                    0x00000021
229                         IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1                    0x00000021
230                         IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2                    0x00000021
231                         IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3                    0x00000021
232                 >;
233         };
235         pinctrl_usdhc2: usdhc2grp {
236                 fsl,pins = <
237                         IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK                      0x06000041
238                         IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD                      0x00000021
239                         IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0                  0x00000021
240                         IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1                  0x00000021
241                         IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2                  0x00000021
242                         IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3                  0x00000021
243                         IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT              0x00000021
244                         IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22                     0x00000021
245                 >;
246         };
248         pinctrl_wifi_reg_on: wifiregongrp {
249                 fsl,pins = <
250                         IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24                    0x00000021
251                 >;
252         };