arch/arm64/boot/dts/hisilicon/hip05.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /**
   3  * dts file for Hisilicon D02 Development Board
   4  *
   5  * Copyright (C) 2014,2015 Hisilicon Ltd.
   6  */
   7
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9
  10 / {
  11         compatible = "hisilicon,hip05-d02";
  12         interrupt-parent = <&gic>;
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         psci {
  17                 compatible = "arm,psci-0.2";
  18                 method = "smc";
  19         };
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu-map {
  26                         cluster0 {
  27                                 core0 {
  28                                         cpu = <&cpu0>;
  29                                 };
  30                                 core1 {
  31                                         cpu = <&cpu1>;
  32                                 };
  33                                 core2 {
  34                                         cpu = <&cpu2>;
  35                                 };
  36                                 core3 {
  37                                         cpu = <&cpu3>;
  38                                 };
  39                         };
  40                         cluster1 {
  41                                 core0 {
  42                                         cpu = <&cpu4>;
  43                                 };
  44                                 core1 {
  45                                         cpu = <&cpu5>;
  46                                 };
  47                                 core2 {
  48                                         cpu = <&cpu6>;
  49                                 };
  50                                 core3 {
  51                                         cpu = <&cpu7>;
  52                                 };
  53                         };
  54                         cluster2 {
  55                                 core0 {
  56                                         cpu = <&cpu8>;
  57                                 };
  58                                 core1 {
  59                                         cpu = <&cpu9>;
  60                                 };
  61                                 core2 {
  62                                         cpu = <&cpu10>;
  63                                 };
  64                                 core3 {
  65                                         cpu = <&cpu11>;
  66                                 };
  67                         };
  68                         cluster3 {
  69                                 core0 {
  70                                         cpu = <&cpu12>;
  71                                 };
  72                                 core1 {
  73                                         cpu = <&cpu13>;
  74                                 };
  75                                 core2 {
  76                                         cpu = <&cpu14>;
  77                                 };
  78                                 core3 {
  79                                         cpu = <&cpu15>;
  80                                 };
  81                         };
  82                 };
  83
  84                 cpu0: cpu@20000 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a57";
  87                         reg = <0x20000>;
  88                         enable-method = "psci";
  89                         next-level-cache = <&cluster0_l2>;
  90                 };
  91
  92                 cpu1: cpu@20001 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a57";
  95                         reg = <0x20001>;
  96                         enable-method = "psci";
  97                         next-level-cache = <&cluster0_l2>;
  98                 };
  99
 100                 cpu2: cpu@20002 {
 101                         device_type = "cpu";
 102                         compatible = "arm,cortex-a57";
 103                         reg = <0x20002>;
 104                         enable-method = "psci";
 105                         next-level-cache = <&cluster0_l2>;
 106                 };
 107
 108                 cpu3: cpu@20003 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a57";
 111                         reg = <0x20003>;
 112                         enable-method = "psci";
 113                         next-level-cache = <&cluster0_l2>;
 114                 };
 115
 116                 cpu4: cpu@20100 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a57";
 119                         reg = <0x20100>;
 120                         enable-method = "psci";
 121                         next-level-cache = <&cluster1_l2>;
 122                 };
 123
 124                 cpu5: cpu@20101 {
 125                         device_type = "cpu";
 126                         compatible = "arm,cortex-a57";
 127                         reg = <0x20101>;
 128                         enable-method = "psci";
 129                         next-level-cache = <&cluster1_l2>;
 130                 };
 131
 132                 cpu6: cpu@20102 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a57";
 135                         reg = <0x20102>;
 136                         enable-method = "psci";
 137                         next-level-cache = <&cluster1_l2>;
 138                 };
 139
 140                 cpu7: cpu@20103 {
 141                         device_type = "cpu";
 142                         compatible = "arm,cortex-a57";
 143                         reg = <0x20103>;
 144                         enable-method = "psci";
 145                         next-level-cache = <&cluster1_l2>;
 146                 };
 147
 148                 cpu8: cpu@20200 {
 149                         device_type = "cpu";
 150                         compatible = "arm,cortex-a57";
 151                         reg = <0x20200>;
 152                         enable-method = "psci";
 153                         next-level-cache = <&cluster2_l2>;
 154                 };
 155
 156                 cpu9: cpu@20201 {
 157                         device_type = "cpu";
 158                         compatible = "arm,cortex-a57";
 159                         reg = <0x20201>;
 160                         enable-method = "psci";
 161                         next-level-cache = <&cluster2_l2>;
 162                 };
 163
 164                 cpu10: cpu@20202 {
 165                         device_type = "cpu";
 166                         compatible = "arm,cortex-a57";
 167                         reg = <0x20202>;
 168                         enable-method = "psci";
 169                         next-level-cache = <&cluster2_l2>;
 170                 };
 171
 172                 cpu11: cpu@20203 {
 173                         device_type = "cpu";
 174                         compatible = "arm,cortex-a57";
 175                         reg = <0x20203>;
 176                         enable-method = "psci";
 177                         next-level-cache = <&cluster2_l2>;
 178                 };
 179
 180                 cpu12: cpu@20300 {
 181                         device_type = "cpu";
 182                         compatible = "arm,cortex-a57";
 183                         reg = <0x20300>;
 184                         enable-method = "psci";
 185                         next-level-cache = <&cluster3_l2>;
 186                 };
 187
 188                 cpu13: cpu@20301 {
 189                         device_type = "cpu";
 190                         compatible = "arm,cortex-a57";
 191                         reg = <0x20301>;
 192                         enable-method = "psci";
 193                         next-level-cache = <&cluster3_l2>;
 194                 };
 195
 196                 cpu14: cpu@20302 {
 197                         device_type = "cpu";
 198                         compatible = "arm,cortex-a57";
 199                         reg = <0x20302>;
 200                         enable-method = "psci";
 201                         next-level-cache = <&cluster3_l2>;
 202                 };
 203
 204                 cpu15: cpu@20303 {
 205                         device_type = "cpu";
 206                         compatible = "arm,cortex-a57";
 207                         reg = <0x20303>;
 208                         enable-method = "psci";
 209                         next-level-cache = <&cluster3_l2>;
 210                 };
 211
 212                 cluster0_l2: l2-cache0 {
 213                         compatible = "cache";
 214                 };
 215
 216                 cluster1_l2: l2-cache1 {
 217                         compatible = "cache";
 218                 };
 219
 220                 cluster2_l2: l2-cache2 {
 221                         compatible = "cache";
 222                 };
 223
 224                 cluster3_l2: l2-cache3 {
 225                         compatible = "cache";
 226                 };
 227         };
 228
 229         gic: interrupt-controller@8d000000 {
 230                 compatible = "arm,gic-v3";
 231                 #interrupt-cells = <3>;
 232                 #address-cells = <2>;
 233                 #size-cells = <2>;
 234                 ranges;
 235                 interrupt-controller;
 236                 #redistributor-regions = <1>;
 237                 redistributor-stride = <0x0 0x30000>;
 238                 reg = <0x0 0x8d000000 0 0x10000>,       /* GICD */
 239                       <0x0 0x8d100000 0 0x300000>,      /* GICR */
 240                       <0x0 0xfe000000 0 0x10000>,       /* GICC */
 241                       <0x0 0xfe010000 0 0x10000>,       /* GICH */
 242                       <0x0 0xfe020000 0 0x10000>;       /* GICV */
 243                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 244
 245                 its_peri: msi-controller@8c000000 {
 246                         compatible = "arm,gic-v3-its";
 247                         msi-controller;
 248                         #msi-cells = <1>;
 249                         reg = <0x0 0x8c000000 0x0 0x40000>;
 250                 };
 251
 252                 its_m3: msi-controller@a3000000 {
 253                         compatible = "arm,gic-v3-its";
 254                         msi-controller;
 255                         #msi-cells = <1>;
 256                         reg = <0x0 0xa3000000 0x0 0x40000>;
 257                 };
 258
 259                 its_pcie: msi-controller@b7000000 {
 260                         compatible = "arm,gic-v3-its";
 261                         msi-controller;
 262                         #msi-cells = <1>;
 263                         reg = <0x0 0xb7000000 0x0 0x40000>;
 264                 };
 265
 266                 its_dsa: msi-controller@c6000000 {
 267                         compatible = "arm,gic-v3-its";
 268                         msi-controller;
 269                         #msi-cells = <1>;
 270                         reg = <0x0 0xc6000000 0x0 0x40000>;
 271                 };
 272         };
 273
 274         timer {
 275                 compatible = "arm,armv8-timer";
 276                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 277                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 278                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 279                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 280         };
 281
 282         pmu {
 283                 compatible = "arm,cortex-a57-pmu";
 284                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 285         };
 286
 287         soc {
 288                 compatible = "simple-bus";
 289                 #address-cells = <2>;
 290                 #size-cells = <2>;
 291                 ranges;
 292
 293                 refclk200mhz: refclk200mhz {
 294                         compatible = "fixed-clock";
 295                         #clock-cells = <0>;
 296                         clock-frequency = <200000000>;
 297                 };
 298
 299                 uart0: serial@80300000 {
 300                         compatible = "snps,dw-apb-uart";
 301                         reg = <0x0 0x80300000 0x0 0x10000>;
 302                         interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
 303                         clocks = <&refclk200mhz>, <&refclk200mhz>;
 304                         clock-names = "baudclk", "apb_pclk";
 305                         reg-shift = <2>;
 306                         reg-io-width = <4>;
 307                         status = "disabled";
 308                 };
 309
 310                 uart1: serial@80310000 {
 311                         compatible = "snps,dw-apb-uart";
 312                         reg = <0x0 0x80310000 0x0 0x10000>;
 313                         interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 314                         clocks = <&refclk200mhz>, <&refclk200mhz>;
 315                         clock-names = "baudclk", "apb_pclk";
 316                         reg-shift = <2>;
 317                         reg-io-width = <4>;
 318                         status = "disabled";
 319                 };
 320
 321                 lbc: localbus@80380000 {
 322                         compatible = "hisilicon,hisi-localbus", "simple-bus";
 323                         reg = <0x0 0x80380000 0x0 0x10000>;
 324                         status = "disabled";
 325                 };
 326
 327                 peri_gpio0: gpio@802e0000 {
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         compatible = "snps,dw-apb-gpio";
 331                         reg = <0x0 0x802e0000 0x0 0x10000>;
 332                         status = "disabled";
 333
 334                         porta: gpio-controller@0 {
 335                                 compatible = "snps,dw-apb-gpio-port";
 336                                 gpio-controller;
 337                                 #gpio-cells = <2>;
 338                                 ngpios = <32>;
 339                                 reg = <0>;
 340                                 interrupt-controller;
 341                                 #interrupt-cells = <2>;
 342                                 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
 343                         };
 344                 };
 345
 346                 peri_gpio1: gpio@802f0000 {
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         compatible = "snps,dw-apb-gpio";
 350                         reg = <0x0 0x802f0000 0x0 0x10000>;
 351                         status = "disabled";
 352
 353                         portb: gpio-controller@0 {
 354                                 compatible = "snps,dw-apb-gpio-port";
 355                                 gpio-controller;
 356                                 #gpio-cells = <2>;
 357                                 ngpios = <32>;
 358                                 reg = <0>;
 359                                 interrupt-controller;
 360                                 #interrupt-cells = <2>;
 361                                 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
 362                         };
 363                 };
 364         };
 365 };