arch/arm64/boot/dts/marvell/armada-7040-db.dts

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (C) 2016 Marvell Technology Group Ltd.
   4  *
   5  * Device Tree file for Marvell Armada 7040 Development board platform
   6  */
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include "armada-7040.dtsi"
  10
  11 / {
  12         model = "Marvell Armada 7040 DB board";
  13         compatible = "marvell,armada7040-db", "marvell,armada7040",
  14                      "marvell,armada-ap806-quad", "marvell,armada-ap806";
  15
  16         chosen {
  17                 stdout-path = "serial0:115200n8";
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x0 0x0 0x80000000>;
  23         };
  24
  25         aliases {
  26                 ethernet0 = &cp0_eth0;
  27                 ethernet1 = &cp0_eth1;
  28                 ethernet2 = &cp0_eth2;
  29         };
  30
  31         cp0_exp_usb3_0_current_regulator: gpio-regulator {
  32                 compatible = "regulator-gpio";
  33                 regulator-name = "cp0-usb3-0-current-regulator";
  34                 regulator-type = "current";
  35                 regulator-min-microamp = <500000>;
  36                 regulator-max-microamp = <900000>;
  37                 gpios = <&expander0 4 GPIO_ACTIVE_HIGH>;
  38                 states = <500000 0x0
  39                           900000 0x1>;
  40                 enable-active-high;
  41                 gpios-states = <0>;
  42         };
  43
  44         cp0_exp_usb3_1_current_regulator: gpio-regulator {
  45                 compatible = "regulator-gpio";
  46                 regulator-name = "cp0-usb3-1-current-regulator";
  47                 regulator-type = "current";
  48                 regulator-min-microamp = <500000>;
  49                 regulator-max-microamp = <900000>;
  50                 gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
  51                 states = <500000 0x0
  52                           900000 0x1>;
  53                 enable-active-high;
  54                 gpios-states = <0>;
  55         };
  56
  57         cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
  58                 compatible = "regulator-fixed";
  59                 regulator-name = "usb3h0-vbus";
  60                 regulator-min-microvolt = <5000000>;
  61                 regulator-max-microvolt = <5000000>;
  62                 enable-active-high;
  63                 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
  64                 vin-supply = <&cp0_exp_usb3_0_current_regulator>;
  65         };
  66
  67         cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
  68                 compatible = "regulator-fixed";
  69                 regulator-name = "usb3h1-vbus";
  70                 regulator-min-microvolt = <5000000>;
  71                 regulator-max-microvolt = <5000000>;
  72                 enable-active-high;
  73                 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
  74                 vin-supply = <&cp0_exp_usb3_1_current_regulator>;
  75         };
  76 };
  77
  78 &i2c0 {
  79         status = "okay";
  80         clock-frequency = <100000>;
  81 };
  82
  83 &spi0 {
  84         status = "okay";
  85
  86         spi-flash@0 {
  87                 compatible = "jedec,spi-nor";
  88                 reg = <0>;
  89                 spi-max-frequency = <10000000>;
  90
  91                 partitions {
  92                         compatible = "fixed-partitions";
  93                         #address-cells = <1>;
  94                         #size-cells = <1>;
  95
  96                         partition@0 {
  97                                 label = "U-Boot";
  98                                 reg = <0 0x200000>;
  99                         };
 100                         partition@400000 {
 101                                 label = "Filesystem";
 102                                 reg = <0x200000 0xce0000>;
 103                         };
 104                 };
 105         };
 106 };
 107
 108 &uart0 {
 109         status = "okay";
 110         pinctrl-0 = <&uart0_pins>;
 111         pinctrl-names = "default";
 112 };
 113
 114
 115 &cp0_pcie2 {
 116         status = "okay";
 117         phys = <&cp0_comphy5 2>;
 118         phy-names = "cp0-pcie2-x1-phy";
 119 };
 120
 121 &cp0_i2c0 {
 122         status = "okay";
 123         clock-frequency = <100000>;
 124
 125         expander0: pca9555@21 {
 126                 compatible = "nxp,pca9555";
 127                 pinctrl-names = "default";
 128                 gpio-controller;
 129                 #gpio-cells = <2>;
 130                 reg = <0x21>;
 131                 /*
 132                  * IO0_0: USB3_PWR_EN0  IO1_0: USB_3_1_Dev_Detect
 133                  * IO0_1: USB3_PWR_EN1  IO1_1: USB2_1_current_limit
 134                  * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN
 135                  * IO0_3: USB2_DEVICE_DETECT
 136                  * IO0_4: GPIO_0        IO1_4: SD_Status
 137                  * IO0_5: GPIO_1        IO1_5: LDO_5V_Enable
 138                  * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC
 139                  * IO0_7:               IO1_7: SDIO_Vcntrl
 140                  */
 141         };
 142 };
 143
 144 &cp0_nand_controller {
 145         /*
 146          * SPI on CPM and NAND have common pins on this board. We can
 147          * use only one at a time. To enable the NAND (which will
 148          * disable the SPI), the "status = "okay";" line have to be
 149          * added here.
 150          */
 151         pinctrl-0 = <&nand_pins>, <&nand_rb>;
 152         pinctrl-names = "default";
 153
 154         nand@0 {
 155                 reg = <0>;
 156                 label = "pxa3xx_nand-0";
 157                 nand-rb = <0>;
 158                 nand-on-flash-bbt;
 159                 nand-ecc-strength = <4>;
 160                 nand-ecc-step-size = <512>;
 161
 162                 partitions {
 163                         compatible = "fixed-partitions";
 164                         #address-cells = <1>;
 165                         #size-cells = <1>;
 166
 167                         partition@0 {
 168                                 label = "U-Boot";
 169                                 reg = <0 0x200000>;
 170                         };
 171
 172                         partition@200000 {
 173                                 label = "Linux";
 174                                 reg = <0x200000 0xe00000>;
 175                         };
 176
 177                         partition@1000000 {
 178                                 label = "Filesystem";
 179                                 reg = <0x1000000 0x3f000000>;
 180                         };
 181
 182                 };
 183         };
 184 };
 185
 186 &cp0_spi1 {
 187         status = "okay";
 188
 189         spi-flash@0 {
 190                 compatible = "jedec,spi-nor";
 191                 reg = <0x0>;
 192                 spi-max-frequency = <20000000>;
 193
 194                 partitions {
 195                         compatible = "fixed-partitions";
 196                         #address-cells = <1>;
 197                         #size-cells = <1>;
 198
 199                         partition@0 {
 200                                 label = "U-Boot";
 201                                 reg = <0x0 0x200000>;
 202                         };
 203
 204                         partition@400000 {
 205                                 label = "Filesystem";
 206                                 reg = <0x200000 0xe00000>;
 207                         };
 208                 };
 209         };
 210 };
 211
 212 &cp0_sata0 {
 213         status = "okay";
 214
 215         sata-port@1 {
 216                 phys = <&cp0_comphy3 1>;
 217                 phy-names = "cp0-sata0-1-phy";
 218         };
 219 };
 220
 221 &cp0_comphy1 {
 222         cp0_usbh0_con: connector {
 223                 compatible = "usb-a-connector";
 224                 phy-supply = <&cp0_reg_usb3_0_vbus>;
 225         };
 226 };
 227
 228 &cp0_usb3_0 {
 229         phys = <&cp0_comphy1 0>;
 230         phy-names = "cp0-usb3h0-comphy";
 231         status = "okay";
 232 };
 233
 234 &cp0_comphy4 {
 235         cp0_usbh1_con: connector {
 236                 compatible = "usb-a-connector";
 237                 phy-supply = <&cp0_reg_usb3_1_vbus>;
 238         };
 239 };
 240
 241 &cp0_usb3_1 {
 242         phys = <&cp0_comphy4 1>;
 243         phy-names = "cp0-usb3h1-comphy";
 244         status = "okay";
 245 };
 246
 247 &ap_sdhci0 {
 248         status = "okay";
 249         bus-width = <4>;
 250         no-1-8-v;
 251         non-removable;
 252 };
 253
 254 &cp0_sdhci0 {
 255         status = "okay";
 256         bus-width = <4>;
 257         no-1-8-v;
 258         cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
 259 };
 260
 261 &cp0_mdio {
 262         status = "okay";
 263
 264         phy0: ethernet-phy@0 {
 265                 reg = <0>;
 266         };
 267         phy1: ethernet-phy@1 {
 268                 reg = <1>;
 269         };
 270 };
 271
 272 &cp0_ethernet {
 273         status = "okay";
 274 };
 275
 276 &cp0_eth0 {
 277         status = "okay";
 278         /* Network PHY */
 279         phy-mode = "10gbase-kr";
 280         /* Generic PHY, providing serdes lanes */
 281         phys = <&cp0_comphy2 0>;
 282
 283         fixed-link {
 284                 speed = <10000>;
 285                 full-duplex;
 286         };
 287 };
 288
 289 &cp0_eth1 {
 290         status = "okay";
 291         /* Network PHY */
 292         phy = <&phy0>;
 293         phy-mode = "sgmii";
 294         /* Generic PHY, providing serdes lanes */
 295         phys = <&cp0_comphy0 1>;
 296 };
 297
 298 &cp0_eth2 {
 299         status = "okay";
 300         phy = <&phy1>;
 301         phy-mode = "rgmii-id";
 302 };