WIP FPC-III support
[linux/fpc-iii.git] / arch / arm64 / boot / dts / marvell / armada-80x0.dtsi
blobee67c70bf02efc2396b3a02065b719d7cf68816e
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Copyright (C) 2017 Marvell Technology Group Ltd.
4  *
5  * Device Tree file for the Armada 80x0 SoC family
6  */
8 / {
9         aliases {
10                 gpio1 = &cp1_gpio1;
11                 gpio2 = &cp0_gpio2;
12                 spi1 = &cp0_spi0;
13                 spi2 = &cp0_spi1;
14                 spi3 = &cp1_spi0;
15                 spi4 = &cp1_spi1;
16         };
20  * Instantiate the master CP110
21  */
22 #define CP11X_NAME              cp0
23 #define CP11X_BASE              f2000000
24 #define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
25 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
26 #define CP11X_PCIE0_BASE        f2600000
27 #define CP11X_PCIE1_BASE        f2620000
28 #define CP11X_PCIE2_BASE        f2640000
30 #include "armada-cp110.dtsi"
32 #undef CP11X_NAME
33 #undef CP11X_BASE
34 #undef CP11X_PCIEx_MEM_BASE
35 #undef CP11X_PCIEx_MEM_SIZE
36 #undef CP11X_PCIE0_BASE
37 #undef CP11X_PCIE1_BASE
38 #undef CP11X_PCIE2_BASE
41  * Instantiate the slave CP110
42  */
43 #define CP11X_NAME              cp1
44 #define CP11X_BASE              f4000000
45 #define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
46 #define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
47 #define CP11X_PCIE0_BASE        f4600000
48 #define CP11X_PCIE1_BASE        f4620000
49 #define CP11X_PCIE2_BASE        f4640000
51 #include "armada-cp110.dtsi"
53 #undef CP11X_NAME
54 #undef CP11X_BASE
55 #undef CP11X_PCIEx_MEM_BASE
56 #undef CP11X_PCIEx_MEM_SIZE
57 #undef CP11X_PCIE0_BASE
58 #undef CP11X_PCIE1_BASE
59 #undef CP11X_PCIE2_BASE
61 /* The 80x0 has two CP blocks, but uses only one block from each. */
62 &cp1_gpio1 {
63         status = "okay";
66 &cp0_gpio2 {
67         status = "okay";
70 &cp0_syscon0 {
71         cp0_pinctrl: pinctrl {
72                 compatible = "marvell,armada-8k-cpm-pinctrl";
73         };
76 &cp1_syscon0 {
77         cp1_pinctrl: pinctrl {
78                 compatible = "marvell,armada-8k-cps-pinctrl";
80                 nand_pins: nand-pins {
81                         marvell,pins =
82                         "mpp0", "mpp1", "mpp2", "mpp3",
83                         "mpp4", "mpp5", "mpp6", "mpp7",
84                         "mpp8", "mpp9", "mpp10", "mpp11",
85                         "mpp15", "mpp16", "mpp17", "mpp18",
86                         "mpp19", "mpp20", "mpp21", "mpp22",
87                         "mpp23", "mpp24", "mpp25", "mpp26",
88                         "mpp27";
89                         marvell,function = "dev";
90                 };
92                 nand_rb: nand-rb {
93                         marvell,pins = "mpp13", "mpp12";
94                         marvell,function = "nf";
95                 };
96         };
99 &cp1_crypto {
100         /*
101          * The cryptographic engine found on the cp110
102          * master is enabled by default at the SoC
103          * level. Because it is not possible as of now
104          * to enable two cryptographic engines in
105          * parallel, disable this one by default.
106          */
107         status = "disabled";