WIP FPC-III support
[linux/fpc-iii.git] / arch / arm64 / boot / dts / marvell / armada-ap807-quad.dtsi
blob68782f161f12224f3ec7a79e60d1d61f3d204b20
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3  * Device Tree file for Marvell Armada AP807 Quad
4  *
5  * Copyright (C) 2019 Marvell Technology Group Ltd.
6  */
8 #include "armada-ap807.dtsi"
10 / {
11         model = "Marvell Armada AP807 Quad";
12         compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
14         cpus {
15                 #address-cells = <1>;
16                 #size-cells = <0>;
18                 cpu0: cpu@0 {
19                         device_type = "cpu";
20                         compatible = "arm,cortex-a72";
21                         reg = <0x000>;
22                         enable-method = "psci";
23                         #cooling-cells = <2>;
24                         clocks = <&cpu_clk 0>;
25                         i-cache-size = <0xc000>;
26                         i-cache-line-size = <64>;
27                         i-cache-sets = <256>;
28                         d-cache-size = <0x8000>;
29                         d-cache-line-size = <64>;
30                         d-cache-sets = <256>;
31                         next-level-cache = <&l2_0>;
32                 };
33                 cpu1: cpu@1 {
34                         device_type = "cpu";
35                         compatible = "arm,cortex-a72";
36                         reg = <0x001>;
37                         enable-method = "psci";
38                         #cooling-cells = <2>;
39                         clocks = <&cpu_clk 0>;
40                         i-cache-size = <0xc000>;
41                         i-cache-line-size = <64>;
42                         i-cache-sets = <256>;
43                         d-cache-size = <0x8000>;
44                         d-cache-line-size = <64>;
45                         d-cache-sets = <256>;
46                         next-level-cache = <&l2_0>;
47                 };
48                 cpu2: cpu@100 {
49                         device_type = "cpu";
50                         compatible = "arm,cortex-a72";
51                         reg = <0x100>;
52                         enable-method = "psci";
53                         #cooling-cells = <2>;
54                         clocks = <&cpu_clk 1>;
55                         i-cache-size = <0xc000>;
56                         i-cache-line-size = <64>;
57                         i-cache-sets = <256>;
58                         d-cache-size = <0x8000>;
59                         d-cache-line-size = <64>;
60                         d-cache-sets = <256>;
61                         next-level-cache = <&l2_1>;
62                 };
63                 cpu3: cpu@101 {
64                         device_type = "cpu";
65                         compatible = "arm,cortex-a72";
66                         reg = <0x101>;
67                         enable-method = "psci";
68                         #cooling-cells = <2>;
69                         clocks = <&cpu_clk 1>;
70                         i-cache-size = <0xc000>;
71                         i-cache-line-size = <64>;
72                         i-cache-sets = <256>;
73                         d-cache-size = <0x8000>;
74                         d-cache-line-size = <64>;
75                         d-cache-sets = <256>;
76                         next-level-cache = <&l2_1>;
77                 };
79                 l2_0: l2-cache0 {
80                         compatible = "cache";
81                         cache-size = <0x80000>;
82                         cache-line-size = <64>;
83                         cache-sets = <512>;
84                 };
86                 l2_1: l2-cache1 {
87                         compatible = "cache";
88                         cache-size = <0x80000>;
89                         cache-line-size = <64>;
90                         cache-sets = <512>;
91                 };
92         };